forked from Minki/linux
linux-cpupower-5.12-rc1
This cpupower update for Linux 5.12-rc1 consists of: - Updates to the cpupower command to add support for AMD family 0x19 and cleanup the code to remove many of the family checks to make future family updates easier. - Adding Makefile dependencies for install targets to allow building cpupower in parallel rather than serially. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEPZKym/RZuOCGeA/kCwJExA0NQxwFAmAhYN8ACgkQCwJExA0N Qxz/RBAAr+HWZ13OaLRpuenQuD29p8z+ZrK1opU1lU9Is9w2ck3qIKwyPwVISWy3 x8wlzyQzv6BxHTzSdWJ1IHn/dM8VOAuP3bCBrjrIUhflsX+X7Dst39tZX0Ne4X8z wGt3VFNYr5wbpClhb+Q2Fk1MMPSIte0stVvjsMPeSXZgAB1KPhesTYmnePimwv// kOKXGO3RKHtlfnkcQaljdnsyHalUtmsG48kmL6ex/WCN4D3Aojrlq1bIAfe5U+u0 2iswYcrPiTY536B8E7d76zHyetat945nQ9TR2RRaF8kfEmoyCONFiGejXtSakAdv W1X/5I1egEO5a+oBNpieL7mPIoBZPU0vNXS8/zlYRu1zZ6BvNJ0FSJp1x9mnPME9 16WcAq1uX6A30PlRPErrLqU5QgvQQqcxPKQBPK4kzCB5BBHUpbyunlcWaMmOOZ53 ovV73ulugcaOcXlYrOdMPtD6DyFC2u70REveSq/pUk+L3rR6jEHKWyPXUNpIGsh4 UNidy0bBSp45IbQHws3/e+2QP4Ida6sAqI8L2SnjzULQZtHxBsmffE/ks4WkdTzO D3crtAtTKWciSK6HkVgT+jUQnGWjZabrlqXrrY/jPx86hTwNYZhAgS+D4sx1uGrp r6mN9ye2vb9F/cK/P++I/gzJ7YU10kRdj9LuolvtwPkDFG6gyYk= =pqCu -----END PGP SIGNATURE----- Merge tag 'linux-cpupower-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux Pull cpupower utility update for v5.12-rc1 from Shuah Khan: "This cpupower update for Linux 5.12-rc1 consists of: - Updates to the cpupower command to add support for AMD family 0x19 and cleanup the code to remove many of the family checks to make future family updates easier. - Adding Makefile dependencies for install targets to allow building cpupower in parallel rather than serially." * tag 'linux-cpupower-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux: cpupower: Add cpuid cap flag for MSR_AMD_HWCR support cpupower: Remove family arg to decode_pstates() cpupower: Condense pstate enabled bit checks in decode_pstates() cpupower: Update family checks when decoding HW pstates cpupower: Remove unused pscur variable. cpupower: Add CPUPOWER_CAP_AMD_HW_PSTATE cpuid caps flag cpupower: Correct macro name for CPB caps flag cpupower: Update msr_pstate union struct naming cpupower: add Makefile dependencies for install targets
This commit is contained in:
Rafael J. Wysocki
commit
a51d185681
@ -270,14 +270,14 @@ clean:
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$(MAKE) -C bench O=$(OUTPUT) clean
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install-lib:
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install-lib: libcpupower
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$(INSTALL) -d $(DESTDIR)${libdir}
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$(CP) $(OUTPUT)libcpupower.so* $(DESTDIR)${libdir}/
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$(INSTALL) -d $(DESTDIR)${includedir}
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$(INSTALL_DATA) lib/cpufreq.h $(DESTDIR)${includedir}/cpufreq.h
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$(INSTALL_DATA) lib/cpuidle.h $(DESTDIR)${includedir}/cpuidle.h
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install-tools:
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install-tools: $(OUTPUT)cpupower
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$(INSTALL) -d $(DESTDIR)${bindir}
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$(INSTALL_PROGRAM) $(OUTPUT)cpupower $(DESTDIR)${bindir}
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$(INSTALL) -d $(DESTDIR)${bash_completion_dir}
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@ -293,14 +293,14 @@ install-man:
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$(INSTALL_DATA) -D man/cpupower-info.1 $(DESTDIR)${mandir}/man1/cpupower-info.1
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$(INSTALL_DATA) -D man/cpupower-monitor.1 $(DESTDIR)${mandir}/man1/cpupower-monitor.1
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install-gmo:
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install-gmo: create-gmo
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$(INSTALL) -d $(DESTDIR)${localedir}
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for HLANG in $(LANGUAGES); do \
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echo '$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo'; \
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$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo; \
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done;
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install-bench:
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install-bench: compile-bench
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@#DESTDIR must be set from outside to survive
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@sbindir=$(sbindir) bindir=$(bindir) docdir=$(docdir) confdir=$(confdir) $(MAKE) -C bench O=$(OUTPUT) install
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@ -27,7 +27,7 @@ $(OUTPUT)cpufreq-bench: $(OBJS)
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all: $(OUTPUT)cpufreq-bench
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install:
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install: $(OUTPUT)cpufreq-bench
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mkdir -p $(DESTDIR)/$(sbindir)
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mkdir -p $(DESTDIR)/$(bindir)
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mkdir -p $(DESTDIR)/$(docdir)
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@ -186,8 +186,7 @@ static int get_boost_mode_x86(unsigned int cpu)
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if ((cpupower_cpu_info.vendor == X86_VENDOR_AMD &&
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cpupower_cpu_info.family >= 0x10) ||
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cpupower_cpu_info.vendor == X86_VENDOR_HYGON) {
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ret = decode_pstates(cpu, cpupower_cpu_info.family, b_states,
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pstates, &pstate_no);
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ret = decode_pstates(cpu, b_states, pstates, &pstate_no);
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if (ret)
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return ret;
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@ -13,7 +13,8 @@
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#define MSR_AMD_PSTATE 0xc0010064
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#define MSR_AMD_PSTATE_LIMIT 0xc0010061
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union msr_pstate {
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union core_pstate {
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/* pre fam 17h: */
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struct {
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unsigned fid:6;
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unsigned did:3;
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@ -26,7 +27,8 @@ union msr_pstate {
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unsigned idddiv:2;
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unsigned res3:21;
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unsigned en:1;
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} bits;
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} pstate;
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/* since fam 17h: */
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struct {
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unsigned fid:8;
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unsigned did:6;
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@ -35,37 +37,37 @@ union msr_pstate {
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unsigned idddiv:2;
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unsigned res1:31;
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unsigned en:1;
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} fam17h_bits;
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} pstatedef;
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unsigned long long val;
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};
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static int get_did(int family, union msr_pstate pstate)
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static int get_did(union core_pstate pstate)
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{
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int t;
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if (family == 0x12)
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATEDEF)
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t = pstate.pstatedef.did;
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else if (cpupower_cpu_info.family == 0x12)
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t = pstate.val & 0xf;
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else if (family == 0x17 || family == 0x18)
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t = pstate.fam17h_bits.did;
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else
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t = pstate.bits.did;
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t = pstate.pstate.did;
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return t;
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}
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static int get_cof(int family, union msr_pstate pstate)
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static int get_cof(union core_pstate pstate)
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{
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int t;
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int fid, did, cof;
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did = get_did(family, pstate);
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if (family == 0x17 || family == 0x18) {
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fid = pstate.fam17h_bits.fid;
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did = get_did(pstate);
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATEDEF) {
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fid = pstate.pstatedef.fid;
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cof = 200 * fid / did;
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} else {
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t = 0x10;
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fid = pstate.bits.fid;
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if (family == 0x11)
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fid = pstate.pstate.fid;
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if (cpupower_cpu_info.family == 0x11)
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t = 0x8;
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cof = (100 * (fid + t)) >> did;
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}
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@ -74,8 +76,7 @@ static int get_cof(int family, union msr_pstate pstate)
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/* Needs:
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* cpu -> the cpu that gets evaluated
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* cpu_family -> The cpu's family (0x10, 0x12,...)
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* boots_states -> how much boost states the machines support
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* boost_states -> how much boost states the machines support
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*
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* Fills up:
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* pstates -> a pointer to an array of size MAX_HW_PSTATES
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@ -85,31 +86,23 @@ static int get_cof(int family, union msr_pstate pstate)
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*
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* returns zero on success, -1 on failure
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*/
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int decode_pstates(unsigned int cpu, unsigned int cpu_family,
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int boost_states, unsigned long *pstates, int *no)
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int decode_pstates(unsigned int cpu, int boost_states,
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unsigned long *pstates, int *no)
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{
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int i, psmax, pscur;
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union msr_pstate pstate;
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int i, psmax;
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union core_pstate pstate;
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unsigned long long val;
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/* Only read out frequencies from HW when CPU might be boostable
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to keep the code as short and clean as possible.
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Otherwise frequencies are exported via ACPI tables.
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*/
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if (cpu_family < 0x10 || cpu_family == 0x14)
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/* Only read out frequencies from HW if HW Pstate is supported,
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* otherwise frequencies are exported via ACPI tables.
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*/
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if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_HW_PSTATE))
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return -1;
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if (read_msr(cpu, MSR_AMD_PSTATE_LIMIT, &val))
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return -1;
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psmax = (val >> 4) & 0x7;
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if (read_msr(cpu, MSR_AMD_PSTATE_STATUS, &val))
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return -1;
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pscur = val & 0x7;
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pscur += boost_states;
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psmax += boost_states;
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for (i = 0; i <= psmax; i++) {
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if (i >= MAX_HW_PSTATES) {
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@ -119,12 +112,12 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family,
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}
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if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val))
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return -1;
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if ((cpu_family == 0x17) && (!pstate.fam17h_bits.en))
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continue;
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else if (!pstate.bits.en)
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/* The enabled bit (bit 63) is common for all families */
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if (!pstate.pstatedef.en)
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continue;
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pstates[i] = get_cof(cpu_family, pstate);
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pstates[i] = get_cof(pstate);
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}
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*no = i;
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return 0;
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@ -128,9 +128,23 @@ out:
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/* AMD or Hygon Boost state enable/disable register */
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if (cpu_info->vendor == X86_VENDOR_AMD ||
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cpu_info->vendor == X86_VENDOR_HYGON) {
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if (ext_cpuid_level >= 0x80000007 &&
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(cpuid_edx(0x80000007) & (1 << 9)))
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cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
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if (ext_cpuid_level >= 0x80000007) {
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if (cpuid_edx(0x80000007) & (1 << 9)) {
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cpu_info->caps |= CPUPOWER_CAP_AMD_CPB;
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if (cpu_info->family >= 0x17)
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cpu_info->caps |= CPUPOWER_CAP_AMD_CPB_MSR;
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}
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if ((cpuid_edx(0x80000007) & (1 << 7)) &&
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cpu_info->family != 0x14) {
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/* HW pstate was not implemented in family 0x14 */
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cpu_info->caps |= CPUPOWER_CAP_AMD_HW_PSTATE;
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if (cpu_info->family >= 0x17)
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cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATEDEF;
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}
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}
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if (ext_cpuid_level >= 0x80000008 &&
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cpuid_ebx(0x80000008) & (1 << 4))
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@ -64,12 +64,15 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
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#define CPUPOWER_CAP_INV_TSC 0x00000001
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#define CPUPOWER_CAP_APERF 0x00000002
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#define CPUPOWER_CAP_AMD_CBP 0x00000004
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#define CPUPOWER_CAP_AMD_CPB 0x00000004
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#define CPUPOWER_CAP_PERF_BIAS 0x00000008
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#define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010
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#define CPUPOWER_CAP_IS_SNB 0x00000020
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#define CPUPOWER_CAP_INTEL_IDA 0x00000040
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#define CPUPOWER_CAP_AMD_RDPRU 0x00000080
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#define CPUPOWER_CAP_AMD_HW_PSTATE 0x00000100
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#define CPUPOWER_CAP_AMD_PSTATEDEF 0x00000200
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#define CPUPOWER_CAP_AMD_CPB_MSR 0x00000400
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#define CPUPOWER_AMD_CPBDIS 0x02000000
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@ -125,8 +128,8 @@ extern struct pci_dev *pci_slot_func_init(struct pci_access **pacc,
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/* AMD HW pstate decoding **************************/
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extern int decode_pstates(unsigned int cpu, unsigned int cpu_family,
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int boost_states, unsigned long *pstates, int *no);
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extern int decode_pstates(unsigned int cpu, int boost_states,
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unsigned long *pstates, int *no);
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/* AMD HW pstate decoding **************************/
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@ -143,9 +146,8 @@ unsigned int cpuid_edx(unsigned int op);
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/* cpuid and cpuinfo helpers **************************/
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/* X86 ONLY ********************************************/
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#else
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static inline int decode_pstates(unsigned int cpu, unsigned int cpu_family,
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int boost_states, unsigned long *pstates,
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int *no)
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static inline int decode_pstates(unsigned int cpu, int boost_states,
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unsigned long *pstates, int *no)
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{ return -1; };
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static inline int read_msr(int cpu, unsigned int idx, unsigned long long *val)
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@ -16,17 +16,12 @@
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int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
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int *states)
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{
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struct cpupower_cpu_info cpu_info;
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int ret;
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unsigned long long val;
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*support = *active = *states = 0;
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ret = get_cpu_info(&cpu_info);
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if (ret)
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return ret;
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CPB) {
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*support = 1;
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/* AMD Family 0x17 does not utilize PCI D18F4 like prior
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@ -34,7 +29,7 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
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* has Hardware determined variable increments instead.
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*/
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if (cpu_info.family == 0x17 || cpu_info.family == 0x18) {
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CPB_MSR) {
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if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
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if (!(val & CPUPOWER_AMD_CPBDIS))
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*active = 1;
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