drm/amdkfd: Only apply heavy-weight TLB flush on Aldebaran
It is to workaround HW bug on other Asics and based on reverting two commits back: drm/amdkfd: Add heavy-weight TLB flush after unmapping drm/amdkfd: Add memory sync before TLB flush on unmap Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1570,23 +1570,25 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
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}
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mutex_unlock(&p->mutex);
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err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
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if (err) {
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pr_debug("Sync memory failed, wait interrupted by user signal\n");
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goto sync_memory_failed;
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}
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if (dev->device_info->asic_family == CHIP_ALDEBARAN) {
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err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd,
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(struct kgd_mem *) mem, true);
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if (err) {
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pr_debug("Sync memory failed, wait interrupted by user signal\n");
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goto sync_memory_failed;
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}
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/* Flush TLBs after waiting for the page table updates to complete */
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for (i = 0; i < args->n_devices; i++) {
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peer = kfd_device_by_id(devices_arr[i]);
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if (WARN_ON_ONCE(!peer))
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continue;
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peer_pdd = kfd_get_process_device_data(peer, p);
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if (WARN_ON_ONCE(!peer_pdd))
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continue;
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kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
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/* Flush TLBs after waiting for the page table updates to complete */
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for (i = 0; i < args->n_devices; i++) {
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peer = kfd_device_by_id(devices_arr[i]);
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if (WARN_ON_ONCE(!peer))
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continue;
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peer_pdd = kfd_get_process_device_data(peer, p);
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if (WARN_ON_ONCE(!peer_pdd))
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continue;
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kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
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}
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}
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kfree(devices_arr);
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return 0;
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