forked from Minki/linux
Blackfin EMAC Driver: enable TXDWA new feature for new silicon (rev > 0.2)
Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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d7b843d393
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a50c0c05c3
@ -605,36 +605,87 @@ adjust_head:
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static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
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struct net_device *dev)
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{
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unsigned int data;
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u16 *data;
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current_tx_ptr->skb = skb;
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/*
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* Is skb->data always 16-bit aligned?
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* Do we need to memcpy((char *)(tail->packet + 2), skb->data, len)?
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*/
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if ((((unsigned int)(skb->data)) & 0x02) == 2) {
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/* move skb->data to current_tx_ptr payload */
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data = (unsigned int)(skb->data) - 2;
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*((unsigned short *)data) = (unsigned short)(skb->len);
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current_tx_ptr->desc_a.start_addr = (unsigned long)data;
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/* this is important! */
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blackfin_dcache_flush_range(data, (data + (skb->len)) + 2);
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if (ANOMALY_05000285) {
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/*
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* TXDWA feature is not avaible to older revision < 0.3 silicon
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* of BF537
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*
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* Only if data buffer is ODD WORD alignment, we do not
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* need to memcpy
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*/
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u32 data_align = (u32)(skb->data) & 0x3;
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if (data_align == 0x2) {
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/* move skb->data to current_tx_ptr payload */
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data = (u16 *)(skb->data) - 1;
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*data = (u16)(skb->len);
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current_tx_ptr->desc_a.start_addr = (u32)data;
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/* this is important! */
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blackfin_dcache_flush_range((u32)data,
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(u32)((u8 *)data + skb->len + 4));
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} else {
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*((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
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memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
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skb->len);
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current_tx_ptr->desc_a.start_addr =
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(u32)current_tx_ptr->packet;
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if (current_tx_ptr->status.status_word != 0)
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current_tx_ptr->status.status_word = 0;
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blackfin_dcache_flush_range(
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(u32)current_tx_ptr->packet,
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(u32)(current_tx_ptr->packet + skb->len + 2));
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}
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} else {
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*((unsigned short *)(current_tx_ptr->packet)) =
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(unsigned short)(skb->len);
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memcpy((char *)(current_tx_ptr->packet + 2), skb->data,
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(skb->len));
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current_tx_ptr->desc_a.start_addr =
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(unsigned long)current_tx_ptr->packet;
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if (current_tx_ptr->status.status_word != 0)
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current_tx_ptr->status.status_word = 0;
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blackfin_dcache_flush_range((unsigned int)current_tx_ptr->
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packet,
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(unsigned int)(current_tx_ptr->
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packet + skb->len) +
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2);
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/*
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* TXDWA feature is avaible to revision < 0.3 silicon of
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* BF537 and always avaible to BF52x
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*/
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u32 data_align = (u32)(skb->data) & 0x3;
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if (data_align == 0x0) {
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u16 sysctl = bfin_read_EMAC_SYSCTL();
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sysctl |= TXDWA;
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bfin_write_EMAC_SYSCTL(sysctl);
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/* move skb->data to current_tx_ptr payload */
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data = (u16 *)(skb->data) - 2;
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*data = (u16)(skb->len);
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current_tx_ptr->desc_a.start_addr = (u32)data;
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/* this is important! */
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blackfin_dcache_flush_range(
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(u32)data,
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(u32)((u8 *)data + skb->len + 4));
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} else if (data_align == 0x2) {
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u16 sysctl = bfin_read_EMAC_SYSCTL();
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sysctl &= ~TXDWA;
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bfin_write_EMAC_SYSCTL(sysctl);
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/* move skb->data to current_tx_ptr payload */
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data = (u16 *)(skb->data) - 1;
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*data = (u16)(skb->len);
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current_tx_ptr->desc_a.start_addr = (u32)data;
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/* this is important! */
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blackfin_dcache_flush_range(
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(u32)data,
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(u32)((u8 *)data + skb->len + 4));
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} else {
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u16 sysctl = bfin_read_EMAC_SYSCTL();
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sysctl &= ~TXDWA;
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bfin_write_EMAC_SYSCTL(sysctl);
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*((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
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memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
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skb->len);
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current_tx_ptr->desc_a.start_addr =
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(u32)current_tx_ptr->packet;
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if (current_tx_ptr->status.status_word != 0)
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current_tx_ptr->status.status_word = 0;
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blackfin_dcache_flush_range(
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(u32)current_tx_ptr->packet,
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(u32)(current_tx_ptr->packet + skb->len + 2));
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}
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}
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/* enable this packet's dma */
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