forked from Minki/linux
powerpc/mm: Cleanup LPCR defines
This makes it easy to verify we are not overloading the bits. No functionality change by this patch. mpe: Cleanup more. Completely fixup whitespace, convert all UL values to ASM_CONST(), and replace all occurrences of 63-x with the actual shift. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -330,43 +330,43 @@
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#define HFSCR_FP __MASK(FSCR_FP_LG)
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#define SPRN_TAR 0x32f /* Target Address Register */
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#define SPRN_LPCR 0x13E /* LPAR Control Register */
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#define LPCR_VPM0 (1ul << (63-0))
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#define LPCR_VPM1 (1ul << (63-1))
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#define LPCR_ISL (1ul << (63-2))
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#define LPCR_VC_SH (63-2)
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#define LPCR_DPFD_SH (63-11)
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#define LPCR_DPFD (7ul << LPCR_DPFD_SH)
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#define LPCR_VRMASD (0x1ful << (63-16))
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#define LPCR_VRMA_L (1ul << (63-12))
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#define LPCR_VRMA_LP0 (1ul << (63-15))
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#define LPCR_VRMA_LP1 (1ul << (63-16))
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#define LPCR_VRMASD_SH (63-16)
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#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
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#define LPCR_RMLS_SH (63-37)
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#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
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#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
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#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */
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#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */
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#define LPCR_ONL 0x00040000 /* online - PURR/SPURR count */
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#define LPCR_LD 0x00020000 /* large decremeter */
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#define LPCR_PECE 0x0001f000 /* powersave exit cause enable */
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#define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */
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#define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */
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#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
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#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
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#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */
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#define LPCR_MER 0x00000800 /* Mediated External Exception */
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#define LPCR_MER_SH 11
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#define LPCR_TC 0x00000200 /* Translation control */
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#define LPCR_LPES 0x0000000c
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#define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */
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#define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */
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#define LPCR_LPES_SH 2
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#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */
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#define LPCR_HVICE 0x00000002 /* P9: HV interrupt enable */
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#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */
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#define LPCR_UPRT 0x00400000 /* Use Process Table (ISA 3) */
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#define LPCR_HR 0x00100000
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#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
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#define LPCR_VPM1 ASM_CONST(0x4000000000000000)
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#define LPCR_ISL ASM_CONST(0x2000000000000000)
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#define LPCR_VC_SH 61
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#define LPCR_DPFD_SH 52
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#define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
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#define LPCR_VRMASD_SH 47
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#define LPCR_VRMASD (ASM_CONST(1) << LPCR_VRMASD_SH)
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#define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
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#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
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#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
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#define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit sel */
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#define LPCR_RMLS_SH 26
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#define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
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#define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
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#define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
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#define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */
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#define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
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#define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */
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#define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */
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#define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */
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#define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */
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#define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */
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#define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */
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#define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
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#define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
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#define LPCR_MER_SH 11
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#define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
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#define LPCR_LPES 0x0000000c
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#define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
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#define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */
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#define LPCR_LPES_SH 2
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#define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */
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#define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */
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#define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */
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#define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */
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#define LPCR_HR ASM_CONST(0x0000000000100000)
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#ifndef SPRN_LPID
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#define SPRN_LPID 0x13F /* Logical Partition Identifier */
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#endif
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