forked from Minki/linux
Merge branch 'Add-comphy-support-for-Armada-38x'
Russell King says: ==================== Add comphy support for Armada 38x This series adds support for the comphy for Armada 38x, which allows these SoCs to use 2500BASE-X mode with appropriate SFP modules. Tested on SolidRun Clearfog after updating for the 5.0 merge window changes. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
a4751093a2
@ -19,7 +19,7 @@ Optional properties:
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"marvell,armada-370-neta" and 9800B for others.
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- clock-names: List of names corresponding to clocks property; shall be
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"core" for core clock and "bus" for the optional bus clock.
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- phys: comphy for the ethernet port, see ../phy/phy-bindings.txt
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Optional properties (valid only for Armada XP/38x):
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@ -0,0 +1,40 @@
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mvebu armada 38x comphy driver
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------------------------------
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This comphy controller can be found on Marvell Armada 38x. It provides a
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number of shared PHYs used by various interfaces (network, sata, usb,
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PCIe...).
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Required properties:
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- compatible: should be "marvell,armada-380-comphy"
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- reg: should contain the comphy register location and length.
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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A sub-node is required for each comphy lane provided by the comphy.
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Required properties (child nodes):
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- reg: comphy lane number.
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- #phy-cells : from the generic phy bindings, must be 1. Defines the
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input port to use for a given comphy lane.
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Example:
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comphy: phy@18300 {
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compatible = "marvell,armada-380-comphy";
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reg = <0x18300 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpm_comphy0: phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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cpm_comphy1: phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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};
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@ -93,6 +93,7 @@
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bm,pool-long = <2>;
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bm,pool-short = <1>;
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buffer-manager = <&bm>;
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phys = <&comphy1 1>;
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phy-mode = "sgmii";
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status = "okay";
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};
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@ -103,6 +104,7 @@
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bm,pool-short = <1>;
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buffer-manager = <&bm>;
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managed = "in-band-status";
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phys = <&comphy5 2>;
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phy-mode = "sgmii";
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sfp = <&sfp>;
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status = "okay";
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@ -335,6 +335,43 @@
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#clock-cells = <1>;
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};
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comphy: phy@18300 {
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compatible = "marvell,armada-380-comphy";
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reg = <0x18300 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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comphy0: phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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comphy1: phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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comphy2: phy@2 {
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reg = <2>;
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#phy-cells = <1>;
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};
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comphy3: phy@3 {
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reg = <3>;
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#phy-cells = <1>;
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};
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comphy4: phy@4 {
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reg = <4>;
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#phy-cells = <1>;
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};
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comphy5: phy@5 {
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reg = <5>;
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#phy-cells = <1>;
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};
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};
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coreclk: mvebu-sar@18600 {
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compatible = "marvell,armada-380-core-clock";
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reg = <0x18600 0x04>;
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@ -27,6 +27,7 @@
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include <linux/phy/phy.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <linux/platform_device.h>
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@ -436,6 +437,7 @@ struct mvneta_port {
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struct device_node *dn;
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unsigned int tx_csum_limit;
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struct phylink *phylink;
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struct phy *comphy;
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struct mvneta_bm *bm_priv;
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struct mvneta_bm_pool *pool_long;
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@ -3151,6 +3153,8 @@ static void mvneta_start_dev(struct mvneta_port *pp)
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{
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int cpu;
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WARN_ON(phy_power_on(pp->comphy));
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mvneta_max_rx_size_set(pp, pp->pkt_size);
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mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
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@ -3213,6 +3217,8 @@ static void mvneta_stop_dev(struct mvneta_port *pp)
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mvneta_tx_reset(pp);
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mvneta_rx_reset(pp);
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WARN_ON(phy_power_off(pp->comphy));
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}
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static void mvneta_percpu_enable(void *arg)
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@ -3338,6 +3344,7 @@ static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
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static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
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struct phylink_link_state *state)
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{
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struct mvneta_port *pp = netdev_priv(ndev);
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__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
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/* We only support QSGMII, SGMII, 802.3z and RGMII modes */
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@ -3358,8 +3365,13 @@ static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
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phylink_set(mask, Pause);
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/* Half-duplex at speeds higher than 100Mbit is unsupported */
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if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
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phylink_set(mask, 1000baseT_Full);
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phylink_set(mask, 1000baseX_Full);
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}
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if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
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phylink_set(mask, 2500baseX_Full);
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}
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if (!phy_interface_mode_is_8023z(state->interface)) {
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/* 10M and 100M are only supported in non-802.3z mode */
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@ -3373,6 +3385,11 @@ static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
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__ETHTOOL_LINK_MODE_MASK_NBITS);
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bitmap_and(state->advertising, state->advertising, mask,
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__ETHTOOL_LINK_MODE_MASK_NBITS);
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/* We can only operate at 2500BaseX or 1000BaseX. If requested
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* to advertise both, only report advertising at 2500BaseX.
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*/
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phylink_helper_basex_speed(state);
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}
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static int mvneta_mac_link_state(struct net_device *ndev,
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@ -3384,7 +3401,9 @@ static int mvneta_mac_link_state(struct net_device *ndev,
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gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
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if (gmac_stat & MVNETA_GMAC_SPEED_1000)
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state->speed = SPEED_1000;
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state->speed =
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state->interface == PHY_INTERFACE_MODE_2500BASEX ?
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SPEED_2500 : SPEED_1000;
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else if (gmac_stat & MVNETA_GMAC_SPEED_100)
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state->speed = SPEED_100;
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else
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@ -3499,12 +3518,20 @@ static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
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MVNETA_GMAC_FORCE_LINK_DOWN);
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}
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/* When at 2.5G, the link partner can send frames with shortened
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* preambles.
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*/
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if (state->speed == SPEED_2500)
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new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
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if (pp->comphy &&
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(state->interface == PHY_INTERFACE_MODE_SGMII ||
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state->interface == PHY_INTERFACE_MODE_1000BASEX ||
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state->interface == PHY_INTERFACE_MODE_2500BASEX))
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WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
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state->interface));
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if (new_ctrl0 != gmac_ctrl0)
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mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
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if (new_ctrl2 != gmac_ctrl2)
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@ -4404,7 +4431,7 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
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if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
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mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
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else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
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phy_mode == PHY_INTERFACE_MODE_1000BASEX)
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phy_interface_mode_is_8023z(phy_mode))
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mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
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else if (!phy_interface_mode_is_rgmii(phy_mode))
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return -EINVAL;
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@ -4421,6 +4448,7 @@ static int mvneta_probe(struct platform_device *pdev)
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struct mvneta_port *pp;
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struct net_device *dev;
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struct phylink *phylink;
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struct phy *comphy;
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const char *dt_mac_addr;
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char hw_mac_addr[ETH_ALEN];
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const char *mac_from;
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@ -4446,6 +4474,14 @@ static int mvneta_probe(struct platform_device *pdev)
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goto err_free_irq;
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}
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comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
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if (comphy == ERR_PTR(-EPROBE_DEFER)) {
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err = -EPROBE_DEFER;
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goto err_free_irq;
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} else if (IS_ERR(comphy)) {
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comphy = NULL;
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}
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phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
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&mvneta_phylink_ops);
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if (IS_ERR(phylink)) {
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@ -4462,6 +4498,7 @@ static int mvneta_probe(struct platform_device *pdev)
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pp = netdev_priv(dev);
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spin_lock_init(&pp->lock);
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pp->phylink = phylink;
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pp->comphy = comphy;
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pp->phy_interface = phy_mode;
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pp->dn = dn;
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@ -21,6 +21,16 @@ config PHY_BERLIN_USB
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help
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Enable this to support the USB PHY on Marvell Berlin SoCs.
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config PHY_MVEBU_A38X_COMPHY
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tristate "Marvell Armada 38x comphy driver"
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on OF
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select GENERIC_PHY
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help
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This driver allows to control the comphy, an hardware block providing
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shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be
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used by various controllers (Ethernet, sata, usb, PCIe...).
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config PHY_MVEBU_CP110_COMPHY
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tristate "Marvell CP110 comphy driver"
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depends on ARCH_MVEBU || COMPILE_TEST
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@ -2,6 +2,7 @@
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obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
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obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
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obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
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obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY) += phy-armada38x-comphy.o
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obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
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obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
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obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
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237
drivers/phy/marvell/phy-armada38x-comphy.c
Normal file
237
drivers/phy/marvell/phy-armada38x-comphy.c
Normal file
@ -0,0 +1,237 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Russell King, Deep Blue Solutions Ltd.
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*
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* Partly derived from CP110 comphy driver by Antoine Tenart
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* <antoine.tenart@bootlin.com>
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*/
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#define MAX_A38X_COMPHY 6
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#define MAX_A38X_PORTS 3
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#define COMPHY_CFG1 0x00
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#define COMPHY_CFG1_GEN_TX(x) ((x) << 26)
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#define COMPHY_CFG1_GEN_TX_MSK COMPHY_CFG1_GEN_TX(15)
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#define COMPHY_CFG1_GEN_RX(x) ((x) << 22)
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#define COMPHY_CFG1_GEN_RX_MSK COMPHY_CFG1_GEN_RX(15)
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#define GEN_SGMII_1_25GBPS 6
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#define GEN_SGMII_3_125GBPS 8
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#define COMPHY_STAT1 0x18
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#define COMPHY_STAT1_PLL_RDY_TX BIT(3)
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#define COMPHY_STAT1_PLL_RDY_RX BIT(2)
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#define COMPHY_SELECTOR 0xfc
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struct a38x_comphy;
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struct a38x_comphy_lane {
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void __iomem *base;
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struct a38x_comphy *priv;
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unsigned int n;
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|
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int port;
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};
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|
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struct a38x_comphy {
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void __iomem *base;
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struct device *dev;
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struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
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};
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|
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static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = {
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{ 0, 0, 0 },
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{ 4, 5, 0 },
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{ 0, 4, 0 },
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{ 0, 0, 4 },
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{ 0, 3, 0 },
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{ 0, 0, 3 },
|
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};
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|
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static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane,
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unsigned int offset, u32 mask, u32 value)
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{
|
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u32 val;
|
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|
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val = readl_relaxed(lane->base + offset) & ~mask;
|
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writel(val | value, lane->base + offset);
|
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}
|
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|
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static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane,
|
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unsigned int gen_tx, unsigned int gen_rx)
|
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{
|
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a38x_comphy_set_reg(lane, COMPHY_CFG1,
|
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COMPHY_CFG1_GEN_TX_MSK | COMPHY_CFG1_GEN_RX_MSK,
|
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COMPHY_CFG1_GEN_TX(gen_tx) |
|
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COMPHY_CFG1_GEN_RX(gen_rx));
|
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}
|
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|
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static int a38x_comphy_poll(struct a38x_comphy_lane *lane,
|
||||
unsigned int offset, u32 mask, u32 value)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val,
|
||||
(val & mask) == value,
|
||||
1000, 150000);
|
||||
|
||||
if (ret)
|
||||
dev_err(lane->priv->dev,
|
||||
"comphy%u: timed out waiting for status\n", lane->n);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* We only support changing the speed for comphys configured for GBE.
|
||||
* Since that is all we do, we only poll for PLL ready status.
|
||||
*/
|
||||
static int a38x_comphy_set_mode(struct phy *phy, enum phy_mode mode, int sub)
|
||||
{
|
||||
struct a38x_comphy_lane *lane = phy_get_drvdata(phy);
|
||||
unsigned int gen;
|
||||
|
||||
if (mode != PHY_MODE_ETHERNET)
|
||||
return -EINVAL;
|
||||
|
||||
switch (sub) {
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
case PHY_INTERFACE_MODE_1000BASEX:
|
||||
gen = GEN_SGMII_1_25GBPS;
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_2500BASEX:
|
||||
gen = GEN_SGMII_3_125GBPS;
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
a38x_comphy_set_speed(lane, gen, gen);
|
||||
|
||||
return a38x_comphy_poll(lane, COMPHY_STAT1,
|
||||
COMPHY_STAT1_PLL_RDY_TX |
|
||||
COMPHY_STAT1_PLL_RDY_RX,
|
||||
COMPHY_STAT1_PLL_RDY_TX |
|
||||
COMPHY_STAT1_PLL_RDY_RX);
|
||||
}
|
||||
|
||||
static const struct phy_ops a38x_comphy_ops = {
|
||||
.set_mode = a38x_comphy_set_mode,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct phy *a38x_comphy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct a38x_comphy_lane *lane;
|
||||
struct phy *phy;
|
||||
u32 val;
|
||||
|
||||
if (WARN_ON(args->args[0] >= MAX_A38X_PORTS))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
phy = of_phy_simple_xlate(dev, args);
|
||||
if (IS_ERR(phy))
|
||||
return phy;
|
||||
|
||||
lane = phy_get_drvdata(phy);
|
||||
if (lane->port >= 0)
|
||||
return ERR_PTR(-EBUSY);
|
||||
|
||||
lane->port = args->args[0];
|
||||
|
||||
val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR);
|
||||
val = (val >> (4 * lane->n)) & 0xf;
|
||||
|
||||
if (!gbe_mux[lane->n][lane->port] ||
|
||||
val != gbe_mux[lane->n][lane->port]) {
|
||||
dev_warn(lane->priv->dev,
|
||||
"comphy%u: not configured for GBE\n", lane->n);
|
||||
phy = ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
||||
static int a38x_comphy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct phy_provider *provider;
|
||||
struct device_node *child;
|
||||
struct a38x_comphy *priv;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
priv->dev = &pdev->dev;
|
||||
priv->base = base;
|
||||
|
||||
for_each_available_child_of_node(pdev->dev.of_node, child) {
|
||||
struct phy *phy;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = of_property_read_u32(child, "reg", &val);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
|
||||
ret);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (val >= MAX_A38X_COMPHY || priv->lane[val].base) {
|
||||
dev_err(&pdev->dev, "invalid 'reg' property\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops);
|
||||
if (IS_ERR(phy))
|
||||
return PTR_ERR(phy);
|
||||
|
||||
priv->lane[val].base = base + 0x28 * val;
|
||||
priv->lane[val].priv = priv;
|
||||
priv->lane[val].n = val;
|
||||
priv->lane[val].port = -1;
|
||||
phy_set_drvdata(phy, &priv->lane[val]);
|
||||
}
|
||||
|
||||
dev_set_drvdata(&pdev->dev, priv);
|
||||
|
||||
provider = devm_of_phy_provider_register(&pdev->dev, a38x_comphy_xlate);
|
||||
|
||||
return PTR_ERR_OR_ZERO(provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id a38x_comphy_of_match_table[] = {
|
||||
{ .compatible = "marvell,armada-380-comphy" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, a38x_comphy_of_match_table);
|
||||
|
||||
static struct platform_driver a38x_comphy_driver = {
|
||||
.probe = a38x_comphy_probe,
|
||||
.driver = {
|
||||
.name = "armada-38x-comphy",
|
||||
.of_match_table = a38x_comphy_of_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(a38x_comphy_driver);
|
||||
|
||||
MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>");
|
||||
MODULE_DESCRIPTION("Common PHY driver for Armada 38x SoCs");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user