forked from Minki/linux
USB: EHCI: define extension registers like normal ones
This patch (as1562) cleans up the definitions of the EHCI extended registers to be consistent with the definitions of the standard registers. This makes the code look a lot nicer, with no functional change. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alan Stern
Greg Kroah-Hartman
parent
cf61fdb944
commit
a46af4ebf9
@ -203,11 +203,9 @@ static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
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/* check TDI/ARC silicon is in host mode */
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static int tdi_in_host_mode (struct ehci_hcd *ehci)
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{
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u32 __iomem *reg_ptr;
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u32 tmp;
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reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
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tmp = ehci_readl(ehci, reg_ptr);
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tmp = ehci_readl(ehci, &ehci->regs->usbmode);
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return (tmp & 3) == USBMODE_CM_HC;
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}
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@ -303,11 +301,9 @@ static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
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/* put TDI/ARC silicon into EHCI mode */
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static void tdi_reset (struct ehci_hcd *ehci)
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{
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u32 __iomem *reg_ptr;
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u32 tmp;
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reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
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tmp = ehci_readl(ehci, reg_ptr);
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tmp = ehci_readl(ehci, &ehci->regs->usbmode);
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tmp |= USBMODE_CM_HC;
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/* The default byte access to MMR space is LE after
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* controller reset. Set the required endian mode
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@ -315,7 +311,7 @@ static void tdi_reset (struct ehci_hcd *ehci)
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*/
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if (ehci_big_endian_mmio(ehci))
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tmp |= USBMODE_BE;
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ehci_writel(ehci, tmp, reg_ptr);
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ehci_writel(ehci, tmp, &ehci->regs->usbmode);
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}
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/* reset a non-running (STS_HALT == 1) controller */
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@ -339,9 +335,8 @@ static int ehci_reset (struct ehci_hcd *ehci)
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if (ehci->has_hostpc) {
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ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
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(u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
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ehci_writel(ehci, TXFIFO_DEFAULT,
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(u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
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&ehci->regs->usbmode_ex);
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ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
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}
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if (retval)
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return retval;
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@ -149,10 +149,8 @@ static __maybe_unused void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
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if (ehci->has_hostpc) {
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port = HCS_N_PORTS(ehci->hcs_params);
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while (port--) {
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u32 __iomem *hostpc_reg;
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u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
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hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
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+ HOSTPC0 + 4 * port);
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temp = ehci_readl(ehci, hostpc_reg);
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ehci_writel(ehci, temp & ~HOSTPC_PHCD, hostpc_reg);
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}
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@ -185,10 +183,8 @@ static __maybe_unused void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
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if (ehci->has_hostpc) {
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port = HCS_N_PORTS(ehci->hcs_params);
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while (port--) {
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u32 __iomem *hostpc_reg;
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u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
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hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
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+ HOSTPC0 + 4 * port);
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temp = ehci_readl(ehci, hostpc_reg);
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ehci_writel(ehci, temp | HOSTPC_PHCD, hostpc_reg);
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}
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@ -285,11 +281,9 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
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port = HCS_N_PORTS(ehci->hcs_params);
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while (port--) {
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u32 __iomem *hostpc_reg;
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u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
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u32 t3;
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hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
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+ HOSTPC0 + 4 * port);
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t3 = ehci_readl(ehci, hostpc_reg);
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ehci_writel(ehci, t3 | HOSTPC_PHCD, hostpc_reg);
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t3 = ehci_readl(ehci, hostpc_reg);
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@ -388,10 +382,9 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
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i = HCS_N_PORTS(ehci->hcs_params);
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while (i--) {
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if (test_bit(i, &ehci->bus_suspended)) {
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u32 __iomem *hostpc_reg;
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u32 __iomem *hostpc_reg =
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&ehci->regs->hostpc[i];
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hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
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+ HOSTPC0 + 4 * i);
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temp = ehci_readl(ehci, hostpc_reg);
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ehci_writel(ehci, temp & ~HOSTPC_PHCD,
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hostpc_reg);
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@ -667,7 +660,7 @@ static int ehci_hub_control (
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int ports = HCS_N_PORTS (ehci->hcs_params);
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u32 __iomem *status_reg = &ehci->regs->port_status[
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(wIndex & 0xff) - 1];
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u32 __iomem *hostpc_reg = NULL;
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u32 __iomem *hostpc_reg = &ehci->regs->hostpc[(wIndex & 0xff) - 1];
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u32 temp, temp1, status;
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unsigned long flags;
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int retval = 0;
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@ -680,9 +673,6 @@ static int ehci_hub_control (
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* power, "this is the one", etc. EHCI spec supports this.
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*/
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if (ehci->has_hostpc)
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hostpc_reg = (u32 __iomem *)((u8 *)ehci->regs
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+ HOSTPC0 + 4 * ((wIndex & 0xff) - 1));
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spin_lock_irqsave (&ehci->lock, flags);
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switch (typeReq) {
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case ClearHubFeature:
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@ -734,7 +724,7 @@ static int ehci_hub_control (
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goto error;
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/* clear phy low-power mode before resume */
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if (hostpc_reg) {
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if (ehci->has_hostpc) {
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temp1 = ehci_readl(ehci, hostpc_reg);
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ehci_writel(ehci, temp1 & ~HOSTPC_PHCD,
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hostpc_reg);
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@ -984,7 +974,7 @@ static int ehci_hub_control (
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temp &= ~PORT_WKCONN_E;
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temp |= PORT_WKDISC_E | PORT_WKOC_E;
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ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
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if (hostpc_reg) {
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if (ehci->has_hostpc) {
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spin_unlock_irqrestore(&ehci->lock, flags);
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msleep(5);/* 5ms for HCD enter low pwr mode */
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spin_lock_irqsave(&ehci->lock, flags);
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@ -111,7 +111,13 @@ struct ehci_regs {
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/* ASYNCLISTADDR: offset 0x18 */
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u32 async_next; /* address of next async queue head */
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u32 reserved[9];
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u32 reserved1[2];
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/* TXFILLTUNING: offset 0x24 */
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u32 txfill_tuning; /* TX FIFO Tuning register */
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#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
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u32 reserved2[6];
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/* CONFIGFLAG: offset 0x40 */
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u32 configured_flag;
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@ -155,26 +161,34 @@ struct ehci_regs {
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#define PORT_CSC (1<<1) /* connect status change */
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#define PORT_CONNECT (1<<0) /* device connected */
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#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
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};
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#define USBMODE 0x68 /* USB Device mode */
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u32 reserved3[9];
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/* USBMODE: offset 0x68 */
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u32 usbmode; /* USB Device mode */
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#define USBMODE_SDIS (1<<3) /* Stream disable */
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#define USBMODE_BE (1<<2) /* BE/LE endianness select */
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#define USBMODE_CM_HC (3<<0) /* host controller mode */
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#define USBMODE_CM_IDLE (0<<0) /* idle state */
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u32 reserved4[7];
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/* Moorestown has some non-standard registers, partially due to the fact that
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* its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
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* PORTSCx
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*/
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#define HOSTPC0 0x84 /* HOSTPC extension */
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/* HOSTPC: offset 0x84 */
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u32 hostpc[0]; /* HOSTPC extension */
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#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
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#define HOSTPC_PSPD (3<<25) /* Port speed detection */
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#define USBMODE_EX 0xc8 /* USB Device mode extension */
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u32 reserved5[17];
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/* USBMODE_EX: offset 0xc8 */
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u32 usbmode_ex; /* USB Device mode extension */
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#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
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#define USBMODE_EX_HC (3<<0) /* host controller mode */
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#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
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#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
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};
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/* Appendix C, Debug port ... intended for use with special "debug devices"
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* that can help if there's no serial console. (nonstandard enumeration.)
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