powerpc/pseries: Stop selecting PPC_HASH_MMU_NATIVE
The pseries platform does not use the native hash code but the PAPR virtualised hash interfaces, so remove PPC_HASH_MMU_NATIVE. This requires moving tlbiel code from hash_native.c to hash_utils.c. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20211201144153.2456614-4-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin
Michael Ellerman
parent
7ebc49031d
commit
a4135cbebd
@ -14,7 +14,6 @@ enum {
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TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
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};
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#ifdef CONFIG_PPC_NATIVE
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static inline void tlbiel_all(void)
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{
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/*
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@ -30,9 +29,6 @@ static inline void tlbiel_all(void)
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else
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hash__tlbiel_all(TLB_INVAL_SCOPE_GLOBAL);
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}
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#else
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static inline void tlbiel_all(void) { BUG(); }
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#endif
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static inline void tlbiel_all_lpid(bool radix)
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{
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@ -43,110 +43,6 @@
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static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
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static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is)
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{
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unsigned long rb;
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rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
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asm volatile("tlbiel %0" : : "r" (rb));
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}
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/*
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* tlbiel instruction for hash, set invalidation
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* i.e., r=1 and is=01 or is=10 or is=11
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*/
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static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is,
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unsigned int pid,
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unsigned int ric, unsigned int prs)
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{
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unsigned long rb;
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unsigned long rs;
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unsigned int r = 0; /* hash format */
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rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
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rs = ((unsigned long)pid << PPC_BITLSHIFT(31));
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asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)
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: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)
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: "memory");
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}
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static void tlbiel_all_isa206(unsigned int num_sets, unsigned int is)
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{
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unsigned int set;
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asm volatile("ptesync": : :"memory");
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for (set = 0; set < num_sets; set++)
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tlbiel_hash_set_isa206(set, is);
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ppc_after_tlbiel_barrier();
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}
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static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
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{
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unsigned int set;
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asm volatile("ptesync": : :"memory");
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/*
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* Flush the partition table cache if this is HV mode.
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*/
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if (early_cpu_has_feature(CPU_FTR_HVMODE))
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tlbiel_hash_set_isa300(0, is, 0, 2, 0);
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/*
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* Now invalidate the process table cache. UPRT=0 HPT modes (what
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* current hardware implements) do not use the process table, but
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* add the flushes anyway.
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*
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* From ISA v3.0B p. 1078:
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* The following forms are invalid.
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* * PRS=1, R=0, and RIC!=2 (The only process-scoped
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* HPT caching is of the Process Table.)
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*/
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tlbiel_hash_set_isa300(0, is, 0, 2, 1);
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/*
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* Then flush the sets of the TLB proper. Hash mode uses
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* partition scoped TLB translations, which may be flushed
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* in !HV mode.
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*/
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for (set = 0; set < num_sets; set++)
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tlbiel_hash_set_isa300(set, is, 0, 0, 0);
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ppc_after_tlbiel_barrier();
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asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");
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}
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void hash__tlbiel_all(unsigned int action)
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{
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unsigned int is;
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switch (action) {
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case TLB_INVAL_SCOPE_GLOBAL:
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is = 3;
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break;
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case TLB_INVAL_SCOPE_LPID:
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is = 2;
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break;
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default:
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BUG();
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}
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if (early_cpu_has_feature(CPU_FTR_ARCH_300))
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tlbiel_all_isa300(POWER9_TLB_SETS_HASH, is);
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else if (early_cpu_has_feature(CPU_FTR_ARCH_207S))
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tlbiel_all_isa206(POWER8_TLB_SETS, is);
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else if (early_cpu_has_feature(CPU_FTR_ARCH_206))
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tlbiel_all_isa206(POWER7_TLB_SETS, is);
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else
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WARN(1, "%s called on pre-POWER7 CPU\n", __func__);
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}
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static inline unsigned long ___tlbie(unsigned long vpn, int psize,
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int apsize, int ssize)
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{
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@ -175,6 +175,110 @@ static struct mmu_psize_def mmu_psize_defaults_gp[] = {
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},
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};
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static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is)
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{
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unsigned long rb;
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rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
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asm volatile("tlbiel %0" : : "r" (rb));
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}
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/*
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* tlbiel instruction for hash, set invalidation
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* i.e., r=1 and is=01 or is=10 or is=11
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*/
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static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is,
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unsigned int pid,
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unsigned int ric, unsigned int prs)
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{
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unsigned long rb;
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unsigned long rs;
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unsigned int r = 0; /* hash format */
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rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
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rs = ((unsigned long)pid << PPC_BITLSHIFT(31));
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asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)
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: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)
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: "memory");
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}
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static void tlbiel_all_isa206(unsigned int num_sets, unsigned int is)
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{
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unsigned int set;
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asm volatile("ptesync": : :"memory");
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for (set = 0; set < num_sets; set++)
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tlbiel_hash_set_isa206(set, is);
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ppc_after_tlbiel_barrier();
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}
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static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
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{
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unsigned int set;
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asm volatile("ptesync": : :"memory");
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/*
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* Flush the partition table cache if this is HV mode.
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*/
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if (early_cpu_has_feature(CPU_FTR_HVMODE))
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tlbiel_hash_set_isa300(0, is, 0, 2, 0);
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/*
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* Now invalidate the process table cache. UPRT=0 HPT modes (what
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* current hardware implements) do not use the process table, but
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* add the flushes anyway.
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*
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* From ISA v3.0B p. 1078:
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* The following forms are invalid.
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* * PRS=1, R=0, and RIC!=2 (The only process-scoped
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* HPT caching is of the Process Table.)
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*/
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tlbiel_hash_set_isa300(0, is, 0, 2, 1);
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/*
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* Then flush the sets of the TLB proper. Hash mode uses
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* partition scoped TLB translations, which may be flushed
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* in !HV mode.
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*/
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for (set = 0; set < num_sets; set++)
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tlbiel_hash_set_isa300(set, is, 0, 0, 0);
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ppc_after_tlbiel_barrier();
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asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");
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}
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void hash__tlbiel_all(unsigned int action)
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{
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unsigned int is;
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switch (action) {
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case TLB_INVAL_SCOPE_GLOBAL:
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is = 3;
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break;
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case TLB_INVAL_SCOPE_LPID:
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is = 2;
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break;
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default:
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BUG();
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}
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if (early_cpu_has_feature(CPU_FTR_ARCH_300))
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tlbiel_all_isa300(POWER9_TLB_SETS_HASH, is);
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else if (early_cpu_has_feature(CPU_FTR_ARCH_207S))
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tlbiel_all_isa206(POWER8_TLB_SETS, is);
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else if (early_cpu_has_feature(CPU_FTR_ARCH_206))
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tlbiel_all_isa206(POWER7_TLB_SETS, is);
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else
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WARN(1, "%s called on pre-POWER7 CPU\n", __func__);
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}
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/*
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* 'R' and 'C' update notes:
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* - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
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@ -17,7 +17,6 @@ config PPC_PSERIES
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select PPC_RTAS_DAEMON
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select RTAS_ERROR_LOGGING
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select PPC_UDBG_16550
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select PPC_HASH_MMU_NATIVE
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select PPC_DOORBELL
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select HOTPLUG_CPU
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select ARCH_RANDOM
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