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-----------
  - Use STiH418's A9 PLL
  - Add Ethernet support to STiH407 family
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Merge tag 'sti-dt-for-v4.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/dt

Merge "STi DT changes for v4.4, round 2" from Maxime Coquelin:

 - Use STiH418's A9 PLL
 - Add Ethernet support to STiH407 family

* tag 'sti-dt-for-v4.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
  ARM: STi: DT: Add support for stih418 A9 pll
  ARM: dts: Enable Ethernet on STi's B2199 board
  ARM: dts: Enable Ethernet on STi's B2120 boards
  ARM: dts: Add Ethernet node to STiH407 family
  ARM: dts: Fix RGMII pinctrl timings
This commit is contained in:
Arnd Bergmann 2015-10-23 22:04:49 +02:00
commit a3de778b1f
7 changed files with 46 additions and 3 deletions
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1
arch/arm/boot/dts/stih407-b2120.dts
View File

@ -25,6 +25,7 @@
aliases {
ttyAS0 = &sbc_serial0;
ethernet0 = &ethernet0;
};
};

27
arch/arm/boot/dts/stih407-family.dtsi
View File

@ -653,5 +653,32 @@
clocks = <&clk_sysin>;
status = "okay";
};
ethernet0: dwmac@9630000 {
device_type = "network";
status = "disabled";
compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
reg = <0x9630000 0x8000>, <0x80 0x4>;
reg-names = "stmmaceth", "sti-ethconf";
st,syscon = <&syscfg_sbc_reg 0x80>;
st,gmac_en;
resets = <&softreset STIH407_ETH1_SOFTRESET>;
reset-names = "stmmaceth";
interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
<GIC_SPI 99 IRQ_TYPE_NONE>;
interrupt-names = "macirq", "eth_wake_irq";
/* DMA Bus Mode */
snps,pbl = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1>;
clock-names = "stmmaceth", "sti-ethclk";
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
<&clk_s_c0_flexgen CLK_ETH_PHY>;
};
};
};

4
arch/arm/boot/dts/stih407-pinctrl.dtsi
View File

@ -216,9 +216,9 @@
rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
};
};

1
arch/arm/boot/dts/stih410-b2120.dts
View File

@ -25,6 +25,7 @@
aliases {
ttyAS0 = &sbc_serial0;
ethernet0 = &ethernet0;
};
soc {

8
arch/arm/boot/dts/stih418-b2199.dts
View File

@ -24,6 +24,7 @@
aliases {
ttyAS0 = &sbc_serial0;
ethernet0 = &ethernet0;
};
soc {
@ -101,5 +102,12 @@
st_dwc3: dwc3@8f94000 {
status = "okay";
};
ethernet0: dwmac@9630000 {
st,tx-retime-src = "clkgen";
status = "okay";
phy-mode = "rgmii";
fixed-link = <0 1 1000 0 0>;
};
};
};

2
arch/arm/boot/dts/stih418-clock.dtsi
View File

@ -44,7 +44,7 @@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;

6
arch/arm/boot/dts/stihxxx-b2120.dtsi
View File

@ -87,5 +87,11 @@
status = "okay";
};
ethernet0: dwmac@9630000 {
st,tx-retime-src = "clkgen";
status = "okay";
phy-mode = "rgmii";
fixed-link = <0 1 1000 0 0>;
};
};
};