forked from Minki/linux
clk: mediatek: Add new clkmux register API
On both MT8183 & MT6765, there add "set/clr" register for each clkmux setting, and one update register to trigger value change. It is designed to prevent read-modify-write racing issue. The sw design need to add a new API to handle this hw change with a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> [sboyd@kernel.org: Squash in flags=0 to silence warning] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
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commit
a3ae549917
@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
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obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
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obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
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obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
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obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
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obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
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obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
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obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
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223
drivers/clk/mediatek/clk-mux.c
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223
drivers/clk/mediatek/clk-mux.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/mfd/syscon.h>
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#include "clk-mtk.h"
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#include "clk-mux.h"
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static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_clk_mux, hw);
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}
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static int mtk_clk_mux_enable(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = BIT(mux->data->gate_shift);
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return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
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mask, ~mask);
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}
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static void mtk_clk_mux_disable(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = BIT(mux->data->gate_shift);
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regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
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}
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static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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return regmap_write(mux->regmap, mux->data->clr_ofs,
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BIT(mux->data->gate_shift));
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}
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static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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regmap_write(mux->regmap, mux->data->set_ofs,
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BIT(mux->data->gate_shift));
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}
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static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val;
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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return (val & BIT(mux->data->gate_shift)) == 0;
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}
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static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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u32 val;
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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val = (val >> mux->data->mux_shift) & mask;
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return val;
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}
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static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
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index << mux->data->mux_shift);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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u32 val, orig;
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
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val = (orig & ~(mask << mux->data->mux_shift))
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| (index << mux->data->mux_shift);
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if (val != orig) {
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regmap_write(mux->regmap, mux->data->clr_ofs,
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mask << mux->data->mux_shift);
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regmap_write(mux->regmap, mux->data->set_ofs,
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index << mux->data->mux_shift);
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if (mux->data->upd_shift >= 0)
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regmap_write(mux->regmap, mux->data->upd_ofs,
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BIT(mux->data->upd_shift));
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}
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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const struct clk_ops mtk_mux_ops = {
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_lock,
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};
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const struct clk_ops mtk_mux_clr_set_upd_ops = {
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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};
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const struct clk_ops mtk_mux_gate_ops = {
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.enable = mtk_clk_mux_enable,
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.disable = mtk_clk_mux_disable,
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.is_enabled = mtk_clk_mux_is_enabled,
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_lock,
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};
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const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
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.enable = mtk_clk_mux_enable_setclr,
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.disable = mtk_clk_mux_disable_setclr,
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.is_enabled = mtk_clk_mux_is_enabled,
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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};
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struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
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struct regmap *regmap,
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spinlock_t *lock)
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{
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struct mtk_clk_mux *clk_mux;
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struct clk_init_data init;
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struct clk *clk;
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clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
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if (!clk_mux)
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return ERR_PTR(-ENOMEM);
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init.name = mux->name;
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init.flags = mux->flags | CLK_SET_RATE_PARENT;
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init.parent_names = mux->parent_names;
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init.num_parents = mux->num_parents;
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init.ops = mux->ops;
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clk_mux->regmap = regmap;
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clk_mux->data = mux;
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clk_mux->lock = lock;
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clk_mux->hw.init = &init;
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clk = clk_register(NULL, &clk_mux->hw);
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if (IS_ERR(clk)) {
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kfree(clk_mux);
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return clk;
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}
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return clk;
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}
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int mtk_clk_register_muxes(const struct mtk_mux *muxes,
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int num, struct device_node *node,
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spinlock_t *lock,
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struct clk_onecell_data *clk_data)
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{
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struct regmap *regmap;
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struct clk *clk;
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int i;
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regmap = syscon_node_to_regmap(node);
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if (IS_ERR(regmap)) {
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pr_err("Cannot find regmap for %pOF: %ld\n", node,
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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for (i = 0; i < num; i++) {
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const struct mtk_mux *mux = &muxes[i];
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if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
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clk = mtk_clk_register_mux(mux, regmap, lock);
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if (IS_ERR(clk)) {
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pr_err("Failed to register clk %s: %ld\n",
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mux->name, PTR_ERR(clk));
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continue;
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}
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clk_data->clks[mux->id] = clk;
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}
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}
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return 0;
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}
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89
drivers/clk/mediatek/clk-mux.h
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89
drivers/clk/mediatek/clk-mux.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_MUX_H
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#define __DRV_CLK_MTK_MUX_H
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#include <linux/clk-provider.h>
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struct mtk_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
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const struct mtk_mux *data;
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spinlock_t *lock;
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};
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struct mtk_mux {
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int id;
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const char *name;
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const char * const *parent_names;
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unsigned int flags;
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u32 mux_ofs;
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u32 set_ofs;
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u32 clr_ofs;
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u32 upd_ofs;
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u8 mux_shift;
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u8 mux_width;
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u8 gate_shift;
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s8 upd_shift;
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const struct clk_ops *ops;
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signed char num_parents;
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};
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extern const struct clk_ops mtk_mux_ops;
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extern const struct clk_ops mtk_mux_clr_set_upd_ops;
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extern const struct clk_ops mtk_mux_gate_ops;
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extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
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#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, _ops) { \
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.id = _id, \
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.name = _name, \
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.mux_ofs = _mux_ofs, \
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.set_ofs = _mux_set_ofs, \
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.clr_ofs = _mux_clr_ofs, \
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.upd_ofs = _upd_ofs, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_shift = _gate, \
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.upd_shift = _upd, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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.ops = &_ops, \
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}
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#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags) \
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GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, \
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mtk_mux_gate_clr_set_upd_ops)
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#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd) \
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MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
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_width, _gate, _upd_ofs, _upd, \
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CLK_SET_RATE_PARENT)
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struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
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struct regmap *regmap,
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spinlock_t *lock);
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int mtk_clk_register_muxes(const struct mtk_mux *muxes,
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int num, struct device_node *node,
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spinlock_t *lock,
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struct clk_onecell_data *clk_data);
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#endif /* __DRV_CLK_MTK_MUX_H */
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