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AT91: pm: make sure that r0 is 0 when dealing with cache operations

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When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Nicolas Ferre 2010-10-22 18:55:39 +02:00
parent 8aeeda822f
commit a2a571b74a
3 changed files with 10 additions and 3 deletions
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9
arch/arm/mach-at91/pm.c
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@ -261,8 +261,13 @@ static int at91_pm_enter(suspend_state_t state)
* For ARM 926 based chips, this requirement is weaker
* as at91sam9 can access a RAM in self-refresh mode.
*/
asm("b 1f; .align 5; 1:");
asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
asm volatile ( "mov r0, #0\n\t"
"b 1f\n\t"
".align 5\n\t"
"1: mcr p15, 0, r0, c7, c10, 4\n\t"
: /* no output */
: /* no input */
: "r0");
saved_lpr = sdram_selfrefresh_enable();
wait_for_interrupt_enable();
sdram_selfrefresh_disable(saved_lpr);

3
arch/arm/mach-at91/pm.h
View File

@ -21,7 +21,8 @@ static inline u32 sdram_selfrefresh_enable(void)
}
#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4")
#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
: : "r" (0))
#elif defined(CONFIG_ARCH_AT91CAP9)
#include <mach/at91cap9_ddrsdr.h>

1
arch/arm/mach-at91/pm_slowclock.S
View File

@ -124,6 +124,7 @@ ENTRY(at91_slow_clock)
ldr r5, .at91_va_base_ramc1
/* Drain write buffer */
mov r0, #0
mcr p15, 0, r0, c7, c10, 4
#ifdef CONFIG_ARCH_AT91RM9200