MIPS: PCI: Byteswap not needed in little-endian mode
Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which is a better description for its functionality. When compiled in big-endian mode, xlp_config_pci_bswap() will configure the PCIe links to byteswap. In little-endian mode, no swap configuration is needed for the PCIe controller, and the function is empty. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4802/ Signed-off-by: John Crispin <blogic@openwrt.org>
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@ -191,7 +191,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
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return 0;
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return 0;
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}
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}
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static int xlp_enable_pci_bswap(void)
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/*
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* If big-endian, enable hardware byteswap on the PCIe bridges.
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* This will make both the SoC and PCIe devices behave consistently with
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* readl/writel.
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*/
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#ifdef __BIG_ENDIAN
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static void xlp_config_pci_bswap(void)
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{
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{
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uint64_t pciebase, sysbase;
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uint64_t pciebase, sysbase;
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int node, i;
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int node, i;
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@ -222,8 +228,11 @@ static int xlp_enable_pci_bswap(void)
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reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
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reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
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nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
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nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
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}
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}
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return 0;
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}
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}
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#else
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/* Swap configuration not needed in little-endian mode */
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static inline void xlp_config_pci_bswap(void) {}
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#endif /* __BIG_ENDIAN */
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static int __init pcibios_init(void)
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static int __init pcibios_init(void)
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{
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{
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@ -235,7 +244,7 @@ static int __init pcibios_init(void)
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ioport_resource.start = 0;
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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ioport_resource.end = ~0;
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xlp_enable_pci_bswap();
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xlp_config_pci_bswap();
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set_io_port_base(CKSEG1);
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set_io_port_base(CKSEG1);
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nlm_pci_controller.io_map_base = CKSEG1;
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nlm_pci_controller.io_map_base = CKSEG1;
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