ath11k: Add qcn9074 mhi controller config
Add MHI config for QCN9074 also populate ath11k_hw_params for QCN9074. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-6-git-send-email-akolli@codeaurora.org
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@ -147,6 +147,18 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.cold_boot_calib = false,
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.supports_suspend = true,
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},
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{
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.name = "qcn9074 hw1.0",
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.hw_rev = ATH11K_HW_QCN9074_HW10,
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.fw = {
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.dir = "QCN9074/hw1.0",
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.board_size = 256 * 1024,
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.cal_size = 256 * 1024,
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},
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.max_radios = 1,
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.single_pdev_only = false,
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.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
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},
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};
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int ath11k_core_suspend(struct ath11k_base *ab)
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@ -105,6 +105,7 @@ enum ath11k_hw_rev {
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ATH11K_HW_IPQ8074,
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ATH11K_HW_QCA6390_HW20,
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ATH11K_HW_IPQ6018_HW10,
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ATH11K_HW_QCN9074_HW10,
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};
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enum ath11k_firmware_mode {
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@ -7,10 +7,11 @@
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#include "core.h"
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#include "debug.h"
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#include "mhi.h"
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#include "pci.h"
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#define MHI_TIMEOUT_DEFAULT_MS 90000
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static struct mhi_channel_config ath11k_mhi_channels[] = {
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static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
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{
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.num = 0,
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.name = "LOOPBACK",
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@ -69,7 +70,7 @@ static struct mhi_channel_config ath11k_mhi_channels[] = {
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},
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};
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static struct mhi_event_config ath11k_mhi_events[] = {
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static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
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{
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.num_elements = 32,
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.irq_moderation_ms = 0,
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@ -92,15 +93,108 @@ static struct mhi_event_config ath11k_mhi_events[] = {
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},
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};
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static struct mhi_controller_config ath11k_mhi_config = {
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static struct mhi_controller_config ath11k_mhi_config_qca6390 = {
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.max_channels = 128,
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.timeout_ms = 2000,
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.use_bounce_buf = false,
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.buf_len = 0,
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.num_channels = ARRAY_SIZE(ath11k_mhi_channels),
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.ch_cfg = ath11k_mhi_channels,
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.num_events = ARRAY_SIZE(ath11k_mhi_events),
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.event_cfg = ath11k_mhi_events,
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.num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
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.ch_cfg = ath11k_mhi_channels_qca6390,
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.num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
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.event_cfg = ath11k_mhi_events_qca6390,
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};
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static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
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{
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.num = 0,
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.name = "LOOPBACK",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_TO_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 1,
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.name = "LOOPBACK",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 20,
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.name = "IPCR",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_TO_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 21,
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.name = "IPCR",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = true,
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},
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};
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static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
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{
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.num_elements = 32,
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.irq_moderation_ms = 0,
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.irq = 1,
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.data_type = MHI_ER_CTRL,
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.mode = MHI_DB_BRST_DISABLE,
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.hardware_event = false,
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.client_managed = false,
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.offload_channel = false,
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},
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{
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.num_elements = 256,
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.irq_moderation_ms = 1,
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.irq = 2,
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.mode = MHI_DB_BRST_DISABLE,
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.priority = 1,
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.hardware_event = false,
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.client_managed = false,
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.offload_channel = false,
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},
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};
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static struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
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.max_channels = 30,
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.timeout_ms = 10000,
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.use_bounce_buf = false,
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.buf_len = 0,
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.num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
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.ch_cfg = ath11k_mhi_channels_qcn9074,
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.num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
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.event_cfg = ath11k_mhi_events_qcn9074,
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};
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void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
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@ -221,6 +315,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
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{
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struct ath11k_base *ab = ab_pci->ab;
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struct mhi_controller *mhi_ctrl;
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struct mhi_controller_config *ath11k_mhi_config;
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int ret;
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mhi_ctrl = mhi_alloc_controller();
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@ -254,7 +349,12 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
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mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
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mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
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ret = mhi_register_controller(mhi_ctrl, &ath11k_mhi_config);
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if (ab->hw_rev == ATH11K_HW_QCA6390_HW20)
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ath11k_mhi_config = &ath11k_mhi_config_qca6390;
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else if (ab->hw_rev == ATH11K_HW_QCN9074_HW10)
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ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
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ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
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if (ret) {
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ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
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mhi_free_controller(mhi_ctrl);
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@ -21,6 +21,7 @@
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#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02
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#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01
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#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02
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#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07
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#define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32
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#define ATH11K_QMI_RESP_LEN_MAX 8192
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#define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52
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