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ARM: iop32x: merge everything into mach-iop32x/

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Various bits of iop32x are now in their traditional locations in plat-iop,
mach-iop/include/mach/ and in include/asm/mach/hardware. As nothing
outside of the iop32x mach code references these any more, this can all
be moved into one place now.

The only remaining things in the include/mach/ directory are now the
NR_IRQS definition, the entry-macros.S file and the the decompressor
uart access. After the irqchip code has been converted to SPARSE_IRQ
and GENERIC_IRQ_MULTI_HANDLER, it can be moved to ARCH_MULTIPLATFORM.

Link: https://lore.kernel.org/r/20190809163334.489360-7-arnd@arndb.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-08-09 18:33:21 +02:00
parent ba9ef6afc4
commit a1f487d75c
28 changed files with 102 additions and 125 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Makefile
View File

@ -229,7 +229,6 @@ plat-$(CONFIG_ARCH_EXYNOS) += samsung
plat-$(CONFIG_ARCH_OMAP) += omap
plat-$(CONFIG_ARCH_S3C64XX) += samsung
plat-$(CONFIG_ARCH_S5PV210) += samsung
plat-$(CONFIG_PLAT_IOP) += iop
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += samsung

10
arch/arm/mach-iop32x/Makefile
View File

@ -3,7 +3,15 @@
# Makefile for the linux kernel.
#
obj-y := irq.o
obj-$(CONFIG_ARCH_IOP32X) += irq.o
obj-$(CONFIG_ARCH_IOP32X) += i2c.o
obj-$(CONFIG_ARCH_IOP32X) += pci.o
obj-$(CONFIG_ARCH_IOP32X) += setup.o
obj-$(CONFIG_ARCH_IOP32X) += time.o
obj-$(CONFIG_ARCH_IOP32X) += cp6.o
obj-$(CONFIG_ARCH_IOP32X) += adma.o
obj-$(CONFIG_ARCH_IOP32X) += pmu.o
obj-$(CONFIG_ARCH_IOP32X) += restart.o
obj-$(CONFIG_MACH_GLANTANK) += glantank.o
obj-$(CONFIG_ARCH_IQ80321) += iq80321.o

4
arch/arm/plat-iop/adma.c → arch/arm/mach-iop32x/adma.c
View File

@ -4,10 +4,12 @@
* Copyright © 2006, Intel Corporation.
*/
#include <linux/platform_device.h>
#include <asm/hardware/iop3xx.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/dma-iop32x.h>
#include "iop3xx.h"
#include "irqs.h"
#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR

0
arch/arm/plat-iop/cp6.c → arch/arm/mach-iop32x/cp6.c
View File

5
arch/arm/mach-iop32x/em7210.c
View File

@ -21,7 +21,6 @@
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/mach/arch.h>
@ -29,8 +28,10 @@
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <mach/time.h>
#include "hardware.h"
#include "gpio-iop32x.h"
#include "irqs.h"
static void __init em7210_timer_init(void)
{

5
arch/arm/mach-iop32x/glantank.c
View File

@ -22,7 +22,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -30,8 +29,10 @@
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <mach/time.h>
#include "hardware.h"
#include "gpio-iop32x.h"
#include "irqs.h"
/*
* GLAN Tank timer tick configuration.

2
arch/arm/mach-iop32x/include/mach/glantank.h → arch/arm/mach-iop32x/glantank.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/glantank.h
*
* IO-Data GLAN Tank board registers
*/

6
arch/arm/mach-iop32x/include/mach/hardware.h → arch/arm/mach-iop32x/hardware.h
View File

@ -1,8 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/hardware.h
*/
#ifndef __HARDWARE_H
#define __HARDWARE_H
@ -28,7 +24,7 @@ void iop32x_init_irq(void);
/*
* Generic chipset bits
*/
#include "iop32x.h"
#include "iop3xx.h"
/*
* Board specific bits

6
arch/arm/plat-iop/i2c.c → arch/arm/mach-iop32x/i2c.c
View File

@ -22,10 +22,12 @@
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/hardware/iop3xx.h>
#include <asm/mach/arch.h>
#include "hardware.h"
#include "iop3xx.h"
#include "irqs.h"
/*
* Each of the I2C busses have corresponding GPIO lines, and the driver
* need to access these directly to drive the bus low at times.

2
arch/arm/mach-iop32x/include/mach/entry-macro.S
View File

@ -7,8 +7,6 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/iop32x.h>
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)

31
arch/arm/mach-iop32x/include/mach/iop32x.h
View File

@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-iop32x/include/mach/iop32x.h
*
* Intel IOP32X Chip definitions
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
* Copyright (C) 2004 Intel Corp.
*/
#ifndef __IOP32X_H
#define __IOP32X_H
/*
* Peripherals that are shared between the iop32x and iop33x but
* located at different addresses.
*/
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
#include <asm/hardware/iop3xx.h>
/* ATU Parameters
* set up a 1:1 bus to physical ram relationship
* w/ physical ram on top of pci in the memory map
*/
#define IOP32X_MAX_RAM_SIZE 0x40000000UL
#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
#endif

33
arch/arm/mach-iop32x/include/mach/irqs.h
View File

@ -9,39 +9,6 @@
#ifndef __IRQS_H
#define __IRQS_H
/*
* IOP80321 chipset interrupts
*/
#define IRQ_IOP32X_DMA0_EOT 0
#define IRQ_IOP32X_DMA0_EOC 1
#define IRQ_IOP32X_DMA1_EOT 2
#define IRQ_IOP32X_DMA1_EOC 3
#define IRQ_IOP32X_AA_EOT 6
#define IRQ_IOP32X_AA_EOC 7
#define IRQ_IOP32X_CORE_PMON 8
#define IRQ_IOP32X_TIMER0 9
#define IRQ_IOP32X_TIMER1 10
#define IRQ_IOP32X_I2C_0 11
#define IRQ_IOP32X_I2C_1 12
#define IRQ_IOP32X_MESSAGING 13
#define IRQ_IOP32X_ATU_BIST 14
#define IRQ_IOP32X_PERFMON 15
#define IRQ_IOP32X_CORE_PMU 16
#define IRQ_IOP32X_BIU_ERR 17
#define IRQ_IOP32X_ATU_ERR 18
#define IRQ_IOP32X_MCU_ERR 19
#define IRQ_IOP32X_DMA0_ERR 20
#define IRQ_IOP32X_DMA1_ERR 21
#define IRQ_IOP32X_AA_ERR 23
#define IRQ_IOP32X_MSG_ERR 24
#define IRQ_IOP32X_SSP 25
#define IRQ_IOP32X_XINT0 27
#define IRQ_IOP32X_XINT1 28
#define IRQ_IOP32X_XINT2 29
#define IRQ_IOP32X_XINT3 30
#define IRQ_IOP32X_HPI 31
#define NR_IRQS 32
#endif

5
arch/arm/mach-iop32x/include/mach/time.h
View File

@ -1,5 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP32X_TIME_H_
#define _IOP32X_TIME_H_
#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0
#endif

18
arch/arm/include/asm/hardware/iop3xx.h → arch/arm/mach-iop32x/iop3xx.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/iop3xx.h
*
* Intel IOP32X and IOP33X register definitions
*
* Author: Rory Bolt <rorybolt@pacbell.net>
@ -12,6 +10,22 @@
#ifndef __IOP3XX_H
#define __IOP3XX_H
/*
* Peripherals that are shared between the iop32x and iop33x but
* located at different addresses.
*/
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
#include "iop3xx.h"
/* ATU Parameters
* set up a 1:1 bus to physical ram relationship
* w/ physical ram on top of pci in the memory map
*/
#define IOP32X_MAX_RAM_SIZE 0x40000000UL
#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
/*
* IOP3XX GPIO handling
*/

5
arch/arm/mach-iop32x/iq31244.c
View File

@ -23,7 +23,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/cputype.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
@ -33,7 +32,9 @@
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "hardware.h"
#include "irqs.h"
#include "gpio-iop32x.h"
/*

2
arch/arm/mach-iop32x/include/mach/iq31244.h → arch/arm/mach-iop32x/iq31244.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/iq31244.h
*
* Intel IQ31244 evaluation board registers
*/

5
arch/arm/mach-iop32x/iq80321.c
View File

@ -20,7 +20,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -29,7 +28,9 @@
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "hardware.h"
#include "irqs.h"
#include "gpio-iop32x.h"
/*

2
arch/arm/mach-iop32x/include/mach/iq80321.h → arch/arm/mach-iop32x/iq80321.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/iq80321.h
*
* Intel IQ80321 evaluation board registers
*/

3
arch/arm/mach-iop32x/irq.c
View File

@ -13,9 +13,10 @@
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include "hardware.h"
static u32 iop32x_mask;
static void intctl_write(u32 val)

42
arch/arm/mach-iop32x/irqs.h Normal file
View File

@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright: (C) 2002 Rory Bolt
*/
#ifndef __IOP32X_IRQS_H
#define __IOP32X_IRQS_H
/*
* IOP80321 chipset interrupts
*/
#define IRQ_IOP32X_DMA0_EOT 0
#define IRQ_IOP32X_DMA0_EOC 1
#define IRQ_IOP32X_DMA1_EOT 2
#define IRQ_IOP32X_DMA1_EOC 3
#define IRQ_IOP32X_AA_EOT 6
#define IRQ_IOP32X_AA_EOC 7
#define IRQ_IOP32X_CORE_PMON 8
#define IRQ_IOP32X_TIMER0 9
#define IRQ_IOP32X_TIMER1 10
#define IRQ_IOP32X_I2C_0 11
#define IRQ_IOP32X_I2C_1 12
#define IRQ_IOP32X_MESSAGING 13
#define IRQ_IOP32X_ATU_BIST 14
#define IRQ_IOP32X_PERFMON 15
#define IRQ_IOP32X_CORE_PMU 16
#define IRQ_IOP32X_BIU_ERR 17
#define IRQ_IOP32X_ATU_ERR 18
#define IRQ_IOP32X_MCU_ERR 19
#define IRQ_IOP32X_DMA0_ERR 20
#define IRQ_IOP32X_DMA1_ERR 21
#define IRQ_IOP32X_AA_ERR 23
#define IRQ_IOP32X_MSG_ERR 24
#define IRQ_IOP32X_SSP 25
#define IRQ_IOP32X_XINT0 27
#define IRQ_IOP32X_XINT1 28
#define IRQ_IOP32X_XINT2 29
#define IRQ_IOP32X_XINT3 30
#define IRQ_IOP32X_HPI 31
#endif

5
arch/arm/mach-iop32x/n2100.c
View File

@ -28,7 +28,6 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -37,7 +36,9 @@
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "hardware.h"
#include "irqs.h"
#include "gpio-iop32x.h"
/*

2
arch/arm/mach-iop32x/include/mach/n2100.h → arch/arm/mach-iop32x/n2100.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/n2100.h
*
* Thecus N2100 board registers
*/

4
arch/arm/plat-iop/pci.c → arch/arm/mach-iop32x/pci.c
View File

@ -17,9 +17,9 @@
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/signal.h>
#include <mach/hardware.h>
#include <asm/mach/pci.h>
#include <asm/hardware/iop3xx.h>
#include "hardware.h"
#include "iop3xx.h"
// #define DEBUG

2
arch/arm/plat-iop/pmu.c → arch/arm/mach-iop32x/pmu.c
View File

@ -5,7 +5,7 @@
*/
#include <linux/platform_device.h>
#include <mach/irqs.h>
#include "irqs.h"
static struct resource pmu_resource = {
.start = IRQ_IOP32X_CORE_PMU,

4
arch/arm/plat-iop/restart.c → arch/arm/mach-iop32x/restart.c
View File

@ -4,9 +4,9 @@
*
* Copyright (C) 2001 MontaVista Software, Inc.
*/
#include <asm/hardware/iop3xx.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include "hardware.h"
#include "iop3xx.h"
void iop3xx_restart(enum reboot_mode mode, const char *cmd)
{

2
arch/arm/plat-iop/setup.c → arch/arm/mach-iop32x/setup.c
View File

@ -10,7 +10,7 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <asm/hardware/iop3xx.h>
#include "iop3xx.h"
/*
* Standard IO mapping for all IOP3xx based systems. Note that

7
arch/arm/plat-iop/time.c → arch/arm/mach-iop32x/time.c
View File

@ -19,12 +19,13 @@
#include <linux/clockchips.h>
#include <linux/export.h>
#include <linux/sched_clock.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <linux/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/time.h>
#include "hardware.h"
#include "irqs.h"
/*
* Minimum clocksource/clockevent timer range in seconds
@ -167,7 +168,7 @@ void __init iop_init_time(unsigned long tick_rate)
*/
write_tmr0(timer_ctl & ~IOP_TMR_EN);
write_tisr(1);
setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
setup_irq(IRQ_IOP32X_TIMER0, &iop_timer_irq);
iop_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&iop_clockevent, tick_rate,
0xf, 0xfffffffe);

14
arch/arm/plat-iop/Makefile
View File

@ -1,14 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the linux kernel.
#
# IOP32X
obj-$(CONFIG_ARCH_IOP32X) += i2c.o
obj-$(CONFIG_ARCH_IOP32X) += pci.o
obj-$(CONFIG_ARCH_IOP32X) += setup.o
obj-$(CONFIG_ARCH_IOP32X) += time.o
obj-$(CONFIG_ARCH_IOP32X) += cp6.o
obj-$(CONFIG_ARCH_IOP32X) += adma.o
obj-$(CONFIG_ARCH_IOP32X) += pmu.o
obj-$(CONFIG_ARCH_IOP32X) += restart.o