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crypto: caam - select DMA address size at runtime

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i.MX8 mScale SoC still use 32-bit addresses in its CAAM implmentation,
so we can't rely on sizeof(dma_addr_t) to detemine CAAM pointer
size. Convert the code to query CTPR and MCFGR for that during driver
probing.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Spencer <christopher.spencer@sea.co.uk>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Horia Geantă <horia.geanta@nxp.com>
Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Andrey Smirnov 2019-08-20 13:23:59 -07:00 committed by Herbert Xu
parent dff36801a9
commit a1cf573ee9
7 changed files with 63 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/crypto/caam/caampkc.c
View File

@ -17,13 +17,13 @@
#include "sg_sw_sec4.h"
#include "caampkc.h"
#define DESC_RSA_PUB_LEN (2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))
#define DESC_RSA_PUB_LEN (2 * CAAM_CMD_SZ + SIZEOF_RSA_PUB_PDB)
#define DESC_RSA_PRIV_F1_LEN (2 * CAAM_CMD_SZ + \
sizeof(struct rsa_priv_f1_pdb))
SIZEOF_RSA_PRIV_F1_PDB)
#define DESC_RSA_PRIV_F2_LEN (2 * CAAM_CMD_SZ + \
sizeof(struct rsa_priv_f2_pdb))
SIZEOF_RSA_PRIV_F2_PDB)
#define DESC_RSA_PRIV_F3_LEN (2 * CAAM_CMD_SZ + \
sizeof(struct rsa_priv_f3_pdb))
SIZEOF_RSA_PRIV_F3_PDB)
#define CAAM_RSA_MAX_INPUT_SIZE 512 /* for a 4096-bit modulus */
/* buffer filled with zeros, used for padding */

5
drivers/crypto/caam/ctrl.c
View File

@ -602,7 +602,10 @@ static int caam_probe(struct platform_device *pdev)
caam_imx = (bool)imx_soc_match;
comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
caam_ptr_sz = sizeof(dma_addr_t);
if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
caam_ptr_sz = sizeof(u64);
else
caam_ptr_sz = sizeof(u32);
caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);

10
drivers/crypto/caam/desc_constr.h
View File

@ -136,9 +136,15 @@ static inline void init_job_desc_pdb(u32 * const desc, u32 options,
static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
if (caam_ptr_sz == sizeof(dma_addr_t)) {
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
*offset = cpu_to_caam_dma(ptr);
*offset = cpu_to_caam_dma(ptr);
} else {
u32 *offset = (u32 *)desc_end(desc);
*offset = cpu_to_caam_dma(ptr);
}
(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
CAAM_PTR_SZ / CAAM_CMD_SZ);

2
drivers/crypto/caam/intern.h
View File

@ -219,7 +219,7 @@ static inline u64 caam_get_dma_mask(struct device *dev)
{
struct device_node *nprop = dev->of_node;
if (sizeof(dma_addr_t) != sizeof(u64))
if (caam_ptr_sz != sizeof(u64))
return DMA_BIT_MASK(32);
if (caam_dpaa2)

16
drivers/crypto/caam/pdb.h
View File

@ -512,7 +512,9 @@ struct rsa_pub_pdb {
dma_addr_t n_dma;
dma_addr_t e_dma;
u32 f_len;
} __packed;
};
#define SIZEOF_RSA_PUB_PDB (2 * sizeof(u32) + 4 * caam_ptr_sz)
/**
* RSA Decrypt PDB - Private Key Form #1
@ -528,7 +530,9 @@ struct rsa_priv_f1_pdb {
dma_addr_t f_dma;
dma_addr_t n_dma;
dma_addr_t d_dma;
} __packed;
};
#define SIZEOF_RSA_PRIV_F1_PDB (sizeof(u32) + 4 * caam_ptr_sz)
/**
* RSA Decrypt PDB - Private Key Form #2
@ -554,7 +558,9 @@ struct rsa_priv_f2_pdb {
dma_addr_t tmp1_dma;
dma_addr_t tmp2_dma;
u32 p_q_len;
} __packed;
};
#define SIZEOF_RSA_PRIV_F2_PDB (2 * sizeof(u32) + 7 * caam_ptr_sz)
/**
* RSA Decrypt PDB - Private Key Form #3
@ -586,6 +592,8 @@ struct rsa_priv_f3_pdb {
dma_addr_t tmp1_dma;
dma_addr_t tmp2_dma;
u32 p_q_len;
} __packed;
};
#define SIZEOF_RSA_PRIV_F3_PDB (2 * sizeof(u32) + 9 * caam_ptr_sz)
#endif

8
drivers/crypto/caam/pkc_desc.c
View File

@ -13,7 +13,7 @@
/* Descriptor for RSA Public operation */
void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb)
{
init_job_desc_pdb(desc, 0, sizeof(*pdb));
init_job_desc_pdb(desc, 0, SIZEOF_RSA_PUB_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->f_dma);
append_ptr(desc, pdb->g_dma);
@ -26,7 +26,7 @@ void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb)
/* Descriptor for RSA Private operation - Private Key Form #1 */
void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb)
{
init_job_desc_pdb(desc, 0, sizeof(*pdb));
init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F1_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->g_dma);
append_ptr(desc, pdb->f_dma);
@ -39,7 +39,7 @@ void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb)
/* Descriptor for RSA Private operation - Private Key Form #2 */
void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb)
{
init_job_desc_pdb(desc, 0, sizeof(*pdb));
init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F2_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->g_dma);
append_ptr(desc, pdb->f_dma);
@ -56,7 +56,7 @@ void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb)
/* Descriptor for RSA Private operation - Private Key Form #3 */
void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb)
{
init_job_desc_pdb(desc, 0, sizeof(*pdb));
init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F3_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->g_dma);
append_ptr(desc, pdb->f_dma);

40
drivers/crypto/caam/regs.h
View File

@ -191,7 +191,8 @@ static inline u64 caam_dma64_to_cpu(u64 value)
static inline u64 cpu_to_caam_dma(u64 value)
{
if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
caam_ptr_sz == sizeof(u64))
return cpu_to_caam_dma64(value);
else
return cpu_to_caam32(value);
@ -199,7 +200,8 @@ static inline u64 cpu_to_caam_dma(u64 value)
static inline u64 caam_dma_to_cpu(u64 value)
{
if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
caam_ptr_sz == sizeof(u64))
return caam_dma64_to_cpu(value);
else
return caam32_to_cpu(value);
@ -213,13 +215,24 @@ static inline u64 caam_dma_to_cpu(u64 value)
static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
u32 *jrstatus)
{
struct {
dma_addr_t desc;/* Pointer to completed descriptor */
u32 jrstatus; /* Status for completed descriptor */
} __packed *outentry = outring;
*desc = outentry[hw_idx].desc;
*jrstatus = outentry[hw_idx].jrstatus;
if (caam_ptr_sz == sizeof(u32)) {
struct {
u32 desc;
u32 jrstatus;
} __packed *outentry = outring;
*desc = outentry[hw_idx].desc;
*jrstatus = outentry[hw_idx].jrstatus;
} else {
struct {
dma_addr_t desc;/* Pointer to completed descriptor */
u32 jrstatus; /* Status for completed descriptor */
} __packed *outentry = outring;
*desc = outentry[hw_idx].desc;
*jrstatus = outentry[hw_idx].jrstatus;
}
}
#define SIZEOF_JR_OUTENTRY (caam_ptr_sz + sizeof(u32))
@ -246,9 +259,15 @@ static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
{
dma_addr_t *inpentry = inpring;
if (caam_ptr_sz == sizeof(u32)) {
u32 *inpentry = inpring;
inpentry[hw_idx] = val;
inpentry[hw_idx] = val;
} else {
dma_addr_t *inpentry = inpring;
inpentry[hw_idx] = val;
}
}
#define SIZEOF_JR_INPENTRY caam_ptr_sz
@ -380,6 +399,7 @@ struct caam_perfmon {
u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
#define CTPR_MS_QI_SHIFT 25
#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
#define CTPR_MS_PS BIT(17)
#define CTPR_MS_DPAA2 BIT(13)
#define CTPR_MS_VIRT_EN_INCL 0x00000001
#define CTPR_MS_VIRT_EN_POR 0x00000002