Merge branch 'bnxt_en-ptp'
Michael Chan says:
====================
bnxt_en: Add hardware PTP timestamping support on 575XX devices
Add PTP RX and TX hardware timestamp support on 575XX devices. These
devices use the two-step method to implement the IEEE-1588 timestamping
support.
v2: Add spinlock to serialize access to the timecounter.
Use .do_aux_work() for the periodic timer reading and to get the TX
timestamp from the firmware.
Propagate error code from ptp_clock_register().
Make the 64-bit timer access safe on 32-bit CPUs.
Read PHC using direct register access.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
a1b05634e1
@ -206,6 +206,7 @@ config SYSTEMPORT
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config BNXT
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tristate "Broadcom NetXtreme-C/E support"
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depends on PCI
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imply PTP_1588_CLOCK
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select FW_LOADER
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select LIBCRC32C
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select NET_DEVLINK
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_BNXT) += bnxt_en.o
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bnxt_en-y := bnxt.o bnxt_sriov.o bnxt_ethtool.o bnxt_dcb.o bnxt_ulp.o bnxt_xdp.o bnxt_vfr.o bnxt_devlink.o bnxt_dim.o
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bnxt_en-y := bnxt.o bnxt_sriov.o bnxt_ethtool.o bnxt_dcb.o bnxt_ulp.o bnxt_xdp.o bnxt_ptp.o bnxt_vfr.o bnxt_devlink.o bnxt_dim.o
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bnxt_en-$(CONFIG_BNXT_FLOWER_OFFLOAD) += bnxt_tc.o
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bnxt_en-$(CONFIG_DEBUG_FS) += bnxt_debugfs.o
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@ -49,6 +49,8 @@
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#include <linux/log2.h>
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#include <linux/aer.h>
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#include <linux/bitmap.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/timecounter.h>
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#include <linux/cpu_rmap.h>
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#include <linux/cpumask.h>
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#include <net/pkt_cls.h>
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@ -63,6 +65,7 @@
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#include "bnxt_ethtool.h"
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#include "bnxt_dcb.h"
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#include "bnxt_xdp.h"
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#include "bnxt_ptp.h"
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#include "bnxt_vfr.h"
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#include "bnxt_tc.h"
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#include "bnxt_devlink.h"
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@ -418,12 +421,25 @@ static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
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vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
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}
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if (unlikely(skb->no_fcs)) {
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lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC);
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goto normal_tx;
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if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
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struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
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if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) &&
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atomic_dec_if_positive(&ptp->tx_avail) >= 0) {
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if (!bnxt_ptp_parse(skb, &ptp->tx_seqid)) {
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lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP);
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skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
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} else {
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atomic_inc(&bp->ptp_cfg->tx_avail);
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}
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}
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}
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if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
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if (unlikely(skb->no_fcs))
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lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC);
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if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh &&
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!lflags) {
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struct tx_push_buffer *tx_push_buf = txr->tx_push;
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struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
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struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
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@ -590,6 +606,8 @@ normal_tx:
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netdev_tx_sent_queue(txq, skb->len);
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skb_tx_timestamp(skb);
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/* Sync BD data before updating doorbell */
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wmb();
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@ -619,6 +637,9 @@ tx_done:
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return NETDEV_TX_OK;
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tx_dma_error:
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if (BNXT_TX_PTP_IS_SET(lflags))
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atomic_inc(&bp->ptp_cfg->tx_avail);
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last_frag = i;
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/* start back at beginning and unmap skb */
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@ -653,6 +674,7 @@ static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
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for (i = 0; i < nr_pkts; i++) {
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struct bnxt_sw_tx_bd *tx_buf;
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bool compl_deferred = false;
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struct sk_buff *skb;
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int j, last;
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@ -679,12 +701,21 @@ static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
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skb_frag_size(&skb_shinfo(skb)->frags[j]),
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PCI_DMA_TODEVICE);
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}
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if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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if (!bnxt_get_tx_ts_p5(bp, skb))
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compl_deferred = true;
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else
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atomic_inc(&bp->ptp_cfg->tx_avail);
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}
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}
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next_tx_int:
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cons = NEXT_TX(cons);
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tx_bytes += skb->len;
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dev_kfree_skb_any(skb);
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if (!compl_deferred)
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dev_kfree_skb_any(skb);
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}
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netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
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@ -1706,9 +1737,9 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
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u8 *data_ptr, agg_bufs, cmp_type;
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dma_addr_t dma_addr;
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struct sk_buff *skb;
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u32 flags, misc;
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void *data;
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int rc = 0;
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u32 misc;
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rxcmp = (struct rx_cmp *)
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&cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
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@ -1806,7 +1837,8 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
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goto next_rx_no_len;
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}
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len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
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flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type);
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len = flags >> RX_CMP_LEN_SHIFT;
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dma_addr = rx_buf->mapping;
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if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
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@ -1883,6 +1915,24 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
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}
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}
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if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) ==
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RX_CMP_FLAGS_ITYPE_PTP_W_TS)) {
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp);
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u64 ns, ts;
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if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) {
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struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
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spin_lock_bh(&ptp->ptp_lock);
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ns = timecounter_cyc2time(&ptp->tc, ts);
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spin_unlock_bh(&ptp->ptp_lock);
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memset(skb_hwtstamps(skb), 0,
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sizeof(*skb_hwtstamps(skb)));
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skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
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}
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}
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}
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bnxt_deliver_skb(bp, bnapi, skb);
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rc = 1;
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@ -7391,6 +7441,56 @@ hwrm_func_resc_qcaps_exit:
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return rc;
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}
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/* bp->hwrm_cmd_lock already held. */
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static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
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{
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struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
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struct hwrm_port_mac_ptp_qcfg_input req = {0};
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struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
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u8 flags;
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int rc;
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if (bp->hwrm_spec_code < 0x10801) {
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rc = -ENODEV;
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goto no_ptp;
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}
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req.port_id = cpu_to_le16(bp->pf.port_id);
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bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_PTP_QCFG, -1, -1);
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rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
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if (rc)
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goto no_ptp;
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flags = resp->flags;
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if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
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rc = -ENODEV;
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goto no_ptp;
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}
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if (!ptp) {
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ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
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if (!ptp)
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return -ENOMEM;
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ptp->bp = bp;
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bp->ptp_cfg = ptp;
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}
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if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {
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ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
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ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
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} else if (bp->flags & BNXT_FLAG_CHIP_P5) {
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ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
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ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
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} else {
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rc = -ENODEV;
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goto no_ptp;
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}
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return 0;
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no_ptp:
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kfree(ptp);
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bp->ptp_cfg = NULL;
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return rc;
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}
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static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
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{
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int rc = 0;
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@ -7462,6 +7562,8 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
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bp->flags &= ~BNXT_FLAG_WOL_CAP;
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if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
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bp->flags |= BNXT_FLAG_WOL_CAP;
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if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED)
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__bnxt_hwrm_ptp_qcfg(bp);
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} else {
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#ifdef CONFIG_BNXT_SRIOV
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struct bnxt_vf_info *vf = &bp->vf;
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@ -10020,6 +10122,7 @@ static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
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}
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}
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bnxt_ptp_start(bp);
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rc = bnxt_init_nic(bp, irq_re_init);
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if (rc) {
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netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
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@ -10335,6 +10438,12 @@ static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
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mdio->val_in);
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case SIOCSHWTSTAMP:
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return bnxt_hwtstamp_set(dev, ifr);
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case SIOCGHWTSTAMP:
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return bnxt_hwtstamp_get(dev, ifr);
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default:
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/* do nothing */
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break;
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@ -12551,6 +12660,8 @@ static void bnxt_remove_one(struct pci_dev *pdev)
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if (BNXT_PF(bp))
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devlink_port_type_clear(&bp->dl_port);
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bnxt_ptp_clear(bp);
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pci_disable_pcie_error_reporting(pdev);
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unregister_netdev(dev);
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clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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@ -12571,6 +12682,8 @@ static void bnxt_remove_one(struct pci_dev *pdev)
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bnxt_dcb_free(bp);
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kfree(bp->edev);
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bp->edev = NULL;
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kfree(bp->ptp_cfg);
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bp->ptp_cfg = NULL;
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kfree(bp->fw_health);
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bp->fw_health = NULL;
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bnxt_cleanup_pci(bp);
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@ -13132,6 +13245,11 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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rc);
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}
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if (bnxt_ptp_init(bp)) {
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netdev_warn(dev, "PTP initialization failed.\n");
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kfree(bp->ptp_cfg);
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bp->ptp_cfg = NULL;
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}
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bnxt_inv_fw_health_reg(bp);
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bnxt_dl_register(bp);
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@ -13161,6 +13279,8 @@ init_err_pci_clean:
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bnxt_free_hwrm_short_cmd_req(bp);
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bnxt_free_hwrm_resources(bp);
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bnxt_ethtool_free(bp);
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kfree(bp->ptp_cfg);
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bp->ptp_cfg = NULL;
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kfree(bp->fw_health);
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bp->fw_health = NULL;
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bnxt_cleanup_pci(bp);
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@ -89,6 +89,8 @@ struct tx_bd_ext {
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#define TX_BD_CFA_META_KEY_VLAN (1 << 28)
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};
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#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
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struct rx_bd {
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__le32 rx_bd_len_flags_type;
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#define RX_BD_TYPE (0x3f << 0)
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@ -159,6 +161,7 @@ struct rx_cmp {
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#define RX_CMP_FLAGS_RSS_VALID (1 << 10)
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#define RX_CMP_FLAGS_UNUSED (1 << 11)
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#define RX_CMP_FLAGS_ITYPES_SHIFT 12
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#define RX_CMP_FLAGS_ITYPES_MASK 0xf000
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#define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
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#define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
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#define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
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@ -240,7 +243,7 @@ struct rx_cmp_ext {
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#define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
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#define RX_CMPL_CFA_CODE_SFT 16
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__le32 rx_cmp_unused3;
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__le32 rx_cmp_timestamp;
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};
|
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#define RX_CMP_L2_ERRORS \
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@ -1362,6 +1365,9 @@ struct bnxt_test_info {
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#define BNXT_GRC_REG_CHIP_NUM 0x48
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#define BNXT_GRC_REG_BASE 0x260000
|
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|
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#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
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#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
|
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|
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#define BNXT_GRC_BASE_MASK 0xfffff000
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#define BNXT_GRC_OFFSET_MASK 0x00000ffc
|
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|
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@ -2042,6 +2048,8 @@ struct bnxt {
|
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|
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struct bpf_prog *xdp_prog;
|
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|
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struct bnxt_ptp_cfg *ptp_cfg;
|
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|
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/* devlink interface and vf-rep structs */
|
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struct devlink *dl;
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struct devlink_port dl_port;
|
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|
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@ -19,9 +19,13 @@
|
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#include <linux/firmware.h>
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#include <linux/utsname.h>
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#include <linux/time.h>
|
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#include <linux/ptp_clock_kernel.h>
|
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#include <linux/net_tstamp.h>
|
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#include <linux/timecounter.h>
|
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#include "bnxt_hsi.h"
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#include "bnxt.h"
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#include "bnxt_xdp.h"
|
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#include "bnxt_ptp.h"
|
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#include "bnxt_ethtool.h"
|
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#include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
|
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#include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
|
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@ -3926,6 +3930,35 @@ static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
|
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return 0;
|
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}
|
||||
|
||||
static int bnxt_get_ts_info(struct net_device *dev,
|
||||
struct ethtool_ts_info *info)
|
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{
|
||||
struct bnxt *bp = netdev_priv(dev);
|
||||
struct bnxt_ptp_cfg *ptp;
|
||||
|
||||
ptp = bp->ptp_cfg;
|
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info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
|
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SOF_TIMESTAMPING_RX_SOFTWARE |
|
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SOF_TIMESTAMPING_SOFTWARE;
|
||||
|
||||
info->phc_index = -1;
|
||||
if (!ptp)
|
||||
return 0;
|
||||
|
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info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
|
||||
SOF_TIMESTAMPING_RX_HARDWARE |
|
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SOF_TIMESTAMPING_RAW_HARDWARE;
|
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if (ptp->ptp_clock)
|
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info->phc_index = ptp_clock_index(ptp->ptp_clock);
|
||||
|
||||
info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
|
||||
|
||||
info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
|
||||
(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
|
||||
(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void bnxt_ethtool_init(struct bnxt *bp)
|
||||
{
|
||||
struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr;
|
||||
@ -4172,6 +4205,7 @@ const struct ethtool_ops bnxt_ethtool_ops = {
|
||||
.nway_reset = bnxt_nway_reset,
|
||||
.set_phys_id = bnxt_set_phys_id,
|
||||
.self_test = bnxt_self_test,
|
||||
.get_ts_info = bnxt_get_ts_info,
|
||||
.reset = bnxt_reset,
|
||||
.set_dump = bnxt_set_dump,
|
||||
.get_dump_flag = bnxt_get_dump_flag,
|
||||
|
||||
@ -189,6 +189,8 @@ struct cmd_nums {
|
||||
#define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL
|
||||
#define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL
|
||||
#define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL
|
||||
#define HWRM_QUEUE_GLOBAL_CFG 0x86UL
|
||||
#define HWRM_QUEUE_GLOBAL_QCFG 0x87UL
|
||||
#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
|
||||
#define HWRM_CFA_L2_FILTER_FREE 0x91UL
|
||||
#define HWRM_CFA_L2_FILTER_CFG 0x92UL
|
||||
@ -250,6 +252,8 @@ struct cmd_nums {
|
||||
#define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
|
||||
#define HWRM_FW_STATE_UNQUIESCE 0xd8UL
|
||||
#define HWRM_PORT_DSC_DUMP 0xd9UL
|
||||
#define HWRM_PORT_EP_TX_QCFG 0xdaUL
|
||||
#define HWRM_PORT_EP_TX_CFG 0xdbUL
|
||||
#define HWRM_TEMP_MONITOR_QUERY 0xe0UL
|
||||
#define HWRM_REG_POWER_QUERY 0xe1UL
|
||||
#define HWRM_CORE_FREQUENCY_QUERY 0xe2UL
|
||||
@ -305,6 +309,8 @@ struct cmd_nums {
|
||||
#define HWRM_CFA_EEM_OP 0x123UL
|
||||
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
|
||||
#define HWRM_CFA_TFLIB 0x125UL
|
||||
#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL
|
||||
#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL
|
||||
#define HWRM_ENGINE_CKV_STATUS 0x12eUL
|
||||
#define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
|
||||
#define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
|
||||
@ -356,6 +362,12 @@ struct cmd_nums {
|
||||
#define HWRM_STAT_EXT_CTX_QUERY 0x199UL
|
||||
#define HWRM_FUNC_SPD_CFG 0x19aUL
|
||||
#define HWRM_FUNC_SPD_QCFG 0x19bUL
|
||||
#define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL
|
||||
#define HWRM_FUNC_PTP_PIN_CFG 0x19dUL
|
||||
#define HWRM_FUNC_PTP_CFG 0x19eUL
|
||||
#define HWRM_FUNC_PTP_TS_QUERY 0x19fUL
|
||||
#define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL
|
||||
#define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL
|
||||
#define HWRM_SELFTEST_QLIST 0x200UL
|
||||
#define HWRM_SELFTEST_EXEC 0x201UL
|
||||
#define HWRM_SELFTEST_IRQ 0x202UL
|
||||
@ -373,6 +385,10 @@ struct cmd_nums {
|
||||
#define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL
|
||||
#define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL
|
||||
#define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL
|
||||
#define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL
|
||||
#define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL
|
||||
#define HWRM_MFG_PRVSN_GET_STATE 0x213UL
|
||||
#define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL
|
||||
#define HWRM_TF 0x2bcUL
|
||||
#define HWRM_TF_VERSION_GET 0x2bdUL
|
||||
#define HWRM_TF_SESSION_OPEN 0x2c6UL
|
||||
@ -385,6 +401,7 @@ struct cmd_nums {
|
||||
#define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL
|
||||
#define HWRM_TF_SESSION_RESC_FREE 0x2ceUL
|
||||
#define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL
|
||||
#define HWRM_TF_SESSION_RESC_INFO 0x2d0UL
|
||||
#define HWRM_TF_TBL_TYPE_GET 0x2daUL
|
||||
#define HWRM_TF_TBL_TYPE_SET 0x2dbUL
|
||||
#define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL
|
||||
@ -399,6 +416,7 @@ struct cmd_nums {
|
||||
#define HWRM_TF_EM_INSERT 0x2eaUL
|
||||
#define HWRM_TF_EM_DELETE 0x2ebUL
|
||||
#define HWRM_TF_EM_HASH_INSERT 0x2ecUL
|
||||
#define HWRM_TF_EM_MOVE 0x2edUL
|
||||
#define HWRM_TF_TCAM_SET 0x2f8UL
|
||||
#define HWRM_TF_TCAM_GET 0x2f9UL
|
||||
#define HWRM_TF_TCAM_MOVE 0x2faUL
|
||||
@ -427,6 +445,16 @@ struct cmd_nums {
|
||||
#define HWRM_DBG_QCAPS 0xff20UL
|
||||
#define HWRM_DBG_QCFG 0xff21UL
|
||||
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL
|
||||
#define HWRM_DBG_USEQ_ALLOC 0xff23UL
|
||||
#define HWRM_DBG_USEQ_FREE 0xff24UL
|
||||
#define HWRM_DBG_USEQ_FLUSH 0xff25UL
|
||||
#define HWRM_DBG_USEQ_QCAPS 0xff26UL
|
||||
#define HWRM_DBG_USEQ_CW_CFG 0xff27UL
|
||||
#define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL
|
||||
#define HWRM_DBG_USEQ_RUN 0xff29UL
|
||||
#define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL
|
||||
#define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL
|
||||
#define HWRM_NVM_DEFRAG 0xffecUL
|
||||
#define HWRM_NVM_REQ_ARBITRATION 0xffedUL
|
||||
#define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
|
||||
#define HWRM_NVM_VALIDATE_OPTION 0xffefUL
|
||||
@ -471,6 +499,7 @@ struct ret_codes {
|
||||
#define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
|
||||
#define HWRM_ERR_CODE_BUSY 0x10UL
|
||||
#define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL
|
||||
#define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL
|
||||
#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
|
||||
#define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
|
||||
#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
|
||||
@ -502,8 +531,8 @@ struct hwrm_err_output {
|
||||
#define HWRM_VERSION_MAJOR 1
|
||||
#define HWRM_VERSION_MINOR 10
|
||||
#define HWRM_VERSION_UPDATE 2
|
||||
#define HWRM_VERSION_RSVD 16
|
||||
#define HWRM_VERSION_STR "1.10.2.16"
|
||||
#define HWRM_VERSION_RSVD 47
|
||||
#define HWRM_VERSION_STR "1.10.2.47"
|
||||
|
||||
/* hwrm_ver_get_input (size:192b/24B) */
|
||||
struct hwrm_ver_get_input {
|
||||
@ -604,7 +633,8 @@ struct hwrm_ver_get_output {
|
||||
__le16 roce_fw_build;
|
||||
__le16 roce_fw_patch;
|
||||
__le16 max_ext_req_len;
|
||||
u8 unused_1[5];
|
||||
__le16 max_req_timeout;
|
||||
u8 unused_1[3];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -725,7 +755,10 @@ struct hwrm_async_event_cmpl {
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x43UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER 0x43UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x46UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
|
||||
@ -919,6 +952,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change {
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
|
||||
__le32 event_data2;
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
|
||||
@ -1074,6 +1109,223 @@ struct hwrm_async_event_cmpl_echo_request {
|
||||
__le32 event_data1;
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_phc_master (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_phc_master {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 0x43UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER
|
||||
__le32 event_data2;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT 16
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK 0xfUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_pps_timestamp {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
|
||||
__le32 event_data2;
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL
|
||||
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_error_report (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_error_report {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
|
||||
__le32 event_data2;
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_hwrm_error {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
|
||||
__le32 event_data2;
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_error_report_base {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
|
||||
__le32 event_data2;
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_error_report_pause_storm {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
|
||||
__le32 event_data2;
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_error_report_invalid_signal {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
|
||||
__le32 event_data2;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_error_report_nvm {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
|
||||
__le32 event_data2;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8)
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8)
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
|
||||
};
|
||||
|
||||
/* hwrm_func_reset_input (size:192b/24B) */
|
||||
struct hwrm_func_reset_input {
|
||||
__le16 req_type;
|
||||
@ -1302,7 +1554,7 @@ struct hwrm_func_qcaps_output {
|
||||
__le32 max_flow_id;
|
||||
__le32 max_hw_ring_grps;
|
||||
__le16 max_sp_tx_rings;
|
||||
u8 unused_0[2];
|
||||
__le16 max_msix_vfs;
|
||||
__le32 flags_ext;
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL
|
||||
@ -1320,6 +1572,14 @@ struct hwrm_func_qcaps_output {
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL
|
||||
u8 max_schqs;
|
||||
u8 mpc_chnls_cap;
|
||||
#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL
|
||||
@ -1342,7 +1602,7 @@ struct hwrm_func_qcfg_input {
|
||||
u8 unused_0[6];
|
||||
};
|
||||
|
||||
/* hwrm_func_qcfg_output (size:768b/96B) */
|
||||
/* hwrm_func_qcfg_output (size:832b/104B) */
|
||||
struct hwrm_func_qcfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
@ -1366,6 +1626,7 @@ struct hwrm_func_qcfg_output {
|
||||
#define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL
|
||||
#define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL
|
||||
#define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL
|
||||
#define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL
|
||||
u8 mac_address[6];
|
||||
__le16 pci_id;
|
||||
__le16 alloc_rsscos_ctx;
|
||||
@ -1374,7 +1635,7 @@ struct hwrm_func_qcfg_output {
|
||||
__le16 alloc_rx_rings;
|
||||
__le16 alloc_l2_ctx;
|
||||
__le16 alloc_vnics;
|
||||
__le16 mtu;
|
||||
__le16 admin_mtu;
|
||||
__le16 mru;
|
||||
__le16 stat_ctx_id;
|
||||
u8 port_partition_type;
|
||||
@ -1383,6 +1644,7 @@ struct hwrm_func_qcfg_output {
|
||||
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
|
||||
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
|
||||
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
|
||||
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL
|
||||
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
|
||||
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
|
||||
u8 port_pf_cnt;
|
||||
@ -1463,11 +1725,35 @@ struct hwrm_func_qcfg_output {
|
||||
#define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL
|
||||
#define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL
|
||||
#define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL
|
||||
u8 unused_2[6];
|
||||
u8 unused_2[3];
|
||||
__le32 partition_min_bw;
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
|
||||
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
|
||||
__le32 partition_max_bw;
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
|
||||
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
|
||||
__le16 host_mtu;
|
||||
u8 unused_3;
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_cfg_input (size:768b/96B) */
|
||||
/* hwrm_func_cfg_input (size:832b/104B) */
|
||||
struct hwrm_func_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -1504,7 +1790,7 @@ struct hwrm_func_cfg_input {
|
||||
#define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL
|
||||
#define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL
|
||||
__le32 enables;
|
||||
#define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
|
||||
#define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL
|
||||
#define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
|
||||
#define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
|
||||
#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
|
||||
@ -1530,7 +1816,11 @@ struct hwrm_func_cfg_input {
|
||||
#define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL
|
||||
#define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL
|
||||
#define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL
|
||||
__le16 mtu;
|
||||
#define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL
|
||||
#define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL
|
||||
#define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL
|
||||
#define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL
|
||||
__le16 admin_mtu;
|
||||
__le16 mru;
|
||||
__le16 num_rsscos_ctxs;
|
||||
__le16 num_cmpl_rings;
|
||||
@ -1615,7 +1905,30 @@ struct hwrm_func_cfg_input {
|
||||
#define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL
|
||||
#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL
|
||||
#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL
|
||||
u8 unused_0[4];
|
||||
__le32 partition_min_bw;
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
|
||||
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
|
||||
__le32 partition_max_bw;
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
|
||||
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
|
||||
__be16 tpid;
|
||||
__le16 host_mtu;
|
||||
};
|
||||
|
||||
/* hwrm_func_cfg_output (size:128b/16B) */
|
||||
@ -1777,14 +2090,15 @@ struct hwrm_func_drv_rgtr_input {
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le32 flags;
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL
|
||||
__le32 enables;
|
||||
#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
|
||||
#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
|
||||
@ -2047,7 +2361,7 @@ struct hwrm_func_backing_store_qcaps_input {
|
||||
__le64 resp_addr;
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_qcaps_output (size:704b/88B) */
|
||||
/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
|
||||
struct hwrm_func_backing_store_qcaps_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
@ -2085,6 +2399,8 @@ struct hwrm_func_backing_store_qcaps_output {
|
||||
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL
|
||||
u8 qp_init_offset;
|
||||
u8 srq_init_offset;
|
||||
u8 cq_init_offset;
|
||||
@ -2093,7 +2409,13 @@ struct hwrm_func_backing_store_qcaps_output {
|
||||
u8 stat_init_offset;
|
||||
u8 mrav_init_offset;
|
||||
u8 tqm_fp_rings_count_ext;
|
||||
u8 rsvd[5];
|
||||
u8 tkc_init_offset;
|
||||
u8 rkc_init_offset;
|
||||
__le16 tkc_entry_size;
|
||||
__le16 rkc_entry_size;
|
||||
__le32 tkc_max_entries;
|
||||
__le32 rkc_max_entries;
|
||||
u8 rsvd[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -2120,7 +2442,7 @@ struct tqm_fp_ring_cfg {
|
||||
__le64 tqm_ring_page_dir;
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_cfg_input (size:2432b/304B) */
|
||||
/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
|
||||
struct hwrm_func_backing_store_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -2150,6 +2472,8 @@ struct hwrm_func_backing_store_cfg_input {
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL
|
||||
u8 qpc_pg_size_qpc_lvl;
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
|
||||
@ -2508,6 +2832,45 @@ struct hwrm_func_backing_store_cfg_input {
|
||||
u8 ring10_unused[3];
|
||||
__le32 tqm_ring10_num_entries;
|
||||
__le64 tqm_ring10_page_dir;
|
||||
__le32 tkc_num_entries;
|
||||
__le32 rkc_num_entries;
|
||||
__le64 tkc_page_dir;
|
||||
__le64 rkc_page_dir;
|
||||
__le16 tkc_entry_size;
|
||||
__le16 rkc_entry_size;
|
||||
u8 tkc_pg_size_tkc_lvl;
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G
|
||||
u8 rkc_pg_size_rkc_lvl;
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G
|
||||
u8 rsvd[2];
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_cfg_output (size:128b/16B) */
|
||||
@ -2634,6 +2997,212 @@ struct hwrm_func_echo_response_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
|
||||
struct hwrm_func_ptp_pin_qcfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
u8 unused_0[8];
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
|
||||
struct hwrm_func_ptp_pin_qcfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 num_pins;
|
||||
u8 state;
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL
|
||||
u8 pin0_usage;
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT
|
||||
u8 pin1_usage;
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT
|
||||
u8 pin2_usage;
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT
|
||||
u8 pin3_usage;
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT
|
||||
u8 unused_0;
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
|
||||
struct hwrm_func_ptp_pin_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le32 enables;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL
|
||||
u8 pin0_state;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED
|
||||
u8 pin0_usage;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT
|
||||
u8 pin1_state;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED
|
||||
u8 pin1_usage;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT
|
||||
u8 pin2_state;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED
|
||||
u8 pin2_usage;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT
|
||||
u8 pin3_state;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED
|
||||
u8 pin3_usage;
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL
|
||||
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT
|
||||
u8 unused_0[4];
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
|
||||
struct hwrm_func_ptp_pin_cfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 unused_0[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_cfg_input (size:320b/40B) */
|
||||
struct hwrm_func_ptp_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 enables;
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL
|
||||
u8 ptp_pps_event;
|
||||
#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL
|
||||
u8 ptp_freq_adj_dll_source;
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
|
||||
u8 ptp_freq_adj_dll_phase;
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M
|
||||
u8 unused_0[3];
|
||||
__le32 ptp_freq_adj_ext_period;
|
||||
__le32 ptp_freq_adj_ext_up;
|
||||
__le32 ptp_freq_adj_ext_phase_lower;
|
||||
__le32 ptp_freq_adj_ext_phase_upper;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_cfg_output (size:128b/16B) */
|
||||
struct hwrm_func_ptp_cfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 unused_0[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_ts_query_input (size:192b/24B) */
|
||||
struct hwrm_func_ptp_ts_query_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le32 flags;
|
||||
#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL
|
||||
#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL
|
||||
u8 unused_0[4];
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_ts_query_output (size:320b/40B) */
|
||||
struct hwrm_func_ptp_ts_query_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
__le64 pps_event_ts;
|
||||
__le64 ptm_res_local_ts;
|
||||
__le64 ptm_pmstr_ts;
|
||||
__le32 ptm_mstr_prop_dly;
|
||||
u8 unused_0[3];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_drv_if_change_input (size:192b/24B) */
|
||||
struct hwrm_func_drv_if_change_input {
|
||||
__le16 req_type;
|
||||
@ -3156,6 +3725,7 @@ struct hwrm_port_mac_cfg_input {
|
||||
#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
|
||||
#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
|
||||
#define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL
|
||||
#define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL
|
||||
__le16 port_id;
|
||||
u8 ipg;
|
||||
u8 lpbk;
|
||||
@ -3188,8 +3758,8 @@ struct hwrm_port_mac_cfg_input {
|
||||
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
|
||||
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
|
||||
u8 unused_0[3];
|
||||
__s32 ptp_freq_adj_ppb;
|
||||
u8 unused_1[4];
|
||||
__le32 ptp_freq_adj_ppb;
|
||||
__le32 ptp_adj_phase;
|
||||
};
|
||||
|
||||
/* hwrm_port_mac_cfg_output (size:128b/16B) */
|
||||
@ -3221,16 +3791,17 @@ struct hwrm_port_mac_ptp_qcfg_input {
|
||||
u8 unused_0[6];
|
||||
};
|
||||
|
||||
/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
|
||||
/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
|
||||
struct hwrm_port_mac_ptp_qcfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 flags;
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL
|
||||
u8 unused_0[3];
|
||||
__le32 rx_ts_reg_off_lower;
|
||||
__le32 rx_ts_reg_off_upper;
|
||||
@ -3247,6 +3818,8 @@ struct hwrm_port_mac_ptp_qcfg_output {
|
||||
__le32 tx_ts_reg_off_seq_id;
|
||||
__le32 tx_ts_reg_off_fifo;
|
||||
__le32 tx_ts_reg_off_granularity;
|
||||
__le32 ts_ref_clock_reg_lower;
|
||||
__le32 ts_ref_clock_reg_upper;
|
||||
u8 unused_1[7];
|
||||
u8 valid;
|
||||
};
|
||||
@ -3647,7 +4220,7 @@ struct hwrm_port_lpbk_clr_stats_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_port_ts_query_input (size:192b/24B) */
|
||||
/* hwrm_port_ts_query_input (size:256b/32B) */
|
||||
struct hwrm_port_ts_query_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -3662,6 +4235,11 @@ struct hwrm_port_ts_query_input {
|
||||
#define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL
|
||||
__le16 port_id;
|
||||
u8 unused_0[2];
|
||||
__le16 enables;
|
||||
#define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL
|
||||
#define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL
|
||||
__le16 ts_req_timeout;
|
||||
__le32 ptp_seq_id;
|
||||
};
|
||||
|
||||
/* hwrm_port_ts_query_output (size:192b/24B) */
|
||||
@ -4215,7 +4793,8 @@ struct hwrm_queue_qportcfg_output {
|
||||
u8 max_configurable_lossless_queues;
|
||||
u8 queue_cfg_allowed;
|
||||
u8 queue_cfg_info;
|
||||
#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
|
||||
#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
|
||||
#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL
|
||||
u8 queue_pfcenable_cfg_allowed;
|
||||
u8 queue_pri2cos_cfg_allowed;
|
||||
u8 queue_cos2bw_cfg_allowed;
|
||||
@ -5467,6 +6046,7 @@ struct hwrm_vnic_qcaps_output {
|
||||
#define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL
|
||||
#define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL
|
||||
#define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL
|
||||
#define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL
|
||||
__le16 max_aggs_supported;
|
||||
u8 unused_1[5];
|
||||
u8 valid;
|
||||
@ -7224,6 +7804,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
|
||||
#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL
|
||||
#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL
|
||||
#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL
|
||||
#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL
|
||||
u8 unused_0[3];
|
||||
u8 valid;
|
||||
};
|
||||
@ -7914,11 +8495,14 @@ struct hwrm_temp_monitor_query_output {
|
||||
u8 phy_temp;
|
||||
u8 om_temp;
|
||||
u8 flags;
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
|
||||
u8 unused_0[3];
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
|
||||
#define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL
|
||||
u8 temp2;
|
||||
u8 phy_temp2;
|
||||
u8 om_temp2;
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -8109,6 +8693,7 @@ struct hwrm_dbg_qcaps_output {
|
||||
#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL
|
||||
#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL
|
||||
#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL
|
||||
#define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL
|
||||
u8 unused_1[3];
|
||||
u8 valid;
|
||||
};
|
||||
@ -8632,10 +9217,11 @@ struct hwrm_nvm_install_update_output {
|
||||
/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
|
||||
struct hwrm_nvm_install_update_cmd_err {
|
||||
u8 code;
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL
|
||||
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK
|
||||
u8 unused_0[7];
|
||||
};
|
||||
|
||||
@ -8876,6 +9462,7 @@ struct fw_status_reg {
|
||||
#define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL
|
||||
#define FW_STATUS_REG_SHUTDOWN 0x100000UL
|
||||
#define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL
|
||||
#define FW_STATUS_REG_RECOVERING 0x400000UL
|
||||
};
|
||||
|
||||
/* hcomm_status (size:64b/8B) */
|
||||
|
||||
473
drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c
Normal file
473
drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c
Normal file
@ -0,0 +1,473 @@
|
||||
/* Broadcom NetXtreme-C/E network driver.
|
||||
*
|
||||
* Copyright (c) 2021 Broadcom Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/ptp_clock_kernel.h>
|
||||
#include <linux/net_tstamp.h>
|
||||
#include <linux/timecounter.h>
|
||||
#include <linux/timekeeping.h>
|
||||
#include <linux/ptp_classify.h>
|
||||
#include "bnxt_hsi.h"
|
||||
#include "bnxt.h"
|
||||
#include "bnxt_ptp.h"
|
||||
|
||||
int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id)
|
||||
{
|
||||
unsigned int ptp_class;
|
||||
struct ptp_header *hdr;
|
||||
|
||||
ptp_class = ptp_classify_raw(skb);
|
||||
|
||||
switch (ptp_class & PTP_CLASS_VMASK) {
|
||||
case PTP_CLASS_V1:
|
||||
case PTP_CLASS_V2:
|
||||
hdr = ptp_parse_header(skb, ptp_class);
|
||||
if (!hdr)
|
||||
return -EINVAL;
|
||||
|
||||
*seq_id = ntohs(hdr->sequence_id);
|
||||
return 0;
|
||||
default:
|
||||
return -ERANGE;
|
||||
}
|
||||
}
|
||||
|
||||
static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
|
||||
const struct timespec64 *ts)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
|
||||
ptp_info);
|
||||
u64 ns = timespec64_to_ns(ts);
|
||||
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
timecounter_init(&ptp->tc, &ptp->cc, ns);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Caller holds ptp_lock */
|
||||
static u64 bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
u64 ns;
|
||||
|
||||
ptp_read_system_prets(sts);
|
||||
ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
|
||||
ptp_read_system_postts(sts);
|
||||
ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32;
|
||||
return ns;
|
||||
}
|
||||
|
||||
static void bnxt_ptp_get_current_time(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
|
||||
if (!ptp)
|
||||
return;
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
WRITE_ONCE(ptp->old_time, ptp->current_time);
|
||||
ptp->current_time = bnxt_refclk_read(bp, NULL);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
}
|
||||
|
||||
static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)
|
||||
{
|
||||
struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
|
||||
struct hwrm_port_ts_query_input req = {0};
|
||||
int rc;
|
||||
|
||||
bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_TS_QUERY, -1, -1);
|
||||
req.flags = cpu_to_le32(flags);
|
||||
if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
|
||||
PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
|
||||
req.enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
|
||||
req.ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid);
|
||||
req.ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT);
|
||||
}
|
||||
mutex_lock(&bp->hwrm_cmd_lock);
|
||||
rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
|
||||
if (!rc)
|
||||
*ts = le64_to_cpu(resp->ptp_msg_ts);
|
||||
mutex_unlock(&bp->hwrm_cmd_lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
|
||||
struct timespec64 *ts,
|
||||
struct ptp_system_timestamp *sts)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
|
||||
ptp_info);
|
||||
u64 ns, cycles;
|
||||
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
cycles = bnxt_refclk_read(ptp->bp, sts);
|
||||
ns = timecounter_cyc2time(&ptp->tc, cycles);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
*ts = ns_to_timespec64(ns);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
|
||||
ptp_info);
|
||||
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
timecounter_adjtime(&ptp->tc, delta);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
|
||||
ptp_info);
|
||||
struct hwrm_port_mac_cfg_input req = {0};
|
||||
struct bnxt *bp = ptp->bp;
|
||||
int rc;
|
||||
|
||||
bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1);
|
||||
req.ptp_freq_adj_ppb = cpu_to_le32(ppb);
|
||||
req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
|
||||
rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
|
||||
if (rc)
|
||||
netdev_err(ptp->bp->dev,
|
||||
"ptp adjfreq failed. rc = %d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int bnxt_ptp_enable(struct ptp_clock_info *ptp,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
|
||||
{
|
||||
struct hwrm_port_mac_cfg_input req = {0};
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
u32 flags = 0;
|
||||
|
||||
bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1);
|
||||
if (ptp->rx_filter)
|
||||
flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
|
||||
else
|
||||
flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
|
||||
if (ptp->tx_tstamp_en)
|
||||
flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
|
||||
else
|
||||
flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
|
||||
req.flags = cpu_to_le32(flags);
|
||||
req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
|
||||
req.rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
|
||||
|
||||
return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
|
||||
}
|
||||
|
||||
int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
|
||||
{
|
||||
struct bnxt *bp = netdev_priv(dev);
|
||||
struct hwtstamp_config stmpconf;
|
||||
struct bnxt_ptp_cfg *ptp;
|
||||
u16 old_rxctl;
|
||||
int old_rx_filter, rc;
|
||||
u8 old_tx_tstamp_en;
|
||||
|
||||
ptp = bp->ptp_cfg;
|
||||
if (!ptp)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
|
||||
return -EFAULT;
|
||||
|
||||
if (stmpconf.flags)
|
||||
return -EINVAL;
|
||||
|
||||
if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
|
||||
stmpconf.tx_type != HWTSTAMP_TX_OFF)
|
||||
return -ERANGE;
|
||||
|
||||
old_rx_filter = ptp->rx_filter;
|
||||
old_rxctl = ptp->rxctl;
|
||||
old_tx_tstamp_en = ptp->tx_tstamp_en;
|
||||
switch (stmpconf.rx_filter) {
|
||||
case HWTSTAMP_FILTER_NONE:
|
||||
ptp->rxctl = 0;
|
||||
ptp->rx_filter = HWTSTAMP_FILTER_NONE;
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
|
||||
ptp->rxctl = BNXT_PTP_MSG_EVENTS;
|
||||
ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
|
||||
ptp->rxctl = BNXT_PTP_MSG_SYNC;
|
||||
ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
|
||||
ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
|
||||
ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
|
||||
break;
|
||||
default:
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
if (stmpconf.tx_type == HWTSTAMP_TX_ON)
|
||||
ptp->tx_tstamp_en = 1;
|
||||
else
|
||||
ptp->tx_tstamp_en = 0;
|
||||
|
||||
rc = bnxt_hwrm_ptp_cfg(bp);
|
||||
if (rc)
|
||||
goto ts_set_err;
|
||||
|
||||
stmpconf.rx_filter = ptp->rx_filter;
|
||||
return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
|
||||
-EFAULT : 0;
|
||||
|
||||
ts_set_err:
|
||||
ptp->rx_filter = old_rx_filter;
|
||||
ptp->rxctl = old_rxctl;
|
||||
ptp->tx_tstamp_en = old_tx_tstamp_en;
|
||||
return rc;
|
||||
}
|
||||
|
||||
int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
|
||||
{
|
||||
struct bnxt *bp = netdev_priv(dev);
|
||||
struct hwtstamp_config stmpconf;
|
||||
struct bnxt_ptp_cfg *ptp;
|
||||
|
||||
ptp = bp->ptp_cfg;
|
||||
if (!ptp)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
stmpconf.flags = 0;
|
||||
stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
|
||||
|
||||
stmpconf.rx_filter = ptp->rx_filter;
|
||||
return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
|
||||
-EFAULT : 0;
|
||||
}
|
||||
|
||||
static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
|
||||
{
|
||||
u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
|
||||
u32 win_off;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
|
||||
return -ERANGE;
|
||||
}
|
||||
win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
|
||||
writel(reg_base, bp->bar0 + win_off);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnxt_map_ptp_regs(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
u32 *reg_arr;
|
||||
int rc, i;
|
||||
|
||||
reg_arr = ptp->refclk_regs;
|
||||
if (bp->flags & BNXT_FLAG_CHIP_P5) {
|
||||
rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
|
||||
if (rc)
|
||||
return rc;
|
||||
for (i = 0; i < 2; i++)
|
||||
ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
|
||||
(ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
|
||||
return 0;
|
||||
}
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void bnxt_unmap_ptp_regs(struct bnxt *bp)
|
||||
{
|
||||
writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
|
||||
(BNXT_PTP_GRC_WIN - 1) * 4);
|
||||
}
|
||||
|
||||
static u64 bnxt_cc_read(const struct cyclecounter *cc)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
|
||||
|
||||
return bnxt_refclk_read(ptp->bp, NULL);
|
||||
}
|
||||
|
||||
static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
struct skb_shared_hwtstamps timestamp;
|
||||
u64 ts = 0, ns = 0;
|
||||
int rc;
|
||||
|
||||
rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts);
|
||||
if (!rc) {
|
||||
memset(×tamp, 0, sizeof(timestamp));
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
ns = timecounter_cyc2time(&ptp->tc, ts);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
timestamp.hwtstamp = ns_to_ktime(ns);
|
||||
skb_tstamp_tx(ptp->tx_skb, ×tamp);
|
||||
} else {
|
||||
netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n",
|
||||
rc);
|
||||
}
|
||||
|
||||
dev_kfree_skb_any(ptp->tx_skb);
|
||||
ptp->tx_skb = NULL;
|
||||
atomic_inc(&ptp->tx_avail);
|
||||
}
|
||||
|
||||
static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
|
||||
ptp_info);
|
||||
unsigned long now = jiffies;
|
||||
struct bnxt *bp = ptp->bp;
|
||||
|
||||
if (ptp->tx_skb)
|
||||
bnxt_stamp_tx_skb(bp, ptp->tx_skb);
|
||||
|
||||
if (!time_after_eq(now, ptp->next_period))
|
||||
return ptp->next_period - now;
|
||||
|
||||
bnxt_ptp_get_current_time(bp);
|
||||
ptp->next_period = now + HZ;
|
||||
return HZ;
|
||||
}
|
||||
|
||||
int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
|
||||
if (ptp->tx_skb) {
|
||||
netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
ptp->tx_skb = skb;
|
||||
ptp_schedule_worker(ptp->ptp_clock, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
u64 time;
|
||||
|
||||
if (!ptp)
|
||||
return -ENODEV;
|
||||
|
||||
BNXT_READ_TIME64(ptp, time, ptp->old_time);
|
||||
*ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
|
||||
if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
|
||||
*ts += BNXT_LO_TIMER_MASK + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void bnxt_ptp_start(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
|
||||
if (!ptp)
|
||||
return;
|
||||
|
||||
if (bp->flags & BNXT_FLAG_CHIP_P5) {
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
ptp->current_time = bnxt_refclk_read(bp, NULL);
|
||||
WRITE_ONCE(ptp->old_time, ptp->current_time);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
ptp_schedule_worker(ptp->ptp_clock, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct ptp_clock_info bnxt_ptp_caps = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "bnxt clock",
|
||||
.max_adj = BNXT_MAX_PHC_DRIFT,
|
||||
.n_alarm = 0,
|
||||
.n_ext_ts = 0,
|
||||
.n_per_out = 0,
|
||||
.n_pins = 0,
|
||||
.pps = 0,
|
||||
.adjfreq = bnxt_ptp_adjfreq,
|
||||
.adjtime = bnxt_ptp_adjtime,
|
||||
.do_aux_work = bnxt_ptp_ts_aux_work,
|
||||
.gettimex64 = bnxt_ptp_gettimex,
|
||||
.settime64 = bnxt_ptp_settime,
|
||||
.enable = bnxt_ptp_enable,
|
||||
};
|
||||
|
||||
int bnxt_ptp_init(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
int rc;
|
||||
|
||||
if (!ptp)
|
||||
return 0;
|
||||
|
||||
rc = bnxt_map_ptp_regs(bp);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
|
||||
spin_lock_init(&ptp->ptp_lock);
|
||||
|
||||
memset(&ptp->cc, 0, sizeof(ptp->cc));
|
||||
ptp->cc.read = bnxt_cc_read;
|
||||
ptp->cc.mask = CYCLECOUNTER_MASK(48);
|
||||
ptp->cc.shift = 0;
|
||||
ptp->cc.mult = 1;
|
||||
|
||||
timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
|
||||
|
||||
ptp->ptp_info = bnxt_ptp_caps;
|
||||
ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
|
||||
if (IS_ERR(ptp->ptp_clock)) {
|
||||
int err = PTR_ERR(ptp->ptp_clock);
|
||||
|
||||
ptp->ptp_clock = NULL;
|
||||
bnxt_unmap_ptp_regs(bp);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void bnxt_ptp_clear(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
|
||||
if (!ptp)
|
||||
return;
|
||||
|
||||
if (ptp->ptp_clock)
|
||||
ptp_clock_unregister(ptp->ptp_clock);
|
||||
|
||||
ptp->ptp_clock = NULL;
|
||||
if (ptp->tx_skb) {
|
||||
dev_kfree_skb_any(ptp->tx_skb);
|
||||
ptp->tx_skb = NULL;
|
||||
}
|
||||
bnxt_unmap_ptp_regs(bp);
|
||||
}
|
||||
81
drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h
Normal file
81
drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h
Normal file
@ -0,0 +1,81 @@
|
||||
/* Broadcom NetXtreme-C/E network driver.
|
||||
*
|
||||
* Copyright (c) 2021 Broadcom Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef BNXT_PTP_H
|
||||
#define BNXT_PTP_H
|
||||
|
||||
#define BNXT_PTP_GRC_WIN 5
|
||||
#define BNXT_PTP_GRC_WIN_BASE 0x5000
|
||||
|
||||
#define BNXT_MAX_PHC_DRIFT 31000000
|
||||
#define BNXT_LO_TIMER_MASK 0x0000ffffffffUL
|
||||
#define BNXT_HI_TIMER_MASK 0xffff00000000UL
|
||||
|
||||
#define BNXT_PTP_QTS_TIMEOUT 1000
|
||||
#define BNXT_PTP_QTS_TX_ENABLES (PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID | \
|
||||
PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT)
|
||||
|
||||
struct bnxt_ptp_cfg {
|
||||
struct ptp_clock_info ptp_info;
|
||||
struct ptp_clock *ptp_clock;
|
||||
struct cyclecounter cc;
|
||||
struct timecounter tc;
|
||||
/* serialize timecounter access */
|
||||
spinlock_t ptp_lock;
|
||||
struct sk_buff *tx_skb;
|
||||
u64 current_time;
|
||||
u64 old_time;
|
||||
unsigned long next_period;
|
||||
u16 tx_seqid;
|
||||
struct bnxt *bp;
|
||||
atomic_t tx_avail;
|
||||
#define BNXT_MAX_TX_TS 1
|
||||
u16 rxctl;
|
||||
#define BNXT_PTP_MSG_SYNC (1 << 0)
|
||||
#define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
|
||||
#define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
|
||||
#define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
|
||||
#define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
|
||||
#define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
|
||||
#define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
|
||||
#define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
|
||||
#define BNXT_PTP_MSG_SIGNALING (1 << 12)
|
||||
#define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
|
||||
#define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
|
||||
BNXT_PTP_MSG_DELAY_REQ | \
|
||||
BNXT_PTP_MSG_PDELAY_REQ | \
|
||||
BNXT_PTP_MSG_PDELAY_RESP)
|
||||
u8 tx_tstamp_en:1;
|
||||
int rx_filter;
|
||||
|
||||
u32 refclk_regs[2];
|
||||
u32 refclk_mapped_regs[2];
|
||||
};
|
||||
|
||||
#if BITS_PER_LONG == 32
|
||||
#define BNXT_READ_TIME64(ptp, dst, src) \
|
||||
do { \
|
||||
spin_lock_bh(&(ptp)->ptp_lock); \
|
||||
(dst) = (src); \
|
||||
spin_unlock_bh(&(ptp)->ptp_lock); \
|
||||
} while (0)
|
||||
#else
|
||||
#define BNXT_READ_TIME64(ptp, dst, src) \
|
||||
((dst) = READ_ONCE(src))
|
||||
#endif
|
||||
|
||||
int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id);
|
||||
int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr);
|
||||
int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);
|
||||
int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb);
|
||||
int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts);
|
||||
void bnxt_ptp_start(struct bnxt *bp);
|
||||
int bnxt_ptp_init(struct bnxt *bp);
|
||||
void bnxt_ptp_clear(struct bnxt *bp);
|
||||
#endif
|
||||
@ -632,7 +632,7 @@ static int bnxt_hwrm_func_cfg(struct bnxt *bp, int num_vfs)
|
||||
vf_vnics = (hw_resc->max_vnics - bp->nr_vnics) / num_vfs;
|
||||
vf_vnics = min_t(u16, vf_vnics, vf_rx_rings);
|
||||
|
||||
req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_MTU |
|
||||
req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ADMIN_MTU |
|
||||
FUNC_CFG_REQ_ENABLES_MRU |
|
||||
FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS |
|
||||
FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS |
|
||||
@ -645,7 +645,7 @@ static int bnxt_hwrm_func_cfg(struct bnxt *bp, int num_vfs)
|
||||
|
||||
mtu = bp->dev->mtu + ETH_HLEN + VLAN_HLEN;
|
||||
req.mru = cpu_to_le16(mtu);
|
||||
req.mtu = cpu_to_le16(mtu);
|
||||
req.admin_mtu = cpu_to_le16(mtu);
|
||||
|
||||
req.num_rsscos_ctxs = cpu_to_le16(1);
|
||||
req.num_cmpl_rings = cpu_to_le16(vf_cp_rings);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user