arm64: dts: imx8mq: Add pwm device nodes
We can reuse the pwm from fsl,imx27-pwm as with other imx SOCs. Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -259,6 +259,50 @@
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x30400000 0x30400000 0x400000>;
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pwm1: pwm@30660000 {
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compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
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reg = <0x30660000 0x10000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
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<&clk IMX8MQ_CLK_PWM1_ROOT>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm2: pwm@30670000 {
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compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
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reg = <0x30670000 0x10000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
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<&clk IMX8MQ_CLK_PWM2_ROOT>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm3: pwm@30680000 {
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compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
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reg = <0x30680000 0x10000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
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<&clk IMX8MQ_CLK_PWM3_ROOT>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm4: pwm@30690000 {
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compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
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reg = <0x30690000 0x10000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
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<&clk IMX8MQ_CLK_PWM4_ROOT>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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status = "disabled";
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};
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};
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bus@30800000 { /* AIPS3 */
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