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drm/amdgpu: update RAS TA to Host interface

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Update interface to match latest TA

Organized input/output structures to better maintain backward compatiblity in the future

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
John Clements 2020-04-30 17:11:59 +08:00 committed by Alex Deucher
parent a200034b66
commit a0d254820f
1 changed files with 42 additions and 17 deletions
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59
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
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@ -24,6 +24,8 @@
#ifndef _TA_RAS_IF_H
#define _TA_RAS_IF_H
#define RAS_TA_HOST_IF_VER 0
/* Responses have bit 31 set */
#define RSP_ID_MASK (1U << 31)
#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
@ -36,18 +38,24 @@ enum ras_command {
TA_RAS_COMMAND__TRIGGER_ERROR,
};
enum ta_ras_status {
TA_RAS_STATUS__SUCCESS = 0x00,
TA_RAS_STATUS__RESET_NEEDED = 0x01,
TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0x02,
TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0x03,
TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0x04,
TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0x05,
TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0x06,
TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0x07,
TA_RAS_STATUS__ERROR_TIMEOUT = 0x08,
TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0x09,
TA_RAS_STATUS__ERROR_GENERIC = 0x10,
enum ta_ras_status
{
TA_RAS_STATUS__SUCCESS = 0x00,
TA_RAS_STATUS__RESET_NEEDED = 0xA001,
TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0xA002,
TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003,
TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004,
TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0xA005,
TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0xA006,
TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007,
TA_RAS_STATUS__ERROR_TIMEOUT = 0xA008,
TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0XA009,
TA_RAS_STATUS__ERROR_GENERIC = 0xA00A,
TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B,
TA_RAS_STATUS__ERROR_GET_DEV_INFO = 0xA00C,
TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D,
TA_RAS_STATUS__ERROR_NOT_INITIALIZED = 0xA00E,
TA_RAS_STATUS__ERROR_TEE_INTERNAL = 0xA00F
};
enum ta_ras_block {
@ -97,22 +105,39 @@ struct ta_ras_trigger_error_input {
uint64_t value; // method if error injection. i.e persistent, coherent etc.
};
struct ta_ras_output_flags
{
uint8_t ras_init_success_flag;
uint8_t err_inject_switch_disable_flag;
uint8_t reg_access_failure_flag;
};
/* Common input structure for RAS callbacks */
/**********************************************************/
union ta_ras_cmd_input {
struct ta_ras_enable_features_input enable_features;
struct ta_ras_disable_features_input disable_features;
struct ta_ras_trigger_error_input trigger_error;
uint32_t reserve_pad[256];
};
union ta_ras_cmd_output
{
struct ta_ras_output_flags flags;
uint32_t reserve_pad[256];
};
/* Shared Memory structures */
/**********************************************************/
struct ta_ras_shared_memory {
uint32_t cmd_id;
uint32_t resp_id;
enum ta_ras_status ras_status;
uint32_t reserved;
union ta_ras_cmd_input ras_in_message;
uint32_t cmd_id;
uint32_t resp_id;
uint32_t ras_status;
uint32_t if_version;
union ta_ras_cmd_input ras_in_message;
union ta_ras_cmd_output ras_out_message;
};
#endif // TL_RAS_IF_H_