forked from Minki/linux
drm/amdgpu: update RAS TA to Host interface
Update interface to match latest TA Organized input/output structures to better maintain backward compatiblity in the future Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -24,6 +24,8 @@
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#ifndef _TA_RAS_IF_H
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#ifndef _TA_RAS_IF_H
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#define _TA_RAS_IF_H
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#define _TA_RAS_IF_H
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#define RAS_TA_HOST_IF_VER 0
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/* Responses have bit 31 set */
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/* Responses have bit 31 set */
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#define RSP_ID_MASK (1U << 31)
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#define RSP_ID_MASK (1U << 31)
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#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
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#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
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@ -36,18 +38,24 @@ enum ras_command {
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TA_RAS_COMMAND__TRIGGER_ERROR,
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TA_RAS_COMMAND__TRIGGER_ERROR,
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};
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};
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enum ta_ras_status {
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enum ta_ras_status
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TA_RAS_STATUS__SUCCESS = 0x00,
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{
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TA_RAS_STATUS__RESET_NEEDED = 0x01,
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TA_RAS_STATUS__SUCCESS = 0x00,
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TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0x02,
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TA_RAS_STATUS__RESET_NEEDED = 0xA001,
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TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0x03,
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TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0xA002,
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TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0x04,
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TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003,
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TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0x05,
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TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004,
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TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0x06,
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TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0xA005,
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TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0x07,
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TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0xA006,
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TA_RAS_STATUS__ERROR_TIMEOUT = 0x08,
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TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007,
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TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0x09,
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TA_RAS_STATUS__ERROR_TIMEOUT = 0xA008,
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TA_RAS_STATUS__ERROR_GENERIC = 0x10,
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TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0XA009,
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TA_RAS_STATUS__ERROR_GENERIC = 0xA00A,
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TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B,
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TA_RAS_STATUS__ERROR_GET_DEV_INFO = 0xA00C,
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TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D,
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TA_RAS_STATUS__ERROR_NOT_INITIALIZED = 0xA00E,
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TA_RAS_STATUS__ERROR_TEE_INTERNAL = 0xA00F
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};
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};
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enum ta_ras_block {
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enum ta_ras_block {
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@ -97,22 +105,39 @@ struct ta_ras_trigger_error_input {
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uint64_t value; // method if error injection. i.e persistent, coherent etc.
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uint64_t value; // method if error injection. i.e persistent, coherent etc.
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};
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};
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struct ta_ras_output_flags
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{
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uint8_t ras_init_success_flag;
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uint8_t err_inject_switch_disable_flag;
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uint8_t reg_access_failure_flag;
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};
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/* Common input structure for RAS callbacks */
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/* Common input structure for RAS callbacks */
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/**********************************************************/
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/**********************************************************/
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union ta_ras_cmd_input {
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union ta_ras_cmd_input {
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struct ta_ras_enable_features_input enable_features;
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struct ta_ras_enable_features_input enable_features;
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struct ta_ras_disable_features_input disable_features;
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struct ta_ras_disable_features_input disable_features;
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struct ta_ras_trigger_error_input trigger_error;
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struct ta_ras_trigger_error_input trigger_error;
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uint32_t reserve_pad[256];
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};
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union ta_ras_cmd_output
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{
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struct ta_ras_output_flags flags;
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uint32_t reserve_pad[256];
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};
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};
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/* Shared Memory structures */
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/* Shared Memory structures */
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/**********************************************************/
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/**********************************************************/
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struct ta_ras_shared_memory {
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struct ta_ras_shared_memory {
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uint32_t cmd_id;
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uint32_t cmd_id;
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uint32_t resp_id;
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uint32_t resp_id;
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enum ta_ras_status ras_status;
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uint32_t ras_status;
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uint32_t reserved;
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uint32_t if_version;
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union ta_ras_cmd_input ras_in_message;
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union ta_ras_cmd_input ras_in_message;
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union ta_ras_cmd_output ras_out_message;
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};
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};
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#endif // TL_RAS_IF_H_
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#endif // TL_RAS_IF_H_
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