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* meson: OSD burst-length fixes

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* hibmc: fix runtime warning by setting up generic fbdev after
    registering device
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Merge tag 'drm-misc-fixes-2020-07-08' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes

 * meson: OSD burst-length fixes
 * hibmc: fix runtime warning by setting up generic fbdev after
   registering device

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20200708121050.GA29420@linux-uq9g
This commit is contained in:
Dave Airlie 2020-07-10 06:46:47 +10:00
commit a088eb0faf
3 changed files with 11 additions and 11 deletions
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5
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
View File

@ -307,8 +307,6 @@ static int hibmc_load(struct drm_device *dev)
/* reset all the states of crtc/plane/encoder/connector */
drm_mode_config_reset(dev);
drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
return 0;
err:
@ -355,6 +353,9 @@ static int hibmc_pci_probe(struct pci_dev *pdev,
ret);
goto err_unload;
}
drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
return 0;
err_unload:

6
drivers/gpu/drm/meson/meson_registers.h
View File

@ -261,6 +261,12 @@
#define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12)
#define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22)
#define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24)
#define VIU_OSD_BURST_LENGTH_24 (0x0 << 31 | 0x0 << 10)
#define VIU_OSD_BURST_LENGTH_32 (0x0 << 31 | 0x1 << 10)
#define VIU_OSD_BURST_LENGTH_48 (0x0 << 31 | 0x2 << 10)
#define VIU_OSD_BURST_LENGTH_64 (0x0 << 31 | 0x3 << 10)
#define VIU_OSD_BURST_LENGTH_96 (0x1 << 31 | 0x0 << 10)
#define VIU_OSD_BURST_LENGTH_128 (0x1 << 31 | 0x1 << 10)
#define VD1_IF0_GEN_REG 0x1a50
#define VD1_IF0_CANVAS0 0x1a51

11
drivers/gpu/drm/meson/meson_viu.c
View File

@ -411,13 +411,6 @@ void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv)
priv->io_base + _REG(VIU_MISC_CTRL1));
}
static inline uint32_t meson_viu_osd_burst_length_reg(uint32_t length)
{
uint32_t val = (((length & 0x80) % 24) / 12);
return (((val & 0x3) << 10) | (((val & 0x4) >> 2) << 31));
}
void meson_viu_init(struct meson_drm *priv)
{
uint32_t reg;
@ -444,9 +437,9 @@ void meson_viu_init(struct meson_drm *priv)
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
reg |= meson_viu_osd_burst_length_reg(32);
reg |= VIU_OSD_BURST_LENGTH_32;
else
reg |= meson_viu_osd_burst_length_reg(64);
reg |= VIU_OSD_BURST_LENGTH_64;
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));