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drm/i915: Drop remaining pre-Ironlake code from ironlake_crtc_mode_set().

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Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Eric Anholt 2011-03-30 13:01:08 -07:00 committed by Keith Packard
parent 8febb2974f
commit a07d678705
1 changed files with 36 additions and 83 deletions
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119
drivers/gpu/drm/i915/intel_display.c
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@ -4924,7 +4924,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
int refclk, num_connectors = 0; int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock; intel_clock_t clock, reduced_clock;
u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; bool ok, has_reduced_clock = false, is_sdvo = false;
bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
struct intel_encoder *has_edp_encoder = NULL; struct intel_encoder *has_edp_encoder = NULL;
struct drm_mode_config *mode_config = &dev->mode_config; struct drm_mode_config *mode_config = &dev->mode_config;
@ -4950,9 +4950,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
if (encoder->needs_tv_clock) if (encoder->needs_tv_clock)
is_tv = true; is_tv = true;
break; break;
case INTEL_OUTPUT_DVO:
is_dvo = true;
break;
case INTEL_OUTPUT_TVOUT: case INTEL_OUTPUT_TVOUT:
is_tv = true; is_tv = true;
break; break;
@ -4974,13 +4971,11 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
refclk = dev_priv->lvds_ssc_freq * 1000; refclk = dev_priv->lvds_ssc_freq * 1000;
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
refclk / 1000); refclk / 1000);
} else if (!IS_GEN2(dev)) { } else {
refclk = 96000; refclk = 96000;
if (!has_edp_encoder || if (!has_edp_encoder ||
intel_encoder_is_pch_edp(&has_edp_encoder->base)) intel_encoder_is_pch_edp(&has_edp_encoder->base))
refclk = 120000; /* 120Mhz refclk */ refclk = 120000; /* 120Mhz refclk */
} else {
refclk = 48000;
} }
/* /*
@ -5169,17 +5164,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
udelay(200); udelay(200);
} }
if (IS_PINEVIEW(dev)) { fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; if (has_reduced_clock)
if (has_reduced_clock) fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
fp2 = (1 << reduced_clock.n) << 16 | reduced_clock.m2;
reduced_clock.m1 << 8 | reduced_clock.m2;
} else {
fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
if (has_reduced_clock)
fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
reduced_clock.m2;
}
/* Enable autotuning of the PLL clock (if permissible) */ /* Enable autotuning of the PLL clock (if permissible) */
factor = 21; factor = 21;
@ -5196,59 +5184,38 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
dpll = 0; dpll = 0;
if (!IS_GEN2(dev)) { if (is_lvds)
if (is_lvds) dpll |= DPLLB_MODE_LVDS;
dpll |= DPLLB_MODE_LVDS; else
else dpll |= DPLLB_MODE_DAC_SERIAL;
dpll |= DPLLB_MODE_DAC_SERIAL; if (is_sdvo) {
if (is_sdvo) { int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); if (pixel_multiplier > 1) {
if (pixel_multiplier > 1) { dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
else
dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
}
dpll |= DPLL_DVO_HIGH_SPEED;
} }
if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) dpll |= DPLL_DVO_HIGH_SPEED;
dpll |= DPLL_DVO_HIGH_SPEED; }
if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
dpll |= DPLL_DVO_HIGH_SPEED;
/* compute bitmask from p1 value */ /* compute bitmask from p1 value */
if (IS_PINEVIEW(dev)) dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; /* also FPA1 */
else { dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
/* also FPA1 */ switch (clock.p2) {
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; case 5:
if (IS_G4X(dev) && has_reduced_clock) dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; break;
} case 7:
switch (clock.p2) { dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
case 5: break;
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; case 10:
break; dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
case 7: break;
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; case 14:
break; dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
case 10: break;
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
break;
case 14:
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
} else {
if (is_lvds) {
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
} else {
if (clock.p1 == 2)
dpll |= PLL_P1_DIVIDE_BY_TWO;
else
dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
if (clock.p2 == 4)
dpll |= PLL_P2_DIVIDE_BY_4;
}
} }
if (is_sdvo && is_tv) if (is_sdvo && is_tv)
@ -5268,20 +5235,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
/* Set up the display plane register */ /* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE; dspcntr = DISPPLANE_GAMMA_ENABLE;
if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
/* Enable pixel doubling when the dot clock is > 90% of the (display)
* core speed.
*
* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
* pipe == 0 check?
*/
if (mode->clock >
dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
pipeconf |= PIPECONF_DOUBLE_WIDE;
else
pipeconf &= ~PIPECONF_DOUBLE_WIDE;
}
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
drm_mode_debug_printmodeline(mode); drm_mode_debug_printmodeline(mode);