forked from Minki/linux
Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 topology discovery improvements from Ingo Molnar: "These changes improve topology discovery on AMD CPUs. Right now this feeds information displayed in /sys/devices/system/cpu/cpuX/cache/indexY/* - but in the future we could use this to set up a better scheduling topology." * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, cacheinfo: Base cache sharing info on CPUID 0x8000001d on AMD x86, cacheinfo: Make use of CPUID 0x8000001d for cache information on AMD x86, cacheinfo: Determine number of cache leafs using CPUID 0x8000001d on AMD x86: Add cpu_has_topoext
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commit
a05a4e24dc
@ -311,6 +311,7 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
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#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
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#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
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#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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@ -187,7 +187,7 @@ extern void print_cpu_info(struct cpuinfo_x86 *);
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void print_cpu_msr(struct cpuinfo_x86 *);
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern unsigned short num_cache_leaves;
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extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
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extern void detect_extended_topology(struct cpuinfo_x86 *c);
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extern void detect_ht(struct cpuinfo_x86 *c);
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@ -304,7 +304,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
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int cpu = smp_processor_id();
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/* get information required for multi-node processors */
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if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
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if (cpu_has_topoext) {
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u32 eax, ebx, ecx, edx;
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cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
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@ -657,12 +657,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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detect_ht(c);
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#endif
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if (c->extended_cpuid_level >= 0x80000006) {
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if (cpuid_edx(0x80000006) & 0xf000)
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num_cache_leaves = 4;
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else
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num_cache_leaves = 3;
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}
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init_amd_cacheinfo(c);
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if (c->x86 >= 0xf)
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set_cpu_cap(c, X86_FEATURE_K8);
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@ -538,7 +538,11 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
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unsigned edx;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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amd_cpuid4(index, &eax, &ebx, &ecx);
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if (cpu_has_topoext)
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cpuid_count(0x8000001d, index, &eax.full,
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&ebx.full, &ecx.full, &edx);
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else
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amd_cpuid4(index, &eax, &ebx, &ecx);
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amd_init_l3_cache(this_leaf, index);
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} else {
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cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
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@ -557,21 +561,39 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
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return 0;
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}
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static int __cpuinit find_num_cache_leaves(void)
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static int __cpuinit find_num_cache_leaves(struct cpuinfo_x86 *c)
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{
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unsigned int eax, ebx, ecx, edx;
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unsigned int eax, ebx, ecx, edx, op;
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union _cpuid4_leaf_eax cache_eax;
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int i = -1;
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if (c->x86_vendor == X86_VENDOR_AMD)
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op = 0x8000001d;
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else
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op = 4;
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do {
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++i;
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/* Do cpuid(4) loop to find out num_cache_leaves */
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cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
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/* Do cpuid(op) loop to find out num_cache_leaves */
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cpuid_count(op, i, &eax, &ebx, &ecx, &edx);
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cache_eax.full = eax;
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} while (cache_eax.split.type != CACHE_TYPE_NULL);
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return i;
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}
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void __cpuinit init_amd_cacheinfo(struct cpuinfo_x86 *c)
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{
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if (cpu_has_topoext) {
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num_cache_leaves = find_num_cache_leaves(c);
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} else if (c->extended_cpuid_level >= 0x80000006) {
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if (cpuid_edx(0x80000006) & 0xf000)
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num_cache_leaves = 4;
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else
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num_cache_leaves = 3;
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}
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}
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unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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{
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/* Cache sizes */
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@ -588,7 +610,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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if (is_initialized == 0) {
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/* Init num_cache_leaves from boot CPU */
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num_cache_leaves = find_num_cache_leaves();
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num_cache_leaves = find_num_cache_leaves(c);
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is_initialized++;
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}
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@ -728,12 +750,36 @@ static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
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static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
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{
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struct _cpuid4_info *this_leaf;
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int ret, i, sibling;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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int i, sibling;
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ret = 0;
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if (index == 3) {
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ret = 1;
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if (cpu_has_topoext) {
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unsigned int apicid, nshared, first, last;
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if (!per_cpu(ici_cpuid4_info, cpu))
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return 0;
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this_leaf = CPUID4_INFO_IDX(cpu, index);
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nshared = this_leaf->base.eax.split.num_threads_sharing + 1;
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apicid = cpu_data(cpu).apicid;
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first = apicid - (apicid % nshared);
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last = first + nshared - 1;
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for_each_online_cpu(i) {
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apicid = cpu_data(i).apicid;
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if ((apicid < first) || (apicid > last))
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continue;
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if (!per_cpu(ici_cpuid4_info, i))
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continue;
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this_leaf = CPUID4_INFO_IDX(i, index);
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for_each_online_cpu(sibling) {
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apicid = cpu_data(sibling).apicid;
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if ((apicid < first) || (apicid > last))
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continue;
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set_bit(sibling, this_leaf->shared_cpu_map);
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}
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}
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} else if (index == 3) {
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for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
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if (!per_cpu(ici_cpuid4_info, i))
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continue;
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@ -744,21 +790,10 @@ static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
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set_bit(sibling, this_leaf->shared_cpu_map);
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}
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}
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} else if ((c->x86 == 0x15) && ((index == 1) || (index == 2))) {
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ret = 1;
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for_each_cpu(i, cpu_sibling_mask(cpu)) {
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if (!per_cpu(ici_cpuid4_info, i))
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continue;
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this_leaf = CPUID4_INFO_IDX(i, index);
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for_each_cpu(sibling, cpu_sibling_mask(cpu)) {
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if (!cpu_online(sibling))
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continue;
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set_bit(sibling, this_leaf->shared_cpu_map);
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}
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}
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}
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} else
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return 0;
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return ret;
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return 1;
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}
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static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
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@ -332,7 +332,7 @@ do { \
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static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
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{
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if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
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if (cpu_has_topoext) {
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int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
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if (c->phys_proc_id == o->phys_proc_id &&
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