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Renesas ARM DT updates for v5.9

Browse Source 
- Increase support for the Renesas RZ/G1H SoC on the iWave RainboW
     Qseven board (G21D), and its camera expansion board,
   - IPMMU support for R-Car M3-W+,
   - Support for Rev.3.0/4.0 of the HopeRun HiHope RZ/G2M and RZ/G2N
     boards,
   - Minor fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.9

  - Increase support for the Renesas RZ/G1H SoC on the iWave RainboW
    Qseven board (G21D), and its camera expansion board,
  - IPMMU support for R-Car M3-W+,
  - Support for Rev.3.0/4.0 of the HopeRun HiHope RZ/G2M and RZ/G2N
    boards,
  - Minor fixes and improvements.

* tag 'renesas-arm-dt-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (36 commits)
  ARM: dts: r8a7778: Enable IRLM setup via DT
  arm64: dts: renesas: Add HiHope RZ/G2N Rev2.0/3.0/4.0 board with idk-1110wr display
  arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 sub board support
  arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 main board support
  arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 board with idk-1110wr display
  arm64: dts: renesas: hihope-rzg2-ex: Separate out lvds specific nodes into common file
  arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 sub board support
  arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 main board support
  arm64: dts: renesas: Add HiHope RZ/G2M[N] Rev.3.0/4.0 specific into common file
  arm64: dts: renesas: hihope-common: Separate out Rev.2.0 specific into hihope-rev2.dtsi file
  arm64: dts: renesas: r8a774b1-hihope-rzg2n[-ex]: Rename HiHope RZ/G2N boards
  arm64: dts: renesas: r8a774a1-hihope-rzg2m[-ex/-ex-idk-1110wr]: Rename HiHope RZ/G2M boards
  arm64: dts: renesas: r8a77961: Add IPMMU nodes
  ARM: dts: r8a7742: Add MSIOF[0123] support
  ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add device tree for camera DB
  ARM: dts: r8a7742: Add CMT SoC specific support
  ARM: dts: r8a7742: Add thermal device to DT
  ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS
  ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec
  ARM: dts: r8a7742: Add audio support
  ...

Link: https://lore.kernel.org/r/20200703120642.5128-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-07-06 17:41:24 +02:00
commit 9f0d16ebe3
27 changed files with 1687 additions and 161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -927,6 +927,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7742-iwg21d-q7.dtb \
r8a7742-iwg21d-q7-dbcm-ca.dtb \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \

97
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts Normal file
View File

@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the iWave-RZ/G1H Qseven board development
* platform with camera daughter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a7742-iwg21d-q7.dts"
/ {
model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
aliases {
serial0 = &scif0;
serial1 = &scif1;
serial3 = &scifb1;
serial5 = &hscif0;
ethernet1 = &ether;
};
};
&avb {
/* Pins shared with VIN0, keep status disabled */
status = "disabled";
};
&ether {
pinctrl-0 = <&ether_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <1>;
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&pfc {
ether_pins: ether {
groups = "eth_mdio", "eth_rmii";
function = "eth";
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif1_pins: scif1 {
groups = "scif1_data";
function = "scif1";
};
scifb1_pins: scifb1 {
groups = "scifb1_data";
function = "scifb1";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
status = "okay";
};
&scifb1 {
pinctrl-0 = <&scifb1_pins>;
pinctrl-names = "default";
status = "okay";
rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
};

187
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
View File

@ -5,6 +5,29 @@
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/*
* SSI-SGTL5000
*
* This command is required when Playback/Capture
*
* amixer set "DVC Out" 100%
* amixer set "DVC In" 100%
*
* You can use Mute
*
* amixer set "DVC Out Mute" on
* amixer set "DVC In Mute" on
*
* You can use Volume Ramp
*
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
* amixer set "DVC Out Ramp" on
* aplay xxx.wav &
* amixer set "DVC Out" 80% // Volume Down
* amixer set "DVC Out" 100% // Volume Up
*/
/dts-v1/;
#include "r8a7742-iwg21m.dtsi"
@ -14,19 +37,158 @@
aliases {
serial2 = &scifa2;
serial4 = &scifb2;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait";
stdout-path = "serial2:115200n8";
};
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
reg_1p5v: 1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
rsnd_sgtl5000: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
};
};
vcc_sdhi2: regulator-vcc-sdhi2 {
compatible = "regulator-fixed";
regulator-name = "SDHI2 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
};
vccq_sdhi2: regulator-vccq-sdhi2 {
compatible = "regulator-gpio";
regulator-name = "SDHI2 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
micrel,led-mode = <1>;
};
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
#sound-dai-cells = <0>;
reg = <0x0a>;
clocks = <&audio_clock>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
VDDD-supply = <&reg_1p5v>;
};
};
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
i2c2_pins: i2c2 {
groups = "i2c2_b";
function = "i2c2";
};
scifa2_pins: scifa2 {
groups = "scifa2_data_c";
function = "scifa2";
};
scifb2_pins: scifb2 {
groups = "scifb2_data", "scifb2_ctrl";
function = "scifb2";
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
function = "ssi";
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins>;
pinctrl-names = "default";
status = "okay";
/* Single DAI */
#sound-dai-cells = <0>;
rcar_sound,dai {
dai0 {
playback = <&ssi4 &src4 &dvc1>;
capture = <&ssi3 &src3 &dvc0>;
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scifa2 {
@ -35,3 +197,28 @@
status = "okay";
};
&scifb2 {
pinctrl-0 = <&scifb2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
status = "okay";
};
&ssi4 {
shared-pin;
};

854
arch/arm/boot/dts/r8a7742.dtsi
View File

@ -15,9 +15,31 @@
#address-cells = <2>;
#size-cells = <2>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -200,6 +222,17 @@
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7742-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
@ -305,6 +338,18 @@
#reset-cells = <1>;
};
apmu@e6151000 {
compatible = "renesas,r8a7742-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
};
apmu@e6152000 {
compatible = "renesas,r8a7742-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7742-rst";
reg = <0 0xe6160000 0 0x0100>;
@ -330,6 +375,17 @@
resets = <&cpg 407>;
};
thermal: thermal@e61f0000 {
compatible = "renesas,thermal-r8a7742",
"renesas,rcar-gen2-thermal";
reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <0>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
@ -359,6 +415,195 @@
ranges = <0 0 0xe6300000 0x40000>;
};
i2c0: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7742",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 931>;
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c1: i2c@e6518000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7742",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6518000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 930>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6530000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7742",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6530000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 929>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e6540000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7742",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6540000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 928>;
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
iic0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7742",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe6500000 0 0x425>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>,
<&dmac1 0x61>, <&dmac1 0x62>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 318>;
status = "disabled";
};
iic1: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7742",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe6510000 0 0x425>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 323>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>,
<&dmac1 0x65>, <&dmac1 0x66>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 323>;
status = "disabled";
};
iic2: i2c@e6520000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7742",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe6520000 0 0x425>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
<&dmac1 0x69>, <&dmac1 0x6a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
iic3: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7742";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>,
<&dmac1 0x77>, <&dmac1 0x78>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 926>;
status = "disabled";
};
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7742",
"renesas,rcar-gen2-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 704>;
renesas,buswait = <4>;
phys = <&usb0 1>;
phy-names = "usb";
status = "disabled";
};
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7742",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 704>;
clock-names = "usbhs";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
usb0: usb-channel@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-channel@2 {
reg = <2>;
#phy-cells = <1>;
};
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7742-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,r8a7742-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7742",
"renesas,rcar-dmac";
@ -425,6 +670,19 @@
dma-channels = <15>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7742",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7742",
"renesas,rcar-gen2-scifa", "renesas,scifa";
@ -595,6 +853,515 @@
status = "disabled";
};
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7742",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
<&dmac1 0x51>, <&dmac1 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6e10000 {
compatible = "renesas,msiof-r8a7742",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e10000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
<&dmac1 0x55>, <&dmac1 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6e00000 {
compatible = "renesas,msiof-r8a7742",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 205>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>,
<&dmac1 0x41>, <&dmac1 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 205>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c90000 {
compatible = "renesas,msiof-r8a7742",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6c90000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 215>;
dmas = <&dmac0 0x45>, <&dmac0 0x46>,
<&dmac1 0x45>, <&dmac1 0x46>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 215>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a7742",
"renesas,rcar_sound-gen2";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
<&cpg CPG_CORE R8A7742_CLK_M2>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
"ssi.1", "ssi.0",
"src.9", "src.8", "src.7", "src.6",
"src.5", "src.4", "src.3", "src.2",
"src.1", "src.0",
"ctu.0", "ctu.1",
"mix.0", "mix.1",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 1005>,
<&cpg 1006>, <&cpg 1007>,
<&cpg 1008>, <&cpg 1009>,
<&cpg 1010>, <&cpg 1011>,
<&cpg 1012>, <&cpg 1013>,
<&cpg 1014>, <&cpg 1015>;
reset-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
"ssi.1", "ssi.0";
status = "disabled";
rcar_sound,dvc {
dvc0: dvc-0 {
dmas = <&audma1 0xbc>;
dma-names = "tx";
};
dvc1: dvc-1 {
dmas = <&audma1 0xbe>;
dma-names = "tx";
};
};
rcar_sound,mix {
mix0: mix-0 { };
mix1: mix-1 { };
};
rcar_sound,ctu {
ctu00: ctu-0 { };
ctu01: ctu-1 { };
ctu02: ctu-2 { };
ctu03: ctu-3 { };
ctu10: ctu-4 { };
ctu11: ctu-5 { };
ctu12: ctu-6 { };
ctu13: ctu-7 { };
};
rcar_sound,src {
src0: src-0 {
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x85>, <&audma1 0x9a>;
dma-names = "rx", "tx";
};
src1: src-1 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x87>, <&audma1 0x9c>;
dma-names = "rx", "tx";
};
src2: src-2 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x89>, <&audma1 0x9e>;
dma-names = "rx", "tx";
};
src3: src-3 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
dma-names = "rx", "tx";
};
src4: src-4 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
dma-names = "rx", "tx";
};
src5: src-5 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
dma-names = "rx", "tx";
};
src6: src-6 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma1 0xb4>;
dma-names = "rx", "tx";
};
src7: src-7 {
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x93>, <&audma1 0xb6>;
dma-names = "rx", "tx";
};
src8: src-8 {
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x95>, <&audma1 0xb8>;
dma-names = "rx", "tx";
};
src9: src-9 {
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x97>, <&audma1 0xba>;
dma-names = "rx", "tx";
};
};
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>,
<&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>,
<&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>,
<&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>,
<&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>,
<&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>,
<&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>,
<&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>,
<&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>,
<&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx", "rxu", "txu";
};
};
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a7742",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <13>;
};
audma1: dma-controller@ec720000 {
compatible = "renesas,dmac-r8a7742",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <13>;
};
xhci: usb@ee000000 {
compatible = "renesas,xhci-r8a7742",
"renesas,rcar-gen2-xhci";
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 328>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
};
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7742",
"renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
phys = <&usb0 0>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x1000 0 0 0 0>;
phys = <&usb0 0>;
phy-names = "usb";
};
};
pci1: pci@ee0b0000 {
compatible = "renesas,pci-r8a7742",
"renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee0b0000 0 0xc00>,
<0 0xee0a0000 0 0x1100>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
bus-range = <1 1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
pci2: pci@ee0d0000 {
compatible = "renesas,pci-r8a7742",
"renesas,pci-rcar-gen2";
device_type = "pci";
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 703>;
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
bus-range = <2 2>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x20800 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x21000 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
<&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 313>;
status = "disabled";
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
};
mmcif0: mmc@ee200000 {
compatible = "renesas,mmcif-r8a7742",
"renesas,sh-mmcif";
reg = <0 0xee200000 0 0x80>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 315>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
<&dmac1 0xd1>, <&dmac1 0xd2>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 315>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
};
mmcif1: mmc@ee220000 {
compatible = "renesas,mmcif-r8a7742",
"renesas,sh-mmcif";
@ -611,6 +1378,42 @@
max-frequency = <97500000>;
};
sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7742",
"renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 815>;
status = "disabled";
};
sata1: sata@ee500000 {
compatible = "renesas,sata-r8a7742",
"renesas,rcar-gen2-sata";
reg = <0 0xee500000 0 0x200000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 814>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 814>;
status = "disabled";
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7742",
"renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 813>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -629,6 +1432,57 @@
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
cmt0: timer@ffca0000 {
compatible = "renesas,r8a7742-cmt0",
"renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a7742-cmt1",
"renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 329>;
clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 329>;
status = "disabled";
};
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal>;
trips {
cpu-crit {
temperature = <95000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};
timer {

3
arch/arm/boot/dts/r8a7778.dtsi
View File

@ -78,7 +78,8 @@
<0xfe780010 4>,
<0xfe780024 4>,
<0xfe780044 4>,
<0xfe780064 4>;
<0xfe780064 4>,
<0xfe780000 4>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/boot/dts/r9a06g032.dtsi
View File

@ -174,7 +174,7 @@
};
gic: interrupt-controller@44101000 {
compatible = "arm,cortex-a7-gic", "arm,gic-400";
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x44101000 0x1000>, /* Distributer */

17
arch/arm64/boot/dts/renesas/Makefile
View File

@ -1,9 +1,16 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb \
r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb \
r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb \
r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb \
r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb \
r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \
r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
r8a774c0-ek874-idk-2121wr.dtb \
r8a774c0-ek874-mipi-2.1.dtb

71
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] main board common parts
* Device Tree Source for the HiHope RZ/G2[MN] main board
* Rev.[2.0/3.0/4.0] common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
@ -32,17 +33,6 @@
leds {
compatible = "gpio-leds";
bt_active_led {
label = "blue:bt";
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
led0 {
gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
};
led1 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
@ -55,11 +45,8 @@
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
};
wlan_active_led {
label = "yellow:wlan";
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
led4 {
gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
};
};
@ -112,17 +99,6 @@
states = <3300000 1>, <1800000 0>;
};
wlan_en_reg: regulator-wlan_en {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <70000>;
gpio = <&gpio_expander 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
x302_clk: x302-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -194,11 +170,6 @@
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio_expander 2 GPIO_ACTIVE_HIGH>;
};
};
&hsusb {
@ -210,13 +181,6 @@
clock-frequency = <400000>;
status = "okay";
gpio_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
versaclock5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
@ -281,11 +245,6 @@
power-source = <1800>;
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a";
function = "audio_clk";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@ -309,28 +268,6 @@
};
};
&rcar_sound {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
status = "okay";
/* Single DAI */
#sound-dai-cells = <0>;
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint>;
frame-master = <&rsnd_endpoint>;
playback = <&ssi2>;
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

86
arch/arm64/boot/dts/renesas/hihope-rev2.dtsi Normal file
View File

@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] main board Rev.2.0 common
* parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include "hihope-common.dtsi"
/ {
leds {
compatible = "gpio-leds";
bt_active_led {
label = "blue:bt";
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
wlan_active_led {
label = "yellow:wlan";
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
};
wlan_en_reg: regulator-wlan_en {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <70000>;
gpio = <&gpio_expander 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&hscif0 {
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio_expander 2 GPIO_ACTIVE_HIGH>;
};
};
&i2c4 {
gpio_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&pfc {
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a";
function = "audio_clk";
};
};
&rcar_sound {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
status = "okay";
/* Single DAI */
#sound-dai-cells = <0>;
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint>;
frame-master = <&rsnd_endpoint>;
playback = <&ssi2>;
};
};
};

124
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi Normal file
View File

@ -0,0 +1,124 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] Rev.3.0/4.0 main board
* common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include "hihope-common.dtsi"
/ {
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
};
wlan_en_reg: regulator-wlan_en {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <70000>;
gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
x1801_clk: x1801-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
&hscif0 {
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
};
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
cs2000: clk_multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x1801_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&pfc {
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
status = "okay";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint>;
frame-master = <&rsnd_endpoint>;
playback = <&ssi2>;
};
};
};

52
arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi Normal file
View File

@ -0,0 +1,52 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/ {
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 50000>;
brightness-levels = <0 2 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
&gpio1 {
/*
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-gpio {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&lvds0 {
ports {
port@1 {
lvds_connector: endpoint {
};
};
};
};
&pfc {
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};

37
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
View File

@ -13,14 +13,6 @@
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 50000>;
brightness-levels = <0 2 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
&avb {
@ -51,35 +43,6 @@
status = "okay";
};
&gpio1 {
/*
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-gpio {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&lvds0 {
/*
* Please include the LVDS panel .dtsi file and uncomment the below line
* to enable LVDS panel connected to RZ/G2[MN] boards.
*/
/* status = "okay"; */
ports {
port@1 {
lvds_connector: endpoint {
};
};
};
};
&pciec0 {
status = "okay";
};

43
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts
View File

@ -1,52 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M sub board connected to an
* Advantech IDK-1110WR 10.1" LVDS panel
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 sub board connected
* to an Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
/ {
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 50000>;
brightness-levels = <0 2 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
&gpio1 {
/*
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-gpio {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&lvds0 {
status = "okay";
};
&pfc {
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};

6
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M sub board
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to
* sub board
*
* Copyright (C) 2019 Renesas Electronics Corp.
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m.dts"
@ -14,6 +15,7 @@
"renesas,r8a774a1";
};
/* SW43 should be OFF, if in ON state SATA port will be activated */
&pciec1 {
status = "okay";
};

15
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.2.0 sub board connected to an
* Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m-rev2-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};

20
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.2.0 connected to sub board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m-rev2.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M (Rev.2.0) with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
"renesas,r8a774a1";
};
/* SW43 should be OFF, if in ON state SATA port will be activated */
&pciec1 {
status = "okay";
};

37
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2.dts Normal file
View File

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.2.0 main board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774a1.dtsi"
#include "hihope-rev2.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M main board (Rev.2.0) based on r8a774a1";
compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};

6
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts
View File

@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M main board
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board
*
* Copyright (C) 2019 Renesas Electronics Corp.
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774a1.dtsi"
#include "hihope-common.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M main board based on r8a774a1";

2
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -10,6 +10,8 @@
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include <dt-bindings/power/r8a774a1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
/ {
compatible = "renesas,r8a774a1";
#address-cells = <2>;

15
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 with sub board connected
* to an Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};

5
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N sub board
* Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
* sub board
*
* Copyright (C) 2019 Renesas Electronics Corp.
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n.dts"

15
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.2.0 with sub board connected
* to an Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n-rev2-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};

15
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.2.0 connected to sub board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n-rev2.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N (Rev.2.0) with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
"renesas,r8a774b1";
};

41
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts Normal file
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@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.2.0 main board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1.dtsi"
#include "hihope-rev2.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N main board (Rev.2.0) based on r8a774b1";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&sdhi3 {
mmc-hs400-1_8v;
};

6
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts
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@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N main board
* Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
*
* Copyright (C) 2019 Renesas Electronics Corp.
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1.dtsi"
#include "hihope-common.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";

2
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
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@ -10,6 +10,8 @@
#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
#include <dt-bindings/power/r8a774b1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4
/ {
compatible = "renesas,r8a774b1";
#address-cells = <2>;

89
arch/arm64/boot/dts/renesas/r8a77961.dtsi
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@ -883,6 +883,95 @@
dma-channels = <16>;
};
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_hc: iommu@e6570000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ir: iommu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A77961_PD_A3IR>;
#iommu-cells = <1>;
};
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mp: iommu@ec670000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv0: iommu@fd800000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv1: iommu@fd950000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vc0: iommu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A77961_PD_A3VC>;
#iommu-cells = <1>;
};
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a77961";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77961",
"renesas,etheravb-rcar-gen3";