forked from Minki/linux
Improve SPI support for Ingenic SoCs.
Merge series from 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>: 1.Add support for using GPIOs as chip select lines on Ingenic SoCs. 2.Add support for probing the spi-ingenic driver on the JZ4775 SoC, the X1000 SoC, and the X2000 SoC. 3.Modify annotation texts to be more in line with the current state.
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commit
9ee448f943
@ -18,7 +18,10 @@ properties:
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oneOf:
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- enum:
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- ingenic,jz4750-spi
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- ingenic,jz4775-spi
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- ingenic,jz4780-spi
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- ingenic,x1000-spi
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- ingenic,x2000-spi
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- items:
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- enum:
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- ingenic,jz4760-spi
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@ -419,10 +419,10 @@ config SPI_IMX
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This enables support for the Freescale i.MX SPI controllers.
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config SPI_INGENIC
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tristate "Ingenic JZ47xx SoCs SPI controller"
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tristate "Ingenic SoCs SPI controller"
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depends on MACH_INGENIC || COMPILE_TEST
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help
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This enables support for the Ingenic JZ47xx SoCs SPI controller.
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This enables support for the Ingenic SoCs SPI controller.
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To compile this driver as a module, choose M here: the module
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will be called spi-ingenic.
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@ -1,8 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SPI bus driver for the Ingenic JZ47xx SoCs
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* SPI bus driver for the Ingenic SoCs
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* Copyright (c) 2017-2021 Artur Rojek <contact@artur-rojek.eu>
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* Copyright (c) 2017-2021 Paul Cercueil <paul@crapouillou.net>
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* Copyright (c) 2022 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#include <linux/clk.h>
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@ -52,6 +53,9 @@ struct jz_soc_info {
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u32 bits_per_word_mask;
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struct reg_field flen_field;
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bool has_trendian;
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unsigned int max_speed_hz;
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unsigned int max_native_cs;
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};
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struct ingenic_spi {
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@ -380,7 +384,7 @@ static int spi_ingenic_probe(struct platform_device *pdev)
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struct spi_controller *ctlr;
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struct ingenic_spi *priv;
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void __iomem *base;
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int ret;
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int num_cs, ret;
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pdata = of_device_get_match_data(dev);
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if (!pdata) {
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@ -416,6 +420,9 @@ static int spi_ingenic_probe(struct platform_device *pdev)
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if (IS_ERR(priv->flen_field))
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return PTR_ERR(priv->flen_field);
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if (device_property_read_u32(dev, "num-cs", &num_cs))
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num_cs = pdata->max_native_cs;
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platform_set_drvdata(pdev, ctlr);
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ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware;
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@ -428,8 +435,10 @@ static int spi_ingenic_probe(struct platform_device *pdev)
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ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE;
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ctlr->bits_per_word_mask = pdata->bits_per_word_mask;
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ctlr->min_speed_hz = 7200;
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ctlr->max_speed_hz = 54000000;
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ctlr->num_chipselect = 2;
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ctlr->max_speed_hz = pdata->max_speed_hz;
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ctlr->use_gpio_descriptors = true;
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ctlr->max_native_cs = pdata->max_native_cs;
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ctlr->num_chipselect = num_cs;
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ctlr->dev.of_node = pdev->dev.of_node;
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if (spi_ingenic_request_dma(ctlr, dev))
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@ -452,17 +461,44 @@ static const struct jz_soc_info jz4750_soc_info = {
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.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 17),
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.flen_field = REG_FIELD(REG_SSICR1, 4, 7),
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.has_trendian = false,
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.max_speed_hz = 54000000,
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.max_native_cs = 2,
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};
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static const struct jz_soc_info jz4780_soc_info = {
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.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
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.flen_field = REG_FIELD(REG_SSICR1, 3, 7),
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.has_trendian = true,
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.max_speed_hz = 54000000,
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.max_native_cs = 2,
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};
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static const struct jz_soc_info x1000_soc_info = {
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.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
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.flen_field = REG_FIELD(REG_SSICR1, 3, 7),
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.has_trendian = true,
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.max_speed_hz = 50000000,
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.max_native_cs = 2,
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};
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static const struct jz_soc_info x2000_soc_info = {
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.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
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.flen_field = REG_FIELD(REG_SSICR1, 3, 7),
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.has_trendian = true,
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.max_speed_hz = 50000000,
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.max_native_cs = 1,
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};
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static const struct of_device_id spi_ingenic_of_match[] = {
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{ .compatible = "ingenic,jz4750-spi", .data = &jz4750_soc_info },
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{ .compatible = "ingenic,jz4775-spi", .data = &jz4780_soc_info },
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{ .compatible = "ingenic,jz4780-spi", .data = &jz4780_soc_info },
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{ .compatible = "ingenic,x1000-spi", .data = &x1000_soc_info },
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{ .compatible = "ingenic,x2000-spi", .data = &x2000_soc_info },
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{}
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};
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MODULE_DEVICE_TABLE(of, spi_ingenic_of_match);
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@ -476,7 +512,8 @@ static struct platform_driver spi_ingenic_driver = {
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};
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module_platform_driver(spi_ingenic_driver);
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MODULE_DESCRIPTION("SPI bus driver for the Ingenic JZ47xx SoCs");
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MODULE_DESCRIPTION("SPI bus driver for the Ingenic SoCs");
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MODULE_AUTHOR("Artur Rojek <contact@artur-rojek.eu>");
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MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
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MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
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MODULE_LICENSE("GPL");
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