ice: Add support for dynamic interrupt moderation
Currently there is no support for dynamic interrupt moderation. This patch adds some initial code to support this. The following changes were made: 1. Currently we are using multiple members to store the interrupt granularity (itr_gran_25/50/100/200). This is not necessary because we can query the device to determine what the interrupt granularity should be set to, done by a new function ice_get_itr_intrl_gran. 2. Added intrl to ice_q_vector structure to support interrupt rate limiting. 3. Added the function ice_intrl_usecs_to_reg for converting to a value in usecs that the device understands. 4. Added call to write to the GLINT_RATE register. Disable intrl by default for now. 5. Changed rx/tx_itr_setting to itr_setting because having both seems redundant because a ring is either Tx or Rx. 6. Initialize itr_setting for both Tx/Rx rings in ice_vsi_alloc_rings() Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
committed by
Jeff Kirsher
parent
ca4929b6df
commit
9e4ab4c29a
@@ -1139,6 +1139,7 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi)
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ring->vsi = vsi;
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ring->dev = &pf->pdev->dev;
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ring->count = vsi->num_desc;
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ring->itr_setting = ICE_DFLT_TX_ITR;
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vsi->tx_rings[i] = ring;
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}
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@@ -1158,6 +1159,7 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi)
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ring->netdev = vsi->netdev;
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ring->dev = &pf->pdev->dev;
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ring->count = vsi->num_desc;
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ring->itr_setting = ICE_DFLT_RX_ITR;
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vsi->rx_rings[i] = ring;
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}
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@@ -1595,6 +1597,23 @@ err_cfg_txqs:
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return err;
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}
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/**
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* ice_intrl_usec_to_reg - convert interrupt rate limit to register value
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* @intrl: interrupt rate limit in usecs
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* @gran: interrupt rate limit granularity in usecs
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*
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* This function converts a decimal interrupt rate limit in usecs to the format
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* expected by firmware.
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*/
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static u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran)
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{
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u32 val = intrl / gran;
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if (val)
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return val | GLINT_RATE_INTRL_ENA_M;
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return 0;
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}
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/**
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* ice_vsi_cfg_msix - MSIX mode Interrupt Config in the HW
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* @vsi: the VSI being configured
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@@ -1611,23 +1630,27 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)
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for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
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struct ice_q_vector *q_vector = vsi->q_vectors[i];
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itr_gran = hw->itr_gran_200;
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itr_gran = hw->itr_gran;
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q_vector->intrl = ICE_DFLT_INTRL;
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if (q_vector->num_ring_rx) {
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q_vector->rx.itr =
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ITR_TO_REG(vsi->rx_rings[rxq]->rx_itr_setting,
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ITR_TO_REG(vsi->rx_rings[rxq]->itr_setting,
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itr_gran);
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q_vector->rx.latency_range = ICE_LOW_LATENCY;
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}
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if (q_vector->num_ring_tx) {
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q_vector->tx.itr =
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ITR_TO_REG(vsi->tx_rings[txq]->tx_itr_setting,
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ITR_TO_REG(vsi->tx_rings[txq]->itr_setting,
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itr_gran);
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q_vector->tx.latency_range = ICE_LOW_LATENCY;
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}
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wr32(hw, GLINT_ITR(ICE_RX_ITR, vector), q_vector->rx.itr);
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wr32(hw, GLINT_ITR(ICE_TX_ITR, vector), q_vector->tx.itr);
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wr32(hw, GLINT_RATE(vector),
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ice_intrl_usec_to_reg(q_vector->intrl, hw->intrl_gran));
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/* Both Transmit Queue Interrupt Cause Control register
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* and Receive Queue Interrupt Cause control register
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