From b71590efb2cd91c44fdec6424b7db7849194141c Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sun, 2 Aug 2020 11:49:09 +0300 Subject: [PATCH 01/46] habanalabs: increase length of ASIC name Future ASIC names are longer than 15 chars so increase the variable length to 32 chars. Signed-off-by: Oded Gabbay Reviewed-by: Tomer Tayar --- drivers/misc/habanalabs/common/habanalabs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index edbd627b29d2..278c45a0b255 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -1513,7 +1513,7 @@ struct hl_device { struct device *dev_ctrl; struct delayed_work work_freq; struct delayed_work work_heartbeat; - char asic_name[16]; + char asic_name[32]; enum hl_asic_type asic_type; struct hl_cq *completion_queue; struct workqueue_struct **cq_wq; From a98d73c7fae486f7fea83bdec8599d4fccb6807d Mon Sep 17 00:00:00 2001 From: Ofir Bitton Date: Wed, 15 Jul 2020 08:52:39 +0300 Subject: [PATCH 02/46] habanalabs: Replace dma-fence mechanism with completions habanalabs driver uses dma-fence mechanism for synchronization. dma-fence mechanism was designed solely for GPUs, hence we purpose a simpler mechanism based on completions to replace current dma-fence objects. Signed-off-by: Ofir Bitton Cc: Greg Kroah-Hartman Cc: Daniel Vetter Reviewed-by: Oded Gabbay Reviewed-by: Daniel Vetter Signed-off-by: Oded Gabbay --- .../habanalabs/common/command_submission.c | 95 +++++++++---------- drivers/misc/habanalabs/common/context.c | 13 +-- drivers/misc/habanalabs/common/habanalabs.h | 30 ++++-- drivers/misc/habanalabs/common/hw_queue.c | 2 +- 4 files changed, 77 insertions(+), 63 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_submission.c b/drivers/misc/habanalabs/common/command_submission.c index 2e3fcbc794db..00c1ff2e953d 100644 --- a/drivers/misc/habanalabs/common/command_submission.c +++ b/drivers/misc/habanalabs/common/command_submission.c @@ -38,26 +38,10 @@ void hl_sob_reset_error(struct kref *ref) hw_sob->q_idx, hw_sob->sob_id); } -static const char *hl_fence_get_driver_name(struct dma_fence *fence) -{ - return "HabanaLabs"; -} - -static const char *hl_fence_get_timeline_name(struct dma_fence *fence) -{ - struct hl_cs_compl *hl_cs_compl = - container_of(fence, struct hl_cs_compl, base_fence); - - return dev_name(hl_cs_compl->hdev->dev); -} - -static bool hl_fence_enable_signaling(struct dma_fence *fence) -{ - return true; -} - -static void hl_fence_release(struct dma_fence *fence) +static void hl_fence_release(struct kref *kref) { + struct hl_fence *fence = + container_of(kref, struct hl_fence, refcount); struct hl_cs_compl *hl_cs_cmpl = container_of(fence, struct hl_cs_compl, base_fence); struct hl_device *hdev = hl_cs_cmpl->hdev; @@ -99,15 +83,27 @@ static void hl_fence_release(struct dma_fence *fence) } free: - kfree_rcu(hl_cs_cmpl, base_fence.rcu); + kfree(hl_cs_cmpl); } -static const struct dma_fence_ops hl_fence_ops = { - .get_driver_name = hl_fence_get_driver_name, - .get_timeline_name = hl_fence_get_timeline_name, - .enable_signaling = hl_fence_enable_signaling, - .release = hl_fence_release -}; +void hl_fence_put(struct hl_fence *fence) +{ + if (fence) + kref_put(&fence->refcount, hl_fence_release); +} + +void hl_fence_get(struct hl_fence *fence) +{ + if (fence) + kref_get(&fence->refcount); +} + +static void hl_fence_init(struct hl_fence *fence) +{ + kref_init(&fence->refcount); + fence->error = 0; + init_completion(&fence->completion); +} static void cs_get(struct hl_cs *cs) { @@ -336,7 +332,7 @@ static void cs_do_release(struct kref *ref) * In case the wait for signal CS was submitted, the put occurs * in init_signal_wait_cs() right before hanging on the PQ. */ - dma_fence_put(cs->signal_fence); + hl_fence_put(cs->signal_fence); } /* @@ -348,19 +344,18 @@ static void cs_do_release(struct kref *ref) hl_ctx_put(cs->ctx); /* We need to mark an error for not submitted because in that case - * the dma fence release flow is different. Mainly, we don't need + * the hl fence release flow is different. Mainly, we don't need * to handle hw_sob for signal/wait */ if (cs->timedout) - dma_fence_set_error(cs->fence, -ETIMEDOUT); + cs->fence->error = -ETIMEDOUT; else if (cs->aborted) - dma_fence_set_error(cs->fence, -EIO); + cs->fence->error = -EIO; else if (!cs->submitted) - dma_fence_set_error(cs->fence, -EBUSY); - - dma_fence_signal(cs->fence); - dma_fence_put(cs->fence); + cs->fence->error = -EBUSY; + complete_all(&cs->fence->completion); + hl_fence_put(cs->fence); cs_counters_aggregate(hdev, cs->ctx); kfree(cs->jobs_in_queue_cnt); @@ -401,7 +396,7 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, enum hl_cs_type cs_type, struct hl_cs **cs_new) { struct hl_cs_compl *cs_cmpl; - struct dma_fence *other = NULL; + struct hl_fence *other = NULL; struct hl_cs *cs; int rc; @@ -434,7 +429,8 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, cs_cmpl->cs_seq = ctx->cs_sequence; other = ctx->cs_pending[cs_cmpl->cs_seq & (hdev->asic_prop.max_pending_cs - 1)]; - if ((other) && (!dma_fence_is_signaled(other))) { + + if (other && !completion_done(&other->completion)) { dev_dbg(hdev->dev, "Rejecting CS because of too many in-flights CS\n"); rc = -EAGAIN; @@ -448,8 +444,8 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, goto free_fence; } - dma_fence_init(&cs_cmpl->base_fence, &hl_fence_ops, &cs_cmpl->lock, - ctx->asid, ctx->cs_sequence); + /* init hl_fence */ + hl_fence_init(&cs_cmpl->base_fence); cs->sequence = cs_cmpl->cs_seq; @@ -458,9 +454,9 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, &cs_cmpl->base_fence; ctx->cs_sequence++; - dma_fence_get(&cs_cmpl->base_fence); + hl_fence_get(&cs_cmpl->base_fence); - dma_fence_put(other); + hl_fence_put(other); spin_unlock(&ctx->cs_lock); @@ -773,7 +769,7 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, struct hl_ctx *ctx = hpriv->ctx; struct hl_cs_chunk *cs_chunk_array, *chunk; struct hw_queue_properties *hw_queue_prop; - struct dma_fence *sig_fence = NULL; + struct hl_fence *sig_fence = NULL; struct hl_cs_job *job; struct hl_cs *cs; struct hl_cb *cb; @@ -883,14 +879,14 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, dev_err(hdev->dev, "CS seq 0x%llx is not of a signal CS\n", signal_seq); - dma_fence_put(sig_fence); + hl_fence_put(sig_fence); rc = -EINVAL; goto free_signal_seq_array; } - if (dma_fence_is_signaled(sig_fence)) { + if (completion_done(&sig_fence->completion)) { /* signal CS already finished */ - dma_fence_put(sig_fence); + hl_fence_put(sig_fence); rc = 0; goto free_signal_seq_array; } @@ -902,7 +898,7 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, rc = allocate_cs(hdev, ctx, cs_type, &cs); if (rc) { if (cs_type == CS_TYPE_WAIT) - dma_fence_put(sig_fence); + hl_fence_put(sig_fence); hl_ctx_put(ctx); goto free_signal_seq_array; } @@ -1162,7 +1158,7 @@ out: static long _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq) { - struct dma_fence *fence; + struct hl_fence *fence; unsigned long timeout; long rc; @@ -1181,12 +1177,15 @@ static long _hl_cs_wait_ioctl(struct hl_device *hdev, "Can't wait on CS %llu because current CS is at seq %llu\n", seq, ctx->cs_sequence); } else if (fence) { - rc = dma_fence_wait_timeout(fence, true, timeout); + rc = wait_for_completion_interruptible_timeout( + &fence->completion, timeout); + if (fence->error == -ETIMEDOUT) rc = -ETIMEDOUT; else if (fence->error == -EIO) rc = -EIO; - dma_fence_put(fence); + + hl_fence_put(fence); } else { dev_dbg(hdev->dev, "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", diff --git a/drivers/misc/habanalabs/common/context.c b/drivers/misc/habanalabs/common/context.c index 3e375958e73b..b168a9fce817 100644 --- a/drivers/misc/habanalabs/common/context.c +++ b/drivers/misc/habanalabs/common/context.c @@ -23,7 +23,7 @@ static void hl_ctx_fini(struct hl_ctx *ctx) */ for (i = 0 ; i < hdev->asic_prop.max_pending_cs ; i++) - dma_fence_put(ctx->cs_pending[i]); + hl_fence_put(ctx->cs_pending[i]); kfree(ctx->cs_pending); @@ -128,7 +128,7 @@ int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx) atomic_set(&ctx->thread_ctx_switch_token, 1); ctx->thread_ctx_switch_wait_token = 0; ctx->cs_pending = kcalloc(hdev->asic_prop.max_pending_cs, - sizeof(struct dma_fence *), + sizeof(struct hl_fence *), GFP_KERNEL); if (!ctx->cs_pending) return -ENOMEM; @@ -184,10 +184,10 @@ int hl_ctx_put(struct hl_ctx *ctx) return kref_put(&ctx->refcount, hl_ctx_do_release); } -struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq) +struct hl_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq) { struct asic_fixed_properties *asic_prop = &ctx->hdev->asic_prop; - struct dma_fence *fence; + struct hl_fence *fence; spin_lock(&ctx->cs_lock); @@ -201,8 +201,9 @@ struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq) return NULL; } - fence = dma_fence_get( - ctx->cs_pending[seq & (asic_prop->max_pending_cs - 1)]); + fence = ctx->cs_pending[seq & (asic_prop->max_pending_cs - 1)]; + hl_fence_get(fence); + spin_unlock(&ctx->cs_lock); return fence; diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 278c45a0b255..f97eebc64979 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -342,9 +341,22 @@ struct asic_fixed_properties { u8 completion_queues_count; }; +/** + * struct hl_fence - software synchronization primitive + * @completion: fence is implemented using completion + * @refcount: refcount for this fence + * @error: mark this fence with error + * + */ +struct hl_fence { + struct completion completion; + struct kref refcount; + int error; +}; + /** * struct hl_cs_compl - command submission completion object. - * @base_fence: kernel fence object. + * @base_fence: hl fence object. * @lock: spinlock to protect fence. * @hdev: habanalabs device structure. * @hw_sob: the H/W SOB used in this signal/wait CS. @@ -353,7 +365,7 @@ struct asic_fixed_properties { * @sob_val: the SOB value that is used in this signal/wait CS. */ struct hl_cs_compl { - struct dma_fence base_fence; + struct hl_fence base_fence; spinlock_t lock; struct hl_device *hdev; struct hl_hw_sob *hw_sob; @@ -800,7 +812,7 @@ struct hl_va_range { * @hdev: pointer to the device structure. * @refcount: reference counter for the context. Context is released only when * this hits 0l. It is incremented on CS and CS_WAIT. - * @cs_pending: array of DMA fence objects representing pending CS. + * @cs_pending: array of hl fence objects representing pending CS. * @host_va_range: holds available virtual addresses for host mappings. * @host_huge_va_range: holds available virtual addresses for host mappings * with huge pages. @@ -832,7 +844,7 @@ struct hl_ctx { struct hl_fpriv *hpriv; struct hl_device *hdev; struct kref refcount; - struct dma_fence **cs_pending; + struct hl_fence **cs_pending; struct hl_va_range *host_va_range; struct hl_va_range *host_huge_va_range; struct hl_va_range *dram_va_range; @@ -919,8 +931,8 @@ struct hl_cs { struct list_head job_list; spinlock_t job_lock; struct kref refcount; - struct dma_fence *fence; - struct dma_fence *signal_fence; + struct hl_fence *fence; + struct hl_fence *signal_fence; struct work_struct finish_work; struct delayed_work work_tdr; struct list_head mirror_node; @@ -1739,7 +1751,7 @@ int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx); void hl_ctx_do_release(struct kref *ref); void hl_ctx_get(struct hl_device *hdev, struct hl_ctx *ctx); int hl_ctx_put(struct hl_ctx *ctx); -struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq); +struct hl_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq); void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr); void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr); @@ -1781,6 +1793,8 @@ void hl_cs_rollback_all(struct hl_device *hdev); struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, enum hl_queue_type queue_type, bool is_kernel_allocated_cb); void hl_sob_reset_error(struct kref *ref); +void hl_fence_put(struct hl_fence *fence); +void hl_fence_get(struct hl_fence *fence); void goya_set_asic_funcs(struct hl_device *hdev); void gaudi_set_asic_funcs(struct hl_device *hdev); diff --git a/drivers/misc/habanalabs/common/hw_queue.c b/drivers/misc/habanalabs/common/hw_queue.c index 287681646071..65b9aa69a83e 100644 --- a/drivers/misc/habanalabs/common/hw_queue.c +++ b/drivers/misc/habanalabs/common/hw_queue.c @@ -474,7 +474,7 @@ static void init_signal_wait_cs(struct hl_cs *cs) * wait CS was submitted. */ mb(); - dma_fence_put(cs->signal_fence); + hl_fence_put(cs->signal_fence); cs->signal_fence = NULL; } } From 0a068adde505a90ece23caaf19b77567e1d18298 Mon Sep 17 00:00:00 2001 From: Ofir Bitton Date: Tue, 21 Jul 2020 10:49:51 +0300 Subject: [PATCH 03/46] habanalabs: add information about PCIe controller Update firmware header with new API for getting pcie info such as tx/rx throughput and replay counter. These counters are needed by customers for monitor and maintenance of multiple devices. Add new opcodes to the INFO ioctl to retrieve these counters. Signed-off-by: Ofir Bitton Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/firmware_if.c | 48 +++++++++++++++++++ drivers/misc/habanalabs/common/habanalabs.h | 4 ++ .../misc/habanalabs/common/habanalabs_ioctl.c | 41 ++++++++++++++++ drivers/misc/habanalabs/gaudi/gaudi.c | 4 ++ drivers/misc/habanalabs/goya/goya.c | 4 ++ .../misc/habanalabs/include/common/armcp_if.h | 10 ++++ include/uapi/misc/habanalabs.h | 27 +++++++++++ 7 files changed, 138 insertions(+) diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c index f52bc690dfc5..61f5edc96e16 100644 --- a/drivers/misc/habanalabs/common/firmware_if.c +++ b/drivers/misc/habanalabs/common/firmware_if.c @@ -363,6 +363,54 @@ out: return rc; } +int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, + struct hl_info_pci_counters *counters) +{ + struct armcp_packet pkt = {}; + long result; + int rc; + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_PCIE_THROUGHPUT_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + + /* Fetch PCI rx counter */ + pkt.index = cpu_to_le32(armcp_pcie_throughput_rx); + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_ARMCP_INFO_TIMEOUT_USEC, &result); + if (rc) { + dev_err(hdev->dev, + "Failed to handle ArmCP PCI info pkt, error %d\n", rc); + return rc; + } + counters->rx_throughput = result; + + /* Fetch PCI tx counter */ + pkt.index = cpu_to_le32(armcp_pcie_throughput_tx); + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_ARMCP_INFO_TIMEOUT_USEC, &result); + if (rc) { + dev_err(hdev->dev, + "Failed to handle ArmCP PCI info pkt, error %d\n", rc); + return rc; + } + counters->tx_throughput = result; + + /* Fetch PCI replay counter */ + pkt.ctl = cpu_to_le32(ARMCP_PACKET_PCIE_REPLAY_CNT_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_ARMCP_INFO_TIMEOUT_USEC, &result); + if (rc) { + dev_err(hdev->dev, + "Failed to handle ArmCP PCI info pkt, error %d\n", rc); + return rc; + } + counters->replay_cnt = (u32) result; + + return rc; +} + static void fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg) { u32 err_val; diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index f97eebc64979..2c9fcb513215 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -1483,6 +1483,7 @@ struct hl_device_idle_busy_ts { * @soft_reset_cnt: number of soft reset since the driver was loaded. * @hard_reset_cnt: number of hard reset since the driver was loaded. * @idle_busy_ts_idx: index of current entry in idle_busy_ts_arr + * @clk_throttling_reason: bitmask represents the current clk throttling reasons * @id: device minor. * @id_control: minor of the control device * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit @@ -1587,6 +1588,7 @@ struct hl_device { u32 soft_reset_cnt; u32 hard_reset_cnt; u32 idle_busy_ts_idx; + u32 clk_throttling_reason; u16 id; u16 id_control; u16 cpu_pci_msb_addr; @@ -1841,6 +1843,8 @@ void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, int hl_fw_send_heartbeat(struct hl_device *hdev); int hl_fw_armcp_info_get(struct hl_device *hdev); int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size); +int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, + struct hl_info_pci_counters *counters); int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, u32 boot_err0_reg, bool skip_bmc, diff --git a/drivers/misc/habanalabs/common/habanalabs_ioctl.c b/drivers/misc/habanalabs/common/habanalabs_ioctl.c index 5af1c03da473..4d838b1a3bbe 100644 --- a/drivers/misc/habanalabs/common/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/common/habanalabs_ioctl.c @@ -276,6 +276,41 @@ static int time_sync_info(struct hl_device *hdev, struct hl_info_args *args) min((size_t) max_size, sizeof(time_sync))) ? -EFAULT : 0; } +static int pci_counters_info(struct hl_fpriv *hpriv, struct hl_info_args *args) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_info_pci_counters pci_counters = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + int rc; + + if ((!max_size) || (!out)) + return -EINVAL; + + rc = hl_fw_armcp_pci_counters_get(hdev, &pci_counters); + if (rc) + return rc; + + return copy_to_user(out, &pci_counters, + min((size_t) max_size, sizeof(pci_counters))) ? -EFAULT : 0; +} + +static int clk_throttle_info(struct hl_fpriv *hpriv, struct hl_info_args *args) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_info_clk_throttle clk_throttle = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + + if ((!max_size) || (!out)) + return -EINVAL; + + clk_throttle.clk_throttling_reason = hdev->clk_throttling_reason; + + return copy_to_user(out, &clk_throttle, + min((size_t) max_size, sizeof(clk_throttle))) ? -EFAULT : 0; +} + static int cs_counters_info(struct hl_fpriv *hpriv, struct hl_info_args *args) { struct hl_device *hdev = hpriv->hdev; @@ -360,6 +395,12 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, case HL_INFO_CS_COUNTERS: return cs_counters_info(hpriv, args); + case HL_INFO_PCI_COUNTERS: + return pci_counters_info(hpriv, args); + + case HL_INFO_CLK_THROTTLE_REASON: + return clk_throttle_info(hpriv, args); + default: dev_err(dev, "Invalid request %d\n", args->op); rc = -ENOTTY; diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 4009b7df4caf..adb5c5594ac1 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -5653,21 +5653,25 @@ static void gaudi_print_clk_change_info(struct hl_device *hdev, { switch (event_type) { case GAUDI_EVENT_FIX_POWER_ENV_S: + hdev->clk_throttling_reason |= HL_CLK_THROTTLE_POWER; dev_info_ratelimited(hdev->dev, "Clock throttling due to power consumption\n"); break; case GAUDI_EVENT_FIX_POWER_ENV_E: + hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_POWER; dev_info_ratelimited(hdev->dev, "Power envelop is safe, back to optimal clock\n"); break; case GAUDI_EVENT_FIX_THERMAL_ENV_S: + hdev->clk_throttling_reason |= HL_CLK_THROTTLE_THERMAL; dev_info_ratelimited(hdev->dev, "Clock throttling due to overheating\n"); break; case GAUDI_EVENT_FIX_THERMAL_ENV_E: + hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_THERMAL; dev_info_ratelimited(hdev->dev, "Thermal envelop is safe, back to optimal clock\n"); break; diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 33cd2ae653d2..954f2c022d33 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -4580,18 +4580,22 @@ static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type) { switch (event_type) { case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S: + hdev->clk_throttling_reason |= HL_CLK_THROTTLE_POWER; dev_info_ratelimited(hdev->dev, "Clock throttling due to power consumption\n"); break; case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E: + hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_POWER; dev_info_ratelimited(hdev->dev, "Power envelop is safe, back to optimal clock\n"); break; case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S: + hdev->clk_throttling_reason |= HL_CLK_THROTTLE_THERMAL; dev_info_ratelimited(hdev->dev, "Clock throttling due to overheating\n"); break; case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E: + hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_THERMAL; dev_info_ratelimited(hdev->dev, "Thermal envelop is safe, back to optimal clock\n"); break; diff --git a/drivers/misc/habanalabs/include/common/armcp_if.h b/drivers/misc/habanalabs/include/common/armcp_if.h index 07f9972db28d..1403c937253c 100644 --- a/drivers/misc/habanalabs/include/common/armcp_if.h +++ b/drivers/misc/habanalabs/include/common/armcp_if.h @@ -243,6 +243,8 @@ enum armcp_packet_id { ARMCP_PACKET_TEMPERATURE_SET, /* sysfs */ ARMCP_PACKET_VOLTAGE_SET, /* sysfs */ ARMCP_PACKET_CURRENT_SET, /* sysfs */ + ARMCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ + ARMCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ }; #define ARMCP_PACKET_FENCE_VAL 0xFE8CE7A5 @@ -277,6 +279,9 @@ struct armcp_packet { __u8 pad; /* unused */ }; + /* For any general request */ + __le32 index; + /* For frequency get/set */ __le32 pll_index; @@ -344,6 +349,11 @@ enum armcp_pwm_attributes { armcp_pwm_enable }; +enum armcp_pcie_throughput_attributes { + armcp_pcie_throughput_tx, + armcp_pcie_throughput_rx +}; + /* Event Queue Packets */ struct eq_generic_event { diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index d5c4f983b7a8..ee13b919db35 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -264,6 +264,8 @@ enum hl_device_status { * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time * for synchronization. * HL_INFO_CS_COUNTERS - Retrieve command submission counters + * HL_INFO_PCI_COUNTERS - Retrieve PCI counters + * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -276,6 +278,8 @@ enum hl_device_status { #define HL_INFO_RESET_COUNT 9 #define HL_INFO_TIME_SYNC 10 #define HL_INFO_CS_COUNTERS 11 +#define HL_INFO_PCI_COUNTERS 12 +#define HL_INFO_CLK_THROTTLE_REASON 13 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -340,6 +344,29 @@ struct hl_info_time_sync { __u64 host_time; }; +/** + * struct hl_info_pci_counters - pci counters + * @rx_throughput: PCI rx throughput KBps + * @tx_throughput: PCI tx throughput KBps + * @replay_cnt: PCI replay counter + */ +struct hl_info_pci_counters { + __u64 rx_throughput; + __u64 tx_throughput; + __u64 replay_cnt; +}; + +#define HL_CLK_THROTTLE_POWER 0x1 +#define HL_CLK_THROTTLE_THERMAL 0x2 + +/** + * struct hl_info_clk_throttle - clock throttling reason + * @clk_throttling_reason: each bit represents a clk throttling reason + */ +struct hl_info_clk_throttle { + __u32 clk_throttling_reason; +}; + /** * struct hl_info_cs_counters - command submission counters * @out_of_mem_drop_cnt: dropped due to memory allocation issue From 843839bec3a304f8313d6ae554f618a91e52731a Mon Sep 17 00:00:00 2001 From: Ofir Bitton Date: Sun, 19 Jul 2020 11:08:09 +0300 Subject: [PATCH 04/46] habanalabs: expose sync manager resources allocation in INFO IOCTL Although the driver defines the first user-available sync manager object and monitor in habanalabs.h, we would like to also expose this information via the INFO IOCTL so the runtime can get this information dynamically. This is because in future ASICs we won't need to define it statically. Signed-off-by: Ofir Bitton Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/habanalabs.h | 6 ++++ .../misc/habanalabs/common/habanalabs_ioctl.c | 30 ++++++++++++++++++- drivers/misc/habanalabs/gaudi/gaudi.c | 7 +++++ include/uapi/misc/habanalabs.h | 23 ++++++++++++++ 4 files changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 2c9fcb513215..caced12f278f 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -65,6 +65,8 @@ #define HL_PCI_NUM_BARS 6 +#define HL_MAX_DCORES 4 + /** * struct pgt_info - MMU hop page info. * @node: hash linked-list node for the pgts shadow hash of pgts. @@ -291,6 +293,8 @@ struct hl_mmu_properties { * @max_queues: maximum amount of queues in the system * @sync_stream_first_sob: first sync object available for sync stream use * @sync_stream_first_mon: first monitor available for sync stream use + * @first_available_user_sob: first sob available for the user + * @first_available_user_mon: first monitor available for the user * @tpc_enabled_mask: which TPCs are enabled. * @completion_queues_count: number of completion queues. */ @@ -337,6 +341,8 @@ struct asic_fixed_properties { u32 max_queues; u16 sync_stream_first_sob; u16 sync_stream_first_mon; + u16 first_available_user_sob[HL_MAX_DCORES]; + u16 first_available_user_mon[HL_MAX_DCORES]; u8 tpc_enabled_mask; u8 completion_queues_count; }; diff --git a/drivers/misc/habanalabs/common/habanalabs_ioctl.c b/drivers/misc/habanalabs/common/habanalabs_ioctl.c index 4d838b1a3bbe..fe6c5534d378 100644 --- a/drivers/misc/habanalabs/common/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/common/habanalabs_ioctl.c @@ -8,6 +8,7 @@ #include #include "habanalabs.h" +#include #include #include #include @@ -314,7 +315,7 @@ static int clk_throttle_info(struct hl_fpriv *hpriv, struct hl_info_args *args) static int cs_counters_info(struct hl_fpriv *hpriv, struct hl_info_args *args) { struct hl_device *hdev = hpriv->hdev; - struct hl_info_cs_counters cs_counters = {0}; + struct hl_info_cs_counters cs_counters = { {0} }; u32 max_size = args->return_size; void __user *out = (void __user *) (uintptr_t) args->return_pointer; @@ -332,6 +333,30 @@ static int cs_counters_info(struct hl_fpriv *hpriv, struct hl_info_args *args) min((size_t) max_size, sizeof(cs_counters))) ? -EFAULT : 0; } +static int sync_manager_info(struct hl_fpriv *hpriv, struct hl_info_args *args) +{ + struct hl_device *hdev = hpriv->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_info_sync_manager sm_info = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + + if ((!max_size) || (!out)) + return -EINVAL; + + if (args->dcore_id >= HL_MAX_DCORES) + return -EINVAL; + + sm_info.first_available_sync_object = + prop->first_available_user_sob[args->dcore_id]; + sm_info.first_available_monitor = + prop->first_available_user_mon[args->dcore_id]; + + + return copy_to_user(out, &sm_info, min_t(size_t, (size_t) max_size, + sizeof(sm_info))) ? -EFAULT : 0; +} + static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, struct device *dev) { @@ -401,6 +426,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, case HL_INFO_CLK_THROTTLE_REASON: return clk_throttle_info(hpriv, args); + case HL_INFO_SYNC_MANAGER: + return sync_manager_info(hpriv, args); + default: dev_err(dev, "Invalid request %d\n", args->op); rc = -ENOTTY; diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index adb5c5594ac1..45ba3a5f5b14 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -367,6 +367,7 @@ static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid); static int gaudi_get_fixed_properties(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 num_sync_stream_queues = 0; int i; prop->max_queues = GAUDI_QUEUE_ID_SIZE; @@ -383,6 +384,7 @@ static int gaudi_get_fixed_properties(struct hl_device *hdev) prop->hw_queues_props[i].driver_only = 0; prop->hw_queues_props[i].requires_kernel_cb = 1; prop->hw_queues_props[i].supports_sync_stream = 1; + num_sync_stream_queues++; } else if (gaudi_queue_type[i] == QUEUE_TYPE_CPU) { prop->hw_queues_props[i].type = QUEUE_TYPE_CPU; prop->hw_queues_props[i].driver_only = 1; @@ -469,6 +471,11 @@ static int gaudi_get_fixed_properties(struct hl_device *hdev) prop->max_pending_cs = GAUDI_MAX_PENDING_CS; + prop->first_available_user_sob[HL_GAUDI_WS_DCORE] = + num_sync_stream_queues * HL_RSVD_SOBS; + prop->first_available_user_mon[HL_GAUDI_WS_DCORE] = + num_sync_stream_queues * HL_RSVD_MONS; + return 0; } diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index ee13b919db35..ca6dc1fc250e 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -266,6 +266,7 @@ enum hl_device_status { * HL_INFO_CS_COUNTERS - Retrieve command submission counters * HL_INFO_PCI_COUNTERS - Retrieve PCI counters * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason + * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -280,6 +281,7 @@ enum hl_device_status { #define HL_INFO_CS_COUNTERS 11 #define HL_INFO_PCI_COUNTERS 12 #define HL_INFO_CLK_THROTTLE_REASON 13 +#define HL_INFO_SYNC_MANAGER 14 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -367,6 +369,16 @@ struct hl_info_clk_throttle { __u32 clk_throttling_reason; }; +/** + * struct hl_info_sync_manager - sync manager information + * @first_available_sync_object: first available sob + * @first_available_monitor: first available monitor + */ +struct hl_info_sync_manager { + __u32 first_available_sync_object; + __u32 first_available_monitor; +}; + /** * struct hl_info_cs_counters - command submission counters * @out_of_mem_drop_cnt: dropped due to memory allocation issue @@ -386,6 +398,13 @@ struct hl_info_cs_counters { struct hl_cs_counters ctx_cs_counters; }; +enum gaudi_dcores { + HL_GAUDI_WS_DCORE, + HL_GAUDI_WN_DCORE, + HL_GAUDI_EN_DCORE, + HL_GAUDI_ES_DCORE +}; + struct hl_info_args { /* Location of relevant struct in userspace */ __u64 return_pointer; @@ -402,6 +421,10 @@ struct hl_info_args { __u32 op; union { + /* Dcore id for which the information is relevant. + * For Gaudi refer to 'enum gaudi_dcores' + */ + __u32 dcore_id; /* Context ID - Currently not in use */ __u32 ctx_id; /* Period value for utilization rate (100ms - 1000ms, in 100ms From 2e5eda4681f91bce8f65c54c684c79397708fd80 Mon Sep 17 00:00:00 2001 From: Ofir Bitton Date: Wed, 20 May 2020 16:35:08 +0300 Subject: [PATCH 05/46] habanalabs: PCIe Advanced Error Reporting support driver will now get notified upon any PCI error occurred and will respond according to the severity of the error. Signed-off-by: Ofir Bitton Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../misc/habanalabs/common/habanalabs_drv.c | 76 ++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/common/habanalabs_drv.c b/drivers/misc/habanalabs/common/habanalabs_drv.c index c6b31e93fb5e..f9067d3ef437 100644 --- a/drivers/misc/habanalabs/common/habanalabs_drv.c +++ b/drivers/misc/habanalabs/common/habanalabs_drv.c @@ -11,6 +11,7 @@ #include "habanalabs.h" #include +#include #include #define HL_DRIVER_AUTHOR "HabanaLabs Kernel Driver Team" @@ -408,6 +409,8 @@ static int hl_pci_probe(struct pci_dev *pdev, pci_set_drvdata(pdev, hdev); + pci_enable_pcie_error_reporting(pdev); + rc = hl_device_init(hdev, hl_class); if (rc) { dev_err(&pdev->dev, "Fatal error during habanalabs device init\n"); @@ -440,22 +443,93 @@ static void hl_pci_remove(struct pci_dev *pdev) return; hl_device_fini(hdev); + pci_disable_pcie_error_reporting(pdev); pci_set_drvdata(pdev, NULL); - destroy_hdev(hdev); } +/** + * hl_pci_err_detected - a PCI bus error detected on this device + * + * @pdev: pointer to pci device + * @state: PCI error type + * + * Called by the PCI subsystem whenever a non-correctable + * PCI bus error is detected + */ +static pci_ers_result_t +hl_pci_err_detected(struct pci_dev *pdev, pci_channel_state_t state) +{ + struct hl_device *hdev = pci_get_drvdata(pdev); + enum pci_ers_result result; + + switch (state) { + case pci_channel_io_normal: + return PCI_ERS_RESULT_CAN_RECOVER; + + case pci_channel_io_frozen: + dev_warn(hdev->dev, "frozen state error detected\n"); + result = PCI_ERS_RESULT_NEED_RESET; + break; + + case pci_channel_io_perm_failure: + dev_warn(hdev->dev, "failure state error detected\n"); + result = PCI_ERS_RESULT_DISCONNECT; + break; + + default: + result = PCI_ERS_RESULT_NONE; + } + + hdev->asic_funcs->halt_engines(hdev, true); + + return result; +} + +/** + * hl_pci_err_resume - resume after a PCI slot reset + * + * @pdev: pointer to pci device + * + */ +static void hl_pci_err_resume(struct pci_dev *pdev) +{ + struct hl_device *hdev = pci_get_drvdata(pdev); + + dev_warn(hdev->dev, "Resuming device after PCI slot reset\n"); + hl_device_resume(hdev); +} + +/** + * hl_pci_err_slot_reset - a PCI slot reset has just happened + * + * @pdev: pointer to pci device + * + * Determine if the driver can recover from the PCI slot reset + */ +static pci_ers_result_t hl_pci_err_slot_reset(struct pci_dev *pdev) +{ + return PCI_ERS_RESULT_RECOVERED; +} + static const struct dev_pm_ops hl_pm_ops = { .suspend = hl_pmops_suspend, .resume = hl_pmops_resume, }; +static const struct pci_error_handlers hl_pci_err_handler = { + .error_detected = hl_pci_err_detected, + .slot_reset = hl_pci_err_slot_reset, + .resume = hl_pci_err_resume, +}; + static struct pci_driver hl_pci_driver = { .name = HL_NAME, .id_table = ids, .probe = hl_pci_probe, .remove = hl_pci_remove, .driver.pm = &hl_pm_ops, + .err_handler = &hl_pci_err_handler, }; /* From acd330c141b4c49f468f00719ebc944656061eac Mon Sep 17 00:00:00 2001 From: farah kassabri Date: Tue, 4 Aug 2020 09:41:32 +0300 Subject: [PATCH 06/46] habanalabs: remove security from ARB_MST_QUIET register Allow user application to write to this register in order to be able to configure the quiet period of the QMAN between grants. Signed-off-by: farah kassabri Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../misc/habanalabs/gaudi/gaudi_security.c | 55 +++++++------------ 1 file changed, 19 insertions(+), 36 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudi_security.c b/drivers/misc/habanalabs/gaudi/gaudi_security.c index 8d5d6ddee6ed..615b547ad2b7 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi_security.c +++ b/drivers/misc/habanalabs/gaudi/gaudi_security.c @@ -831,8 +831,7 @@ static void gaudi_init_mme_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmMME0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -1311,8 +1310,7 @@ static void gaudi_init_mme_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmMME2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -1790,8 +1788,7 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -2186,8 +2183,7 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -2582,8 +2578,7 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -2978,8 +2973,7 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -3374,8 +3368,7 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -3770,8 +3763,7 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -4166,8 +4158,8 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + + mask = 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -4562,8 +4554,7 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmDMA7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -5491,8 +5482,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -5947,8 +5937,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -6402,8 +6391,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -6857,8 +6845,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -7312,8 +7299,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -7767,8 +7753,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -8223,8 +8208,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); @@ -8681,8 +8665,7 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask = 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); mask |= 1 << ((mmTPC7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); From d6b045c083842d86a749357210c3006a36e3b66f Mon Sep 17 00:00:00 2001 From: Dotan Barak Date: Thu, 6 Aug 2020 09:20:49 +0300 Subject: [PATCH 07/46] habanalabs: print the queue id in case of an error If there is a failure during the testing of a queue, to ease up debugging - print the queue id. Signed-off-by: Dotan Barak Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudi.c | 9 ++++++--- drivers/misc/habanalabs/goya/goya.c | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 45ba3a5f5b14..89d44cd82a27 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -3448,7 +3448,8 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) &fence_dma_addr); if (!fence_ptr) { dev_err(hdev->dev, - "Failed to allocate memory for queue testing\n"); + "Failed to allocate memory for H/W queue %d testing\n", + hw_queue_id); return -ENOMEM; } @@ -3459,7 +3460,8 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) GFP_KERNEL, &pkt_dma_addr); if (!fence_pkt) { dev_err(hdev->dev, - "Failed to allocate packet for queue testing\n"); + "Failed to allocate packet for H/W queue %d testing\n", + hw_queue_id); rc = -ENOMEM; goto free_fence_ptr; } @@ -3476,7 +3478,8 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) pkt_dma_addr); if (rc) { dev_err(hdev->dev, - "Failed to send fence packet\n"); + "Failed to send fence packet to H/W queue %d\n", + hw_queue_id); goto free_pkt; } diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 954f2c022d33..ac4d44fa56e4 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -2946,7 +2946,8 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) &fence_dma_addr); if (!fence_ptr) { dev_err(hdev->dev, - "Failed to allocate memory for queue testing\n"); + "Failed to allocate memory for H/W queue %d testing\n", + hw_queue_id); return -ENOMEM; } @@ -2957,7 +2958,8 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) GFP_KERNEL, &pkt_dma_addr); if (!fence_pkt) { dev_err(hdev->dev, - "Failed to allocate packet for queue testing\n"); + "Failed to allocate packet for H/W queue %d testing\n", + hw_queue_id); rc = -ENOMEM; goto free_fence_ptr; } @@ -2974,7 +2976,8 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) pkt_dma_addr); if (rc) { dev_err(hdev->dev, - "Failed to send fence packet\n"); + "Failed to send fence packet to H/W queue %d\n", + hw_queue_id); goto free_pkt; } From f5b9c8cf25a562b73c80cd4bb252ccb398259056 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 10:11:20 +0300 Subject: [PATCH 08/46] habanalabs: change CB's ID to be 64 bits Although the possible values for CB's ID are only 32 bits, there are a few places in the code where this field is shifted and passed into a function which expects 64 bits. Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/command_buffer.c | 2 +- drivers/misc/habanalabs/common/debugfs.c | 2 +- drivers/misc/habanalabs/common/habanalabs.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_buffer.c b/drivers/misc/habanalabs/common/command_buffer.c index a8004911c977..e4bbe6a8e00f 100644 --- a/drivers/misc/habanalabs/common/command_buffer.c +++ b/drivers/misc/habanalabs/common/command_buffer.c @@ -174,7 +174,7 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, goto release_cb; } - cb->id = rc; + cb->id = (u64) rc; kref_init(&cb->refcount); spin_lock_init(&cb->lock); diff --git a/drivers/misc/habanalabs/common/debugfs.c b/drivers/misc/habanalabs/common/debugfs.c index aa77771635d3..4b416f64f6ec 100644 --- a/drivers/misc/habanalabs/common/debugfs.c +++ b/drivers/misc/habanalabs/common/debugfs.c @@ -110,7 +110,7 @@ static int command_buffers_show(struct seq_file *s, void *data) seq_puts(s, "---------------------------------------------------------------\n"); } seq_printf(s, - " %03d %d 0x%08x %d %d %d\n", + " %03llu %d 0x%08x %d %d %d\n", cb->id, cb->ctx_id, cb->size, kref_read(&cb->refcount), cb->mmap, cb->cs_cnt); diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index caced12f278f..2fd268e4cf10 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -401,11 +401,11 @@ struct hl_cb_mgr { * @lock: spinlock to protect mmap/cs flows. * @debugfs_list: node in debugfs list of command buffers. * @pool_list: node in pool list of command buffers. + * @id: the CB's ID. * @kernel_address: Holds the CB's kernel virtual address. * @bus_address: Holds the CB's DMA address. * @mmap_size: Holds the CB's size that was mmaped. * @size: holds the CB's size. - * @id: the CB's ID. * @cs_cnt: holds number of CS that this CB participates in. * @ctx_id: holds the ID of the owner's context. * @mmap: true if the CB is currently mmaped to user. @@ -418,11 +418,11 @@ struct hl_cb { spinlock_t lock; struct list_head debugfs_list; struct list_head pool_list; + u64 id; u64 kernel_address; dma_addr_t bus_address; u32 mmap_size; u32 size; - u32 id; u32 cs_cnt; u32 ctx_id; u8 mmap; From f907af183b8bf35393e3057204000c16d8cb9bbe Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 10:15:27 +0300 Subject: [PATCH 09/46] habanalabs: cast int to u32 before printing it with %u %u is used for unsigned so we need to cast the int variable to u32 to avoid compiler warning. Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/common/device.c b/drivers/misc/habanalabs/common/device.c index 24b01cce0a38..dcb7f9ca7a67 100644 --- a/drivers/misc/habanalabs/common/device.c +++ b/drivers/misc/habanalabs/common/device.c @@ -286,7 +286,7 @@ static int device_early_init(struct hl_device *hdev) } for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) { - snprintf(workq_name, 32, "hl-free-jobs-%u", i); + snprintf(workq_name, 32, "hl-free-jobs-%u", (u32) i); hdev->cq_wq[i] = create_singlethread_workqueue(workq_name); if (hdev->cq_wq[i] == NULL) { dev_err(hdev->dev, "Failed to allocate CQ workqueue\n"); From bd4ef3729213280522694ff714e28192e486487d Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 10:19:28 +0300 Subject: [PATCH 10/46] habanalabs: eliminate redundant else condition If both parts of if-else are goto statements, we can remove the else and put the else goto statement after the if statement. Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/command_submission.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_submission.c b/drivers/misc/habanalabs/common/command_submission.c index 00c1ff2e953d..a811a9fdf13b 100644 --- a/drivers/misc/habanalabs/common/command_submission.c +++ b/drivers/misc/habanalabs/common/command_submission.c @@ -686,8 +686,8 @@ static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks, rc = -ENOMEM; if (is_kernel_allocated_cb) goto release_cb; - else - goto free_cs_object; + + goto free_cs_object; } job->id = i + 1; From a0e072f5a18ffa04f83669a886dc4a4cfc3a1341 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 10:46:33 +0300 Subject: [PATCH 11/46] habanalabs: use standard BIT() and GENMASK() Use the standard macros to define bitmasks. Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudiP.h | 42 +++++++++++++------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudiP.h b/drivers/misc/habanalabs/gaudi/gaudiP.h index 82137c3f3e2e..1368f6298c80 100644 --- a/drivers/misc/habanalabs/gaudi/gaudiP.h +++ b/drivers/misc/habanalabs/gaudi/gaudiP.h @@ -142,28 +142,28 @@ #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \ VA_HOST_SPACE_START) /* 767TB */ -#define HW_CAP_PLL 0x00000001 -#define HW_CAP_HBM 0x00000002 -#define HW_CAP_MMU 0x00000004 -#define HW_CAP_MME 0x00000008 -#define HW_CAP_CPU 0x00000010 -#define HW_CAP_PCI_DMA 0x00000020 -#define HW_CAP_MSI 0x00000040 -#define HW_CAP_CPU_Q 0x00000080 -#define HW_CAP_HBM_DMA 0x00000100 -#define HW_CAP_CLK_GATE 0x00000200 -#define HW_CAP_SRAM_SCRAMBLER 0x00000400 -#define HW_CAP_HBM_SCRAMBLER 0x00000800 +#define HW_CAP_PLL BIT(0) +#define HW_CAP_HBM BIT(1) +#define HW_CAP_MMU BIT(2) +#define HW_CAP_MME BIT(3) +#define HW_CAP_CPU BIT(4) +#define HW_CAP_PCI_DMA BIT(5) +#define HW_CAP_MSI BIT(6) +#define HW_CAP_CPU_Q BIT(7) +#define HW_CAP_HBM_DMA BIT(8) +#define HW_CAP_CLK_GATE BIT(9) +#define HW_CAP_SRAM_SCRAMBLER BIT(10) +#define HW_CAP_HBM_SCRAMBLER BIT(11) -#define HW_CAP_TPC0 0x01000000 -#define HW_CAP_TPC1 0x02000000 -#define HW_CAP_TPC2 0x04000000 -#define HW_CAP_TPC3 0x08000000 -#define HW_CAP_TPC4 0x10000000 -#define HW_CAP_TPC5 0x20000000 -#define HW_CAP_TPC6 0x40000000 -#define HW_CAP_TPC7 0x80000000 -#define HW_CAP_TPC_MASK 0xFF000000 +#define HW_CAP_TPC0 BIT(24) +#define HW_CAP_TPC1 BIT(25) +#define HW_CAP_TPC2 BIT(26) +#define HW_CAP_TPC3 BIT(27) +#define HW_CAP_TPC4 BIT(28) +#define HW_CAP_TPC5 BIT(29) +#define HW_CAP_TPC6 BIT(30) +#define HW_CAP_TPC7 BIT(31) +#define HW_CAP_TPC_MASK GENMASK(31, 24) #define HW_CAP_TPC_SHIFT 24 #define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39) From 65887291c6a80c3f2263348548899818b334cc8a Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 11:21:01 +0300 Subject: [PATCH 12/46] habanalabs: use FIELD_PREP() instead of << Use the standard FIELD_PREP() macro instead of << operator to perform bitmask operations. This ensures type check safety and eliminate compiler warnings. Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/hw_queue.c | 9 +- drivers/misc/habanalabs/gaudi/gaudi.c | 50 ++-- .../habanalabs/include/gaudi/gaudi_masks.h | 256 ++++++++---------- 3 files changed, 145 insertions(+), 170 deletions(-) diff --git a/drivers/misc/habanalabs/common/hw_queue.c b/drivers/misc/habanalabs/common/hw_queue.c index 65b9aa69a83e..e2f9ba04b32d 100644 --- a/drivers/misc/habanalabs/common/hw_queue.c +++ b/drivers/misc/habanalabs/common/hw_queue.c @@ -8,6 +8,7 @@ #include "habanalabs.h" #include +#include /* * hl_queue_add_ptr - add to pi or ci and checks if it wraps around @@ -288,10 +289,10 @@ static void ext_queue_schedule_job(struct hl_cs_job *job) ptr = cb->bus_address; cq_pkt.data = cpu_to_le32( - ((q->pi << CQ_ENTRY_SHADOW_INDEX_SHIFT) - & CQ_ENTRY_SHADOW_INDEX_MASK) | - (1 << CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT) | - (1 << CQ_ENTRY_READY_SHIFT)); + ((q->pi << CQ_ENTRY_SHADOW_INDEX_SHIFT) + & CQ_ENTRY_SHADOW_INDEX_MASK) | + FIELD_PREP(CQ_ENTRY_SHADOW_INDEX_VALID_MASK, 1) | + FIELD_PREP(CQ_ENTRY_READY_MASK, 1)); /* * No need to protect pi_offset because scheduling to the diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 89d44cd82a27..b6c3fcd21697 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -682,10 +682,10 @@ static int _gaudi_init_tpc_mem(struct hl_device *hdev, init_tpc_mem_pkt->tsize = cpu_to_le32(tpc_kernel_size); - ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) | - (1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) | - (1 << GAUDI_PKT_CTL_RB_SHIFT) | - (1 << GAUDI_PKT_CTL_MB_SHIFT)); + ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA); + ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1); + ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1); + ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1); init_tpc_mem_pkt->ctl = cpu_to_le32(ctl); @@ -2328,7 +2328,8 @@ static void gaudi_init_tpc_qmans(struct hl_device *hdev) tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0; - gaudi->hw_cap_initialized |= 1 << (HW_CAP_TPC_SHIFT + tpc_id); + gaudi->hw_cap_initialized |= + FIELD_PREP(HW_CAP_TPC_MASK, 1 << tpc_id); } } @@ -2907,13 +2908,13 @@ static void gaudi_pre_hw_init(struct hl_device *hdev) (CFG_RST_H_DMA_MASK | CFG_RST_H_MME_MASK | CFG_RST_H_SM_MASK | - CFG_RST_H_TPC_MASK)); + CFG_RST_H_TPC_7_MASK)); WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK); WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H, (CFG_RST_H_HBM_MASK | - CFG_RST_H_TPC_MASK | + CFG_RST_H_TPC_7_MASK | CFG_RST_H_NIC_MASK | CFG_RST_H_SM_MASK | CFG_RST_H_DMA_MASK | @@ -3466,9 +3467,10 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) goto free_fence_ptr; } - tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | - (1 << GAUDI_PKT_CTL_EB_SHIFT) | - (1 << GAUDI_PKT_CTL_MB_SHIFT); + tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT); + tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1); + tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1); + fence_pkt->ctl = cpu_to_le32(tmp); fence_pkt->value = cpu_to_le32(fence_val); fence_pkt->addr = cpu_to_le64(fence_dma_addr); @@ -4285,11 +4287,11 @@ static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, cq_pkt = (struct packet_msg_prot *) (uintptr_t) (kernel_address + len - (sizeof(struct packet_msg_prot) * 2)); - tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | - (1 << GAUDI_PKT_CTL_MB_SHIFT); + tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT); + tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1); if (eb) - tmp |= (1 << GAUDI_PKT_CTL_EB_SHIFT); + tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1); cq_pkt->ctl = cpu_to_le32(tmp); cq_pkt->value = cpu_to_le32(cq_val); @@ -4297,8 +4299,8 @@ static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, cq_pkt++; - tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | - (1 << GAUDI_PKT_CTL_MB_SHIFT); + tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT); + tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1); cq_pkt->ctl = cpu_to_le32(tmp); cq_pkt->value = cpu_to_le32(1); @@ -4330,11 +4332,12 @@ static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt)); cb_size = sizeof(*lin_dma_pkt); - ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) | - (1 << GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT) | - (1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) | - (1 << GAUDI_PKT_CTL_RB_SHIFT) | - (1 << GAUDI_PKT_CTL_MB_SHIFT)); + ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA); + ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK, 1); + ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1); + ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1); + ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1); + lin_dma_pkt->ctl = cpu_to_le32(ctl); lin_dma_pkt->src_addr = cpu_to_le64(val); lin_dma_pkt->dst_addr |= cpu_to_le64(addr); @@ -4940,9 +4943,10 @@ static int gaudi_send_job_on_qman0(struct hl_device *hdev, fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address + job->job_cb_size - sizeof(struct packet_msg_prot)); - tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | - (1 << GAUDI_PKT_CTL_EB_SHIFT) | - (1 << GAUDI_PKT_CTL_MB_SHIFT); + tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT); + tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1); + tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1); + fence_pkt->ctl = cpu_to_le32(tmp); fence_pkt->value = cpu_to_le32(GAUDI_QMAN0_FENCE_VAL); fence_pkt->addr = cpu_to_le64(fence_dma_addr); diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h index 3510c42d24e3..90c048ccbcbf 100644 --- a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h @@ -9,194 +9,164 @@ #define GAUDI_MASKS_H_ #include "asic_reg/gaudi_regs.h" +#include /* Useful masks for bits in various registers */ #define PCI_DMA_QMAN_ENABLE (\ - (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ - (0xF << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ - (0xF << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF))) #define QMAN_EXTERNAL_MAKE_TRUSTED (\ - (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \ - (0xF << DMA0_QM_GLBL_PROT_CQF_SHIFT) | \ - (0xF << DMA0_QM_GLBL_PROT_CP_SHIFT) | \ - (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) #define QMAN_INTERNAL_MAKE_TRUSTED (\ - (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \ - (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) #define HBM_DMA_QMAN_ENABLE (\ - (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ - (0x1F << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ - (0x1F << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ + (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) #define QMAN_MME_ENABLE (\ - (0xF << MME0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ - (0x1F << MME0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ - (0x1F << MME0_QM_GLBL_CFG0_CP_EN_SHIFT)) + (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ + (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) #define QMAN_TPC_ENABLE (\ - (0xF << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ - (0x1F << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ - (0x1F << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT)) + (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ + (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ + (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) #define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\ - (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \ - (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \ - (0x10 << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \ - (1 << DMA0_QM_CGM_CFG_EN_SHIFT)) + (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) #define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\ - (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \ - (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \ - (0xF << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \ - (1 << DMA0_QM_CGM_CFG_EN_SHIFT)) + (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) #define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ - (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ - (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ - (0xF << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF))) #define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ - (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ - (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ - (0xF << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF))) #define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ - (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ - (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ - (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) #define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ - (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ - (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ - (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F))) #define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ - (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ - (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ - (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) #define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ - (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ - (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ - (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F))) #define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ - (0xF << MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ - (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ - (0x1F << MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) #define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ - (0xF << MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ - (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ - (0x1F << MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ + (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F))) -#define QMAN_CGM1_PWR_GATE_EN (0xA << DMA0_QM_CGM_CFG1_MASK_TH_SHIFT) +#define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA)) /* RESET registers configuration */ -#define CFG_RST_L_PSOC_SHIFT 0 -#define CFG_RST_L_PCIE_SHIFT 1 -#define CFG_RST_L_PCIE_IF_SHIFT 2 -#define CFG_RST_L_HBM_S_PLL_SHIFT 3 -#define CFG_RST_L_TPC_S_PLL_SHIFT 4 -#define CFG_RST_L_MME_S_PLL_SHIFT 5 -#define CFG_RST_L_CPU_PLL_SHIFT 6 -#define CFG_RST_L_PCIE_PLL_SHIFT 7 -#define CFG_RST_L_NIC_S_PLL_SHIFT 8 -#define CFG_RST_L_HBM_N_PLL_SHIFT 9 -#define CFG_RST_L_TPC_N_PLL_SHIFT 10 -#define CFG_RST_L_MME_N_PLL_SHIFT 11 -#define CFG_RST_L_NIC_N_PLL_SHIFT 12 -#define CFG_RST_L_DMA_W_PLL_SHIFT 13 -#define CFG_RST_L_SIF_W_PLL_SHIFT 14 -#define CFG_RST_L_MESH_W_PLL_SHIFT 15 -#define CFG_RST_L_SRAM_W_PLL_SHIFT 16 -#define CFG_RST_L_DMA_E_PLL_SHIFT 17 -#define CFG_RST_L_SIF_E_PLL_SHIFT 18 -#define CFG_RST_L_MESH_E_PLL_SHIFT 19 -#define CFG_RST_L_SRAM_E_PLL_SHIFT 20 -#define CFG_RST_L_IF_1_SHIFT 21 -#define CFG_RST_L_IF_0_SHIFT 22 -#define CFG_RST_L_IF_2_SHIFT 23 -#define CFG_RST_L_IF_3_SHIFT 24 -#define CFG_RST_L_TPC_0_SHIFT 25 -#define CFG_RST_L_TPC_1_SHIFT 26 -#define CFG_RST_L_TPC_2_SHIFT 27 -#define CFG_RST_L_TPC_3_SHIFT 28 -#define CFG_RST_L_TPC_4_SHIFT 29 -#define CFG_RST_L_TPC_5_SHIFT 30 -#define CFG_RST_L_TPC_6_SHIFT 31 -#define CFG_RST_H_TPC_7_SHIFT 0 -#define CFG_RST_H_MME_0_SHIFT 1 -#define CFG_RST_H_MME_1_SHIFT 2 -#define CFG_RST_H_MME_2_SHIFT 3 -#define CFG_RST_H_MME_3_SHIFT 4 -#define CFG_RST_H_HBM_0_SHIFT 5 -#define CFG_RST_H_HBM_1_SHIFT 6 -#define CFG_RST_H_HBM_2_SHIFT 7 -#define CFG_RST_H_HBM_3_SHIFT 8 -#define CFG_RST_H_NIC_0_SHIFT 9 -#define CFG_RST_H_NIC_1_SHIFT 10 -#define CFG_RST_H_NIC_2_SHIFT 11 -#define CFG_RST_H_NIC_3_SHIFT 12 -#define CFG_RST_H_NIC_4_SHIFT 13 -#define CFG_RST_H_SM_0_SHIFT 14 -#define CFG_RST_H_SM_1_SHIFT 15 -#define CFG_RST_H_SM_2_SHIFT 16 -#define CFG_RST_H_SM_3_SHIFT 17 -#define CFG_RST_H_DMA_0_SHIFT 18 -#define CFG_RST_H_DMA_1_SHIFT 19 -#define CFG_RST_H_CPU_SHIFT 20 -#define CFG_RST_H_MMU_SHIFT 21 +#define CFG_RST_L_PSOC_MASK BIT_MASK(0) +#define CFG_RST_L_PCIE_MASK BIT_MASK(1) +#define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2) +#define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3) +#define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4) +#define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5) +#define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6) +#define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7) +#define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8) +#define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9) +#define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10) +#define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11) +#define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12) +#define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13) +#define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14) +#define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15) +#define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16) +#define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17) +#define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18) +#define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19) +#define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20) +#define CFG_RST_L_IF_1_MASK BIT_MASK(21) +#define CFG_RST_L_IF_0_MASK BIT_MASK(22) +#define CFG_RST_L_IF_2_MASK BIT_MASK(23) +#define CFG_RST_L_IF_3_MASK BIT_MASK(24) +#define CFG_RST_L_IF_MASK GENMASK(24, 21) -#define CFG_RST_H_DMA_MASK ((1 << CFG_RST_H_DMA_0_SHIFT) | \ - (1 << CFG_RST_H_DMA_1_SHIFT)) +#define CFG_RST_L_TPC_0_MASK BIT_MASK(25) +#define CFG_RST_L_TPC_1_MASK BIT_MASK(26) +#define CFG_RST_L_TPC_2_MASK BIT_MASK(27) +#define CFG_RST_L_TPC_3_MASK BIT_MASK(28) +#define CFG_RST_L_TPC_4_MASK BIT_MASK(29) +#define CFG_RST_L_TPC_5_MASK BIT_MASK(30) +#define CFG_RST_L_TPC_6_MASK BIT_MASK(31) +#define CFG_RST_L_TPC_MASK GENMASK(31, 25) -#define CFG_RST_H_CPU_MASK (1 << CFG_RST_H_CPU_SHIFT) -#define CFG_RST_H_MMU_MASK (1 << CFG_RST_H_MMU_SHIFT) +#define CFG_RST_H_TPC_7_MASK BIT_MASK(0) -#define CFG_RST_H_HBM_MASK ((1 << CFG_RST_H_HBM_0_SHIFT) | \ - (1 << CFG_RST_H_HBM_1_SHIFT) | \ - (1 << CFG_RST_H_HBM_2_SHIFT) | \ - (1 << CFG_RST_H_HBM_3_SHIFT)) +#define CFG_RST_H_MME_0_MASK BIT_MASK(1) +#define CFG_RST_H_MME_1_MASK BIT_MASK(2) +#define CFG_RST_H_MME_2_MASK BIT_MASK(3) +#define CFG_RST_H_MME_3_MASK BIT_MASK(4) +#define CFG_RST_H_MME_MASK GENMASK(4, 1) -#define CFG_RST_H_NIC_MASK ((1 << CFG_RST_H_NIC_0_SHIFT) | \ - (1 << CFG_RST_H_NIC_1_SHIFT) | \ - (1 << CFG_RST_H_NIC_2_SHIFT) | \ - (1 << CFG_RST_H_NIC_3_SHIFT) | \ - (1 << CFG_RST_H_NIC_4_SHIFT)) +#define CFG_RST_H_HBM_0_MASK BIT_MASK(5) +#define CFG_RST_H_HBM_1_MASK BIT_MASK(6) +#define CFG_RST_H_HBM_2_MASK BIT_MASK(7) +#define CFG_RST_H_HBM_3_MASK BIT_MASK(8) +#define CFG_RST_H_HBM_MASK GENMASK(8, 5) -#define CFG_RST_H_SM_MASK ((1 << CFG_RST_H_SM_0_SHIFT) | \ - (1 << CFG_RST_H_SM_1_SHIFT) | \ - (1 << CFG_RST_H_SM_2_SHIFT) | \ - (1 << CFG_RST_H_SM_3_SHIFT)) +#define CFG_RST_H_NIC_0_MASK BIT_MASK(9) +#define CFG_RST_H_NIC_1_MASK BIT_MASK(10) +#define CFG_RST_H_NIC_2_MASK BIT_MASK(11) +#define CFG_RST_H_NIC_3_MASK BIT_MASK(12) +#define CFG_RST_H_NIC_4_MASK BIT_MASK(13) +#define CFG_RST_H_NIC_MASK GENMASK(13, 9) -#define CFG_RST_H_MME_MASK ((1 << CFG_RST_H_MME_0_SHIFT) | \ - (1 << CFG_RST_H_MME_1_SHIFT) | \ - (1 << CFG_RST_H_MME_2_SHIFT) | \ - (1 << CFG_RST_H_MME_3_SHIFT)) +#define CFG_RST_H_SM_0_MASK BIT_MASK(14) +#define CFG_RST_H_SM_1_MASK BIT_MASK(15) +#define CFG_RST_H_SM_2_MASK BIT_MASK(16) +#define CFG_RST_H_SM_3_MASK BIT_MASK(17) +#define CFG_RST_H_SM_MASK GENMASK(17, 14) -#define CFG_RST_L_PSOC_MASK (1 << CFG_RST_L_PSOC_SHIFT) +#define CFG_RST_H_DMA_0_MASK BIT_MASK(18) +#define CFG_RST_H_DMA_1_MASK BIT_MASK(19) +#define CFG_RST_H_DMA_MASK GENMASK(19, 18) -#define CFG_RST_L_IF_MASK ((1 << CFG_RST_L_IF_0_SHIFT) | \ - (1 << CFG_RST_L_IF_1_SHIFT) | \ - (1 << CFG_RST_L_IF_2_SHIFT) | \ - (1 << CFG_RST_L_IF_3_SHIFT)) - -#define CFG_RST_L_TPC_MASK ((1 << CFG_RST_L_TPC_0_SHIFT) | \ - (1 << CFG_RST_L_TPC_1_SHIFT) | \ - (1 << CFG_RST_L_TPC_2_SHIFT) | \ - (1 << CFG_RST_L_TPC_3_SHIFT) | \ - (1 << CFG_RST_L_TPC_4_SHIFT) | \ - (1 << CFG_RST_L_TPC_5_SHIFT) | \ - (1 << CFG_RST_L_TPC_6_SHIFT)) - -#define CFG_RST_H_TPC_MASK (1 << CFG_RST_H_TPC_7_SHIFT) - -#define CA53_RESET (1 << CFG_RST_H_CPU_SHIFT) +#define CFG_RST_H_CPU_MASK BIT_MASK(20) +#define CFG_RST_H_MMU_MASK BIT_MASK(21) #define UNIT_RST_L_PSOC_SHIFT 0 #define UNIT_RST_L_PCIE_SHIFT 1 From 0358372bbe86705399490d82fb022aa34bdc2ee4 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 11:24:05 +0300 Subject: [PATCH 13/46] habanalabs: remove redundant assignment to variable new_dma_pkt->ctl is assigned a value and then is reassigned a new value without the first value ever being used. Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index b6c3fcd21697..1cf37332a0ff 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -3971,8 +3971,6 @@ static int gaudi_patch_dma_packet(struct hl_device *hdev, } } - new_dma_pkt->ctl = user_dma_pkt->ctl; - ctl = le32_to_cpu(user_dma_pkt->ctl); if (likely(dma_desc_cnt)) ctl &= ~GAUDI_PKT_CTL_EB_MASK; From 31ac1f1a5712696c45ea3ebb23e60b4e7e5cb0b6 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 11:28:13 +0300 Subject: [PATCH 14/46] habanalabs: check TPC vector pipe is empty The driver waits for the TPC vector pipe to be empty before checking if the TPC kernel has finished executing, but the code doesn't validate that the pipe was indeed empty, it just wait for it without checking the return value. Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 1cf37332a0ff..a0932261e67c 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -6304,6 +6304,15 @@ static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel, 1000, kernel_timeout); + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for TPC%d vector pipe\n", + tpc_id); + hdev->asic_funcs->set_clock_gating(hdev); + mutex_unlock(&gaudi->clk_gate_mutex); + return -EIO; + } + rc = hl_poll_timeout( hdev, mmTPC0_CFG_WQ_INFLIGHT_CNTR + offset, From 107dd314658e8e017f3a384917261ec7e3309722 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 12 Aug 2020 11:32:27 +0300 Subject: [PATCH 15/46] habanalabs: use 1U when shifting bits Eliminate following warning: warning: Shifting signed 32-bit value by 31 bits is undefined behavior Reported-by: kernel test robot Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- .../misc/habanalabs/gaudi/gaudi_security.c | 12332 ++++++++-------- 1 file changed, 6166 insertions(+), 6166 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudi_security.c b/drivers/misc/habanalabs/gaudi/gaudi_security.c index 615b547ad2b7..2d7add0e5bcc 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi_security.c +++ b/drivers/misc/habanalabs/gaudi/gaudi_security.c @@ -487,241 +487,241 @@ static void gaudi_init_mme_protection_bits(struct hl_device *hdev) pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_CTRL_RESET & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_RL_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_RL_MIN & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); - mask |= 1 << ((mmMME0_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1U << ((mmMME0_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + mask = 1U << ((mmMME0_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -729,235 +729,235 @@ static void gaudi_init_mme_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmMME0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmMME0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmMME0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME1_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME1_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME1_CTRL_RESET & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_QM_STALL & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_LOG_SHADOW & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_RL_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_RL_MIN & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); - mask |= 1 << ((mmMME1_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + mask = 1U << ((mmMME1_CTRL_RESET & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1U << ((mmMME1_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME1_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME1_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME1_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + mask = 1U << ((mmMME1_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -965,241 +965,241 @@ static void gaudi_init_mme_protection_bits(struct hl_device *hdev) pb_addr = (mmMME2_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_CTRL_RESET & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_QM_STALL & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_LOG_SHADOW & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_RL_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_RL_MIN & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); - mask |= 1 << ((mmMME2_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + mask = 1U << ((mmMME2_CTRL_RESET & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1U << ((mmMME2_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + mask = 1U << ((mmMME2_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1207,102 +1207,102 @@ static void gaudi_init_mme_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1310,133 +1310,133 @@ static void gaudi_init_mme_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmMME2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmMME2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmMME2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME3_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME3_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME3_CTRL_RESET & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_QM_STALL & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_LOG_SHADOW & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_RL_TH & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_RL_MIN & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); - mask |= 1 << ((mmMME3_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + mask = 1U << ((mmMME3_CTRL_RESET & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1U << ((mmMME3_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmMME3_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmMME3_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmMME3_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + mask = 1U << ((mmMME3_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1484,199 +1484,199 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) pb_addr = (mmDMA0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1685,102 +1685,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + @@ -1788,289 +1788,289 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -2079,102 +2079,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -2183,289 +2183,289 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -2474,102 +2474,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -2578,289 +2578,289 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -2869,102 +2869,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -2973,289 +2973,289 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -3264,102 +3264,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -3368,289 +3368,289 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -3659,102 +3659,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -3763,289 +3763,289 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -4054,102 +4054,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -4159,289 +4159,289 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) ((mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -4450,102 +4450,102 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -4554,605 +4554,605 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev) word_offset = ((mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA0_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA0_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA0_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA0_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA0_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA0_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA0_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA0_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA0_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA0_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA1_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA1_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA1_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA1_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA1_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA1_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA1_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA1_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA1_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA1_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA2_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA2_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA2_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA2_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA2_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA2_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA2_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA2_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA2_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA2_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA3_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA3_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA3_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA3_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA3_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA3_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA3_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA3_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA3_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA3_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA4_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA4_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA4_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA4_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA4_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA4_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA4_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA4_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA4_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA4_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA5_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA5_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA5_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA5_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA5_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA5_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA5_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA5_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA5_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA5_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA6_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA6_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA6_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA6_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA6_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA6_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA6_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA6_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA6_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA6_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_CORE_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + mask = 1U << ((mmDMA7_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_CORE_PROT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_SECURE_PROPS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + mask = 1U << ((mmDMA7_CORE_PROT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_NON_SECURE_PROPS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_ARCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_WR_MAX_AWID & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_WR_AWCACHE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_WR_INFLIGHTS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_ERRMSG_WDATA & 0x7F) >> 2); + mask = 1U << ((mmDMA7_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_ERRMSG_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_CORE_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_STS1 & 0x7F) >> 2); + mask = 1U << ((mmDMA7_CORE_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_STS1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmDMA7_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmDMA7_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmDMA7_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_DBG_DESC_CNT & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_DBG_STS & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); - mask |= 1 << ((mmDMA7_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + mask = 1U << ((mmDMA7_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1U << ((mmDMA7_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); } @@ -5176,199 +5176,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -5378,102 +5378,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -5482,149 +5482,149 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC0_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC0_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC0_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -5633,199 +5633,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -5833,102 +5833,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -5937,149 +5937,149 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC1_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC1_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC1_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -6088,199 +6088,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -6288,102 +6288,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -6391,149 +6391,149 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC2_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC2_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC2_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -6542,199 +6542,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -6742,102 +6742,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -6845,149 +6845,149 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC3_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC3_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC3_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -6996,199 +6996,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -7196,102 +7196,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -7299,149 +7299,149 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC4_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC4_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC4_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -7450,199 +7450,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -7650,102 +7650,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -7753,149 +7753,149 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC5_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC5_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC5_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -7904,199 +7904,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -8104,102 +8104,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -8208,84 +8208,84 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -8293,65 +8293,65 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC6_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC6_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC6_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -8360,199 +8360,199 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_STS1_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_SIZE_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_SIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_SIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_SIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_PI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_PI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_PI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_PI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_CFG1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_STS0_3 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_STS0_3 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_PQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_PQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS0_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS1_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS1_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS1_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_STS1_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_0 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_0 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_CQ_CTL_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_CTL_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_CTL_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_CTL_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -8562,102 +8562,102 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) word_offset = ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_CP_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_DBG_0_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_DBG_0_1 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_DBG_0_1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_CP_DBG_0_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_DBG_0_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_DBG_0_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_ARB_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -8665,149 +8665,149 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_ARB_STATE_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MSG_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CGM_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CGM_STS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CGM_CFG1 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CGM_STS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CGM_CFG1 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_AXCACHE & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_IND_GW_APB_CFG & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + mask = 1U << ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_CFG_ROUND_CSR & 0x7F) >> 2); + mask = 1U << ((mmTPC7_CFG_ROUND_CSR & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_CFG_PROT & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_RD_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_WR_RATE_LIMIT & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_WQ_CREDITS & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_ARUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_ARUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_AWUSER_LO & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_AWUSER_HI & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_OPCODE_EXEC & 0x7F) >> 2); + mask = 1U << ((mmTPC7_CFG_PROT & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_OPCODE_EXEC & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); pb_addr = (mmTPC7_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) << 2; - mask = 1 << ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_DBGMEM_ADD & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_DBGMEM_CTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_DBGMEM_RC & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); - mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + mask = 1U << ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); } From d90416c84d86ff78a2181f135d72d564430107b8 Mon Sep 17 00:00:00 2001 From: farah kassabri Date: Wed, 12 Aug 2020 17:20:13 +0300 Subject: [PATCH 16/46] habanalabs: extend busy engines mask to 64 bits change busy engines bitmask to 64 bits in order to represent more engines, needed for future ASIC support. Signed-off-by: farah kassabri Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/habanalabs.h | 2 +- drivers/misc/habanalabs/common/habanalabs_ioctl.c | 2 +- drivers/misc/habanalabs/gaudi/gaudi.c | 2 +- drivers/misc/habanalabs/goya/goya.c | 2 +- include/uapi/misc/habanalabs.h | 6 ++++++ 5 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 2fd268e4cf10..fbdf105c4bb2 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -754,7 +754,7 @@ struct hl_asic_funcs { void (*set_clock_gating)(struct hl_device *hdev); void (*disable_clock_gating)(struct hl_device *hdev); int (*debug_coresight)(struct hl_device *hdev, void *data); - bool (*is_device_idle)(struct hl_device *hdev, u32 *mask, + bool (*is_device_idle)(struct hl_device *hdev, u64 *mask, struct seq_file *s); int (*soft_reset_late_init)(struct hl_device *hdev); void (*hw_queues_lock)(struct hl_device *hdev); diff --git a/drivers/misc/habanalabs/common/habanalabs_ioctl.c b/drivers/misc/habanalabs/common/habanalabs_ioctl.c index fe6c5534d378..a94800014243 100644 --- a/drivers/misc/habanalabs/common/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/common/habanalabs_ioctl.c @@ -132,7 +132,7 @@ static int hw_idle(struct hl_device *hdev, struct hl_info_args *args) return -EINVAL; hw_idle.is_idle = hdev->asic_funcs->is_device_idle(hdev, - &hw_idle.busy_engines_mask, NULL); + &hw_idle.busy_engines_mask_ext, NULL); return copy_to_user(out, &hw_idle, min((size_t) max_size, sizeof(hw_idle))) ? -EFAULT : 0; diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index a0932261e67c..ba964a316b0b 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -6083,7 +6083,7 @@ static int gaudi_armcp_info_get(struct hl_device *hdev) return 0; } -static bool gaudi_is_device_idle(struct hl_device *hdev, u32 *mask, +static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask, struct seq_file *s) { struct gaudi_device *gaudi = hdev->asic_specific; diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index ac4d44fa56e4..5fb3565c80c5 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -5148,7 +5148,7 @@ static void goya_disable_clock_gating(struct hl_device *hdev) /* clock gating not supported in Goya */ } -static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask, +static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask, struct seq_file *s) { const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n"; diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index ca6dc1fc250e..693081728ef3 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -319,6 +319,12 @@ struct hl_info_hw_idle { * Bits definition is according to `enum _enging_id'. */ __u32 busy_engines_mask; + + /* + * Extended Bitmask of busy engines. + * Bits definition is according to `enum _enging_id'. + */ + __u64 busy_engines_mask_ext; }; struct hl_info_device_status { From 56004701f52e60475f0ebdb1da6fc6bf7cc4b80c Mon Sep 17 00:00:00 2001 From: Tomer Tayar Date: Tue, 18 Aug 2020 15:06:56 +0300 Subject: [PATCH 17/46] habanalabs: Include linux/bitfield.h only in habanalabs.h Include linux/bitfield.h only in habanalabs.h, instead of in each and every file that needs it, as habanalabs.h is already included by all. Signed-off-by: Tomer Tayar Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/habanalabs.h | 1 + drivers/misc/habanalabs/common/hw_queue.c | 1 - drivers/misc/habanalabs/common/pci.c | 1 - drivers/misc/habanalabs/gaudi/gaudi.c | 1 - drivers/misc/habanalabs/include/gaudi/gaudi_masks.h | 1 - 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index fbdf105c4bb2..5ef487a3b843 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -18,6 +18,7 @@ #include #include #include +#include #define HL_NAME "habanalabs" diff --git a/drivers/misc/habanalabs/common/hw_queue.c b/drivers/misc/habanalabs/common/hw_queue.c index e2f9ba04b32d..5e66c98fb0d3 100644 --- a/drivers/misc/habanalabs/common/hw_queue.c +++ b/drivers/misc/habanalabs/common/hw_queue.c @@ -8,7 +8,6 @@ #include "habanalabs.h" #include -#include /* * hl_queue_add_ptr - add to pi or ci and checks if it wraps around diff --git a/drivers/misc/habanalabs/common/pci.c b/drivers/misc/habanalabs/common/pci.c index 2770f03b6cbb..923b2606e29f 100644 --- a/drivers/misc/habanalabs/common/pci.c +++ b/drivers/misc/habanalabs/common/pci.c @@ -9,7 +9,6 @@ #include "../include/hw_ip/pci/pci_general.h" #include -#include #define HL_PLDM_PCI_ELBI_TIMEOUT_MSEC (HL_PCI_ELBI_TIMEOUT_MSEC * 10) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index ba964a316b0b..4a4327d9cbbf 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -21,7 +21,6 @@ #include #include #include -#include /* * Gaudi security scheme: diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h index 90c048ccbcbf..f395721060bd 100644 --- a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h @@ -9,7 +9,6 @@ #define GAUDI_MASKS_H_ #include "asic_reg/gaudi_regs.h" -#include /* Useful masks for bits in various registers */ #define PCI_DMA_QMAN_ENABLE (\ From 9f3064913e1b9b4153accbd33aaf1983be92c569 Mon Sep 17 00:00:00 2001 From: farah kassabri Date: Sun, 9 Aug 2020 16:25:53 +0300 Subject: [PATCH 18/46] habanalabs: add support for getting device total energy Add driver implementation for reading the total energy consumption from the device ARM FW. Signed-off-by: farah kassabri Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/firmware_if.c | 24 +++++++++++++++++++ drivers/misc/habanalabs/common/habanalabs.h | 2 ++ .../misc/habanalabs/common/habanalabs_ioctl.c | 24 +++++++++++++++++++ .../misc/habanalabs/include/common/armcp_if.h | 1 + include/uapi/misc/habanalabs.h | 10 ++++++++ 5 files changed, 61 insertions(+) diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c index 61f5edc96e16..eb66ff532c6a 100644 --- a/drivers/misc/habanalabs/common/firmware_if.c +++ b/drivers/misc/habanalabs/common/firmware_if.c @@ -411,6 +411,30 @@ int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, return rc; } +int hl_fw_armcp_total_energy_get(struct hl_device *hdev, + u64 *total_energy) +{ + struct armcp_packet pkt = {}; + long result; + int rc; + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_TOTAL_ENERGY_GET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_ARMCP_INFO_TIMEOUT_USEC, &result); + if (rc) { + dev_err(hdev->dev, + "Failed to handle ArmCP total energy pkt, error %d\n", + rc); + return rc; + } + + *total_energy = result; + + return rc; +} + static void fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg) { u32 err_val; diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 5ef487a3b843..6577a73e3227 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -1852,6 +1852,8 @@ int hl_fw_armcp_info_get(struct hl_device *hdev); int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size); int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, struct hl_info_pci_counters *counters); +int hl_fw_armcp_total_energy_get(struct hl_device *hdev, + u64 *total_energy); int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, u32 boot_err0_reg, bool skip_bmc, diff --git a/drivers/misc/habanalabs/common/habanalabs_ioctl.c b/drivers/misc/habanalabs/common/habanalabs_ioctl.c index a94800014243..18ee14b4b0e1 100644 --- a/drivers/misc/habanalabs/common/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/common/habanalabs_ioctl.c @@ -357,6 +357,27 @@ static int sync_manager_info(struct hl_fpriv *hpriv, struct hl_info_args *args) sizeof(sm_info))) ? -EFAULT : 0; } +static int total_energy_consumption_info(struct hl_fpriv *hpriv, + struct hl_info_args *args) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_info_energy total_energy = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + int rc; + + if ((!max_size) || (!out)) + return -EINVAL; + + rc = hl_fw_armcp_total_energy_get(hdev, + &total_energy.total_energy_consumption); + if (rc) + return rc; + + return copy_to_user(out, &total_energy, + min((size_t) max_size, sizeof(total_energy))) ? -EFAULT : 0; +} + static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, struct device *dev) { @@ -429,6 +450,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, case HL_INFO_SYNC_MANAGER: return sync_manager_info(hpriv, args); + case HL_INFO_TOTAL_ENERGY: + return total_energy_consumption_info(hpriv, args); + default: dev_err(dev, "Invalid request %d\n", args->op); rc = -ENOTTY; diff --git a/drivers/misc/habanalabs/include/common/armcp_if.h b/drivers/misc/habanalabs/include/common/armcp_if.h index 1403c937253c..4d78898524e9 100644 --- a/drivers/misc/habanalabs/include/common/armcp_if.h +++ b/drivers/misc/habanalabs/include/common/armcp_if.h @@ -245,6 +245,7 @@ enum armcp_packet_id { ARMCP_PACKET_CURRENT_SET, /* sysfs */ ARMCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ ARMCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ + ARMCP_PACKET_TOTAL_ENERGY_GET, /* internal */ }; #define ARMCP_PACKET_FENCE_VAL 0xFE8CE7A5 diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index 693081728ef3..6803991726e8 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -267,6 +267,7 @@ enum hl_device_status { * HL_INFO_PCI_COUNTERS - Retrieve PCI counters * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore + * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -282,6 +283,7 @@ enum hl_device_status { #define HL_INFO_PCI_COUNTERS 12 #define HL_INFO_CLK_THROTTLE_REASON 13 #define HL_INFO_SYNC_MANAGER 14 +#define HL_INFO_TOTAL_ENERGY 15 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -375,6 +377,14 @@ struct hl_info_clk_throttle { __u32 clk_throttling_reason; }; +/** + * struct hl_info_energy - device energy information + * @total_energy_consumption: total device energy consumption + */ +struct hl_info_energy { + __u64 total_energy_consumption; +}; + /** * struct hl_info_sync_manager - sync manager information * @first_available_sync_object: first available sob From 42b0698adde1beb3cd744fd4ea12bb75a80613ab Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Fri, 21 Aug 2020 09:59:18 +0300 Subject: [PATCH 19/46] habanalabs: update GAUDI hardware specs Add define for the 2 MME slave engines. Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/include/gaudi/gaudi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi.h b/drivers/misc/habanalabs/include/gaudi/gaudi.h index 8829891d3eef..f9ea897ae42c 100644 --- a/drivers/misc/habanalabs/include/gaudi/gaudi.h +++ b/drivers/misc/habanalabs/include/gaudi/gaudi.h @@ -44,6 +44,8 @@ #define MME_NUMBER_OF_MASTER_ENGINES 2 +#define MME_NUMBER_OF_SLAVE_ENGINES 2 + #define TPC_NUMBER_OF_ENGINES 8 #define DMA_NUMBER_OF_CHANNELS 8 From 2f55342c5e4d3ea94c0b8237f3ad26963269f90f Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sat, 15 Aug 2020 16:28:10 +0300 Subject: [PATCH 20/46] habanalabs: replace armcp with the generic cpucp ArmCP mandates that the device CPU is always an ARM processor, which might be wrong in the future. Most of this change is an internal renaming of variables, functions and defines but there are two entries in sysfs which have armcp in their names. Add identical cpucp entries but don't remove yet the armcp entries. Those will be deprecated next year. Add the documentation about it in sysfs documentation. Signed-off-by: Moti Haimovski Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../ABI/testing/sysfs-driver-habanalabs | 18 +- drivers/misc/habanalabs/common/debugfs.c | 18 +- drivers/misc/habanalabs/common/device.c | 2 +- drivers/misc/habanalabs/common/firmware_if.c | 127 ++++---- drivers/misc/habanalabs/common/habanalabs.h | 20 +- .../misc/habanalabs/common/habanalabs_ioctl.c | 12 +- drivers/misc/habanalabs/common/hwmon.c | 60 ++-- drivers/misc/habanalabs/common/irq.c | 2 +- drivers/misc/habanalabs/common/sysfs.c | 60 ++-- drivers/misc/habanalabs/gaudi/gaudi.c | 30 +- drivers/misc/habanalabs/gaudi/gaudiP.h | 4 +- drivers/misc/habanalabs/goya/goya.c | 34 +-- drivers/misc/habanalabs/goya/goyaP.h | 2 +- .../include/common/{armcp_if.h => cpucp_if.h} | 273 +++++++++--------- include/uapi/misc/habanalabs.h | 4 +- 15 files changed, 350 insertions(+), 316 deletions(-) rename drivers/misc/habanalabs/include/common/{armcp_if.h => cpucp_if.h} (63%) diff --git a/Documentation/ABI/testing/sysfs-driver-habanalabs b/Documentation/ABI/testing/sysfs-driver-habanalabs index 1a14bf9b22ba..169ae4b2a180 100644 --- a/Documentation/ABI/testing/sysfs-driver-habanalabs +++ b/Documentation/ABI/testing/sysfs-driver-habanalabs @@ -2,13 +2,17 @@ What: /sys/class/habanalabs/hl/armcp_kernel_ver Date: Jan 2019 KernelVersion: 5.1 Contact: oded.gabbay@gmail.com -Description: Version of the Linux kernel running on the device's CPU +Description: Version of the Linux kernel running on the device's CPU. + Will be DEPRECATED in Linux kernel version 5.10, and be + replaced with cpucp_kernel_ver What: /sys/class/habanalabs/hl/armcp_ver Date: Jan 2019 KernelVersion: 5.1 Contact: oded.gabbay@gmail.com Description: Version of the application running on the device's CPU + Will be DEPRECATED in Linux kernel version 5.10, and be + replaced with cpucp_ver What: /sys/class/habanalabs/hl/clk_max_freq_mhz Date: Jun 2019 @@ -33,6 +37,18 @@ KernelVersion: 5.1 Contact: oded.gabbay@gmail.com Description: Version of the Device's CPLD F/W +What: /sys/class/habanalabs/hl/cpucp_kernel_ver +Date: Oct 2020 +KernelVersion: 5.10 +Contact: oded.gabbay@gmail.com +Description: Version of the Linux kernel running on the device's CPU + +What: /sys/class/habanalabs/hl/cpucp_ver +Date: Oct 2020 +KernelVersion: 5.10 +Contact: oded.gabbay@gmail.com +Description: Version of the application running on the device's CPU + What: /sys/class/habanalabs/hl/device_type Date: Jan 2019 KernelVersion: 5.1 diff --git a/drivers/misc/habanalabs/common/debugfs.c b/drivers/misc/habanalabs/common/debugfs.c index 4b416f64f6ec..c27c0f94c97a 100644 --- a/drivers/misc/habanalabs/common/debugfs.c +++ b/drivers/misc/habanalabs/common/debugfs.c @@ -21,7 +21,7 @@ static struct dentry *hl_debug_root; static int hl_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, u8 i2c_reg, long *val) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; if (hl_device_disabled_or_in_reset(hdev)) @@ -29,8 +29,8 @@ static int hl_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_I2C_RD << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_I2C_RD << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.i2c_bus = i2c_bus; pkt.i2c_addr = i2c_addr; pkt.i2c_reg = i2c_reg; @@ -47,7 +47,7 @@ static int hl_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, static int hl_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, u8 i2c_reg, u32 val) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; if (hl_device_disabled_or_in_reset(hdev)) @@ -55,8 +55,8 @@ static int hl_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_I2C_WR << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_I2C_WR << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.i2c_bus = i2c_bus; pkt.i2c_addr = i2c_addr; pkt.i2c_reg = i2c_reg; @@ -73,7 +73,7 @@ static int hl_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr, static void hl_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; if (hl_device_disabled_or_in_reset(hdev)) @@ -81,8 +81,8 @@ static void hl_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state) memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_LED_SET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_LED_SET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.led_index = cpu_to_le32(led); pkt.value = cpu_to_le64(state); diff --git a/drivers/misc/habanalabs/common/device.c b/drivers/misc/habanalabs/common/device.c index dcb7f9ca7a67..6e916cc22a4c 100644 --- a/drivers/misc/habanalabs/common/device.c +++ b/drivers/misc/habanalabs/common/device.c @@ -871,7 +871,7 @@ int hl_device_reset(struct hl_device *hdev, bool hard_reset, * so this message won't be sent */ if (hl_fw_send_pci_access_msg(hdev, - ARMCP_PACKET_DISABLE_PCI_ACCESS)) + CPUCP_PACKET_DISABLE_PCI_ACCESS)) dev_warn(hdev->dev, "Failed to disable PCI access by F/W\n"); } diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c index eb66ff532c6a..f2a38e95359a 100644 --- a/drivers/misc/habanalabs/common/firmware_if.c +++ b/drivers/misc/habanalabs/common/firmware_if.c @@ -68,9 +68,9 @@ out: int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode) { - struct armcp_packet pkt = {}; + struct cpucp_packet pkt = {}; - pkt.ctl = cpu_to_le32(opcode << ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(opcode << CPUCP_PKT_CTL_OPCODE_SHIFT); return hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL); @@ -79,7 +79,7 @@ int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode) int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, u16 len, u32 timeout, long *result) { - struct armcp_packet *pkt; + struct cpucp_packet *pkt; dma_addr_t pkt_dma_addr; u32 tmp; int rc = 0; @@ -111,7 +111,7 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, } rc = hl_poll_timeout_memory(hdev, &pkt->fence, tmp, - (tmp == ARMCP_PACKET_FENCE_VAL), 1000, + (tmp == CPUCP_PACKET_FENCE_VAL), 1000, timeout, true); hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id); @@ -124,12 +124,12 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, tmp = le32_to_cpu(pkt->ctl); - rc = (tmp & ARMCP_PKT_CTL_RC_MASK) >> ARMCP_PKT_CTL_RC_SHIFT; + rc = (tmp & CPUCP_PKT_CTL_RC_MASK) >> CPUCP_PKT_CTL_RC_SHIFT; if (rc) { dev_err(hdev->dev, "F/W ERROR %d for CPU packet %d\n", rc, - (tmp & ARMCP_PKT_CTL_OPCODE_MASK) - >> ARMCP_PKT_CTL_OPCODE_SHIFT); + (tmp & CPUCP_PKT_CTL_OPCODE_MASK) + >> CPUCP_PKT_CTL_OPCODE_SHIFT); rc = -EIO; } else if (result) { *result = (long) le64_to_cpu(pkt->result); @@ -145,14 +145,14 @@ out: int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type) { - struct armcp_packet pkt; + struct cpucp_packet pkt; long result; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.value = cpu_to_le64(event_type); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), @@ -167,12 +167,12 @@ int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type) int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, size_t irq_arr_size) { - struct armcp_unmask_irq_arr_packet *pkt; + struct cpucp_unmask_irq_arr_packet *pkt; size_t total_pkt_size; long result; int rc; - total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) + + total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) + irq_arr_size; /* data should be aligned to 8 bytes in order to ArmCP to copy it */ @@ -191,8 +191,8 @@ int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0])); memcpy(&pkt->irqs, irq_arr, irq_arr_size); - pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << + CPUCP_PKT_CTL_OPCODE_SHIFT); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, total_pkt_size, 0, &result); @@ -207,19 +207,19 @@ int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, int hl_fw_test_cpu_queue(struct hl_device *hdev) { - struct armcp_packet test_pkt = {}; + struct cpucp_packet test_pkt = {}; long result; int rc; - test_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST << - ARMCP_PKT_CTL_OPCODE_SHIFT); - test_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL); + test_pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEST << + CPUCP_PKT_CTL_OPCODE_SHIFT); + test_pkt.value = cpu_to_le64(CPUCP_PACKET_FENCE_VAL); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &test_pkt, sizeof(test_pkt), 0, &result); if (!rc) { - if (result != ARMCP_PACKET_FENCE_VAL) + if (result != CPUCP_PACKET_FENCE_VAL) dev_err(hdev->dev, "CPU queue test failed (0x%08lX)\n", result); } else { @@ -251,61 +251,61 @@ void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, int hl_fw_send_heartbeat(struct hl_device *hdev) { - struct armcp_packet hb_pkt = {}; + struct cpucp_packet hb_pkt = {}; long result; int rc; - hb_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST << - ARMCP_PKT_CTL_OPCODE_SHIFT); - hb_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL); + hb_pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEST << + CPUCP_PKT_CTL_OPCODE_SHIFT); + hb_pkt.value = cpu_to_le64(CPUCP_PACKET_FENCE_VAL); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &hb_pkt, sizeof(hb_pkt), 0, &result); - if ((rc) || (result != ARMCP_PACKET_FENCE_VAL)) + if ((rc) || (result != CPUCP_PACKET_FENCE_VAL)) rc = -EIO; return rc; } -int hl_fw_armcp_info_get(struct hl_device *hdev) +int hl_fw_cpucp_info_get(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; - struct armcp_packet pkt = {}; - void *armcp_info_cpu_addr; - dma_addr_t armcp_info_dma_addr; + struct cpucp_packet pkt = {}; + void *cpucp_info_cpu_addr; + dma_addr_t cpucp_info_dma_addr; long result; int rc; - armcp_info_cpu_addr = + cpucp_info_cpu_addr = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, - sizeof(struct armcp_info), - &armcp_info_dma_addr); - if (!armcp_info_cpu_addr) { + sizeof(struct cpucp_info), + &cpucp_info_dma_addr); + if (!cpucp_info_cpu_addr) { dev_err(hdev->dev, "Failed to allocate DMA memory for ArmCP info packet\n"); return -ENOMEM; } - memset(armcp_info_cpu_addr, 0, sizeof(struct armcp_info)); + memset(cpucp_info_cpu_addr, 0, sizeof(struct cpucp_info)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_INFO_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); - pkt.addr = cpu_to_le64(armcp_info_dma_addr); - pkt.data_max_size = cpu_to_le32(sizeof(struct armcp_info)); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_INFO_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); + pkt.addr = cpu_to_le64(cpucp_info_dma_addr); + pkt.data_max_size = cpu_to_le32(sizeof(struct cpucp_info)); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), - HL_ARMCP_INFO_TIMEOUT_USEC, &result); + HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, "Failed to handle ArmCP info pkt, error %d\n", rc); goto out; } - memcpy(&prop->armcp_info, armcp_info_cpu_addr, - sizeof(prop->armcp_info)); + memcpy(&prop->cpucp_info, cpucp_info_cpu_addr, + sizeof(prop->cpucp_info)); - rc = hl_build_hwmon_channel_info(hdev, prop->armcp_info.sensors); + rc = hl_build_hwmon_channel_info(hdev, prop->cpucp_info.sensors); if (rc) { dev_err(hdev->dev, "Failed to build hwmon channel info, error %d\n", rc); @@ -315,14 +315,14 @@ int hl_fw_armcp_info_get(struct hl_device *hdev) out: hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, - sizeof(struct armcp_info), armcp_info_cpu_addr); + sizeof(struct cpucp_info), cpucp_info_cpu_addr); return rc; } int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size) { - struct armcp_packet pkt = {}; + struct cpucp_packet pkt = {}; void *eeprom_info_cpu_addr; dma_addr_t eeprom_info_dma_addr; long result; @@ -339,13 +339,13 @@ int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size) memset(eeprom_info_cpu_addr, 0, max_size); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_EEPROM_DATA_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_EEPROM_DATA_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.addr = cpu_to_le64(eeprom_info_dma_addr); pkt.data_max_size = cpu_to_le32(max_size); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), - HL_ARMCP_EEPROM_TIMEOUT_USEC, &result); + HL_CPUCP_EEPROM_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, @@ -363,20 +363,20 @@ out: return rc; } -int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, +int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, struct hl_info_pci_counters *counters) { - struct armcp_packet pkt = {}; + struct cpucp_packet pkt = {}; long result; int rc; - pkt.ctl = cpu_to_le32(ARMCP_PACKET_PCIE_THROUGHPUT_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_PCIE_THROUGHPUT_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); /* Fetch PCI rx counter */ - pkt.index = cpu_to_le32(armcp_pcie_throughput_rx); + pkt.index = cpu_to_le32(cpucp_pcie_throughput_rx); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), - HL_ARMCP_INFO_TIMEOUT_USEC, &result); + HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, "Failed to handle ArmCP PCI info pkt, error %d\n", rc); @@ -385,9 +385,9 @@ int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, counters->rx_throughput = result; /* Fetch PCI tx counter */ - pkt.index = cpu_to_le32(armcp_pcie_throughput_tx); + pkt.index = cpu_to_le32(cpucp_pcie_throughput_tx); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), - HL_ARMCP_INFO_TIMEOUT_USEC, &result); + HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, "Failed to handle ArmCP PCI info pkt, error %d\n", rc); @@ -396,11 +396,11 @@ int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, counters->tx_throughput = result; /* Fetch PCI replay counter */ - pkt.ctl = cpu_to_le32(ARMCP_PACKET_PCIE_REPLAY_CNT_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_PCIE_REPLAY_CNT_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), - HL_ARMCP_INFO_TIMEOUT_USEC, &result); + HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, "Failed to handle ArmCP PCI info pkt, error %d\n", rc); @@ -411,21 +411,20 @@ int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, return rc; } -int hl_fw_armcp_total_energy_get(struct hl_device *hdev, - u64 *total_energy) +int hl_fw_cpucp_total_energy_get(struct hl_device *hdev, u64 *total_energy) { - struct armcp_packet pkt = {}; + struct cpucp_packet pkt = {}; long result; int rc; - pkt.ctl = cpu_to_le32(ARMCP_PACKET_TOTAL_ENERGY_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_TOTAL_ENERGY_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), - HL_ARMCP_INFO_TIMEOUT_USEC, &result); + HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, - "Failed to handle ArmCP total energy pkt, error %d\n", + "Failed to handle CpuCP total energy pkt, error %d\n", rc); return rc; } diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 6577a73e3227..6912f88a4b01 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -8,7 +8,7 @@ #ifndef HABANALABSP_H_ #define HABANALABSP_H_ -#include "../include/common/armcp_if.h" +#include "../include/common/cpucp_if.h" #include "../include/common/qman_if.h" #include @@ -34,8 +34,8 @@ #define HL_PLL_LOW_JOB_FREQ_USEC 5000000 /* 5 s */ -#define HL_ARMCP_INFO_TIMEOUT_USEC 10000000 /* 10s */ -#define HL_ARMCP_EEPROM_TIMEOUT_USEC 10000000 /* 10s */ +#define HL_CPUCP_INFO_TIMEOUT_USEC 10000000 /* 10s */ +#define HL_CPUCP_EEPROM_TIMEOUT_USEC 10000000 /* 10s */ #define HL_PCI_ELBI_TIMEOUT_MSEC 10 /* 10ms */ @@ -250,7 +250,7 @@ struct hl_mmu_properties { /** * struct asic_fixed_properties - ASIC specific immutable properties. * @hw_queues_props: H/W queues properties. - * @armcp_info: received various information from ArmCP regarding the H/W, e.g. + * @cpucp_info: received various information from CPU-CP regarding the H/W, e.g. * available sensors. * @uboot_ver: F/W U-boot version. * @preboot_ver: F/W Preboot version. @@ -301,7 +301,7 @@ struct hl_mmu_properties { */ struct asic_fixed_properties { struct hw_queue_properties *hw_queues_props; - struct armcp_info armcp_info; + struct cpucp_info cpucp_info; char uboot_ver[VERSION_MAX_LEN]; char preboot_ver[VERSION_MAX_LEN]; struct hl_mmu_properties dmmu; @@ -1588,7 +1588,7 @@ struct hl_device { u64 clock_gating_mask; atomic_t in_reset; enum hl_pll_frequency curr_pll_profile; - enum armcp_card_types card_type; + enum cpucp_card_types card_type; int cs_active_cnt; u32 major; u32 high_pll; @@ -1776,7 +1776,7 @@ int hl_device_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq); uint32_t hl_device_utilization(struct hl_device *hdev, uint32_t period_ms); int hl_build_hwmon_channel_info(struct hl_device *hdev, - struct armcp_sensor *sensors_arr); + struct cpucp_sensor *sensors_arr); int hl_sysfs_init(struct hl_device *hdev); void hl_sysfs_fini(struct hl_device *hdev); @@ -1848,11 +1848,11 @@ void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr); int hl_fw_send_heartbeat(struct hl_device *hdev); -int hl_fw_armcp_info_get(struct hl_device *hdev); +int hl_fw_cpucp_info_get(struct hl_device *hdev); int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size); -int hl_fw_armcp_pci_counters_get(struct hl_device *hdev, +int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, struct hl_info_pci_counters *counters); -int hl_fw_armcp_total_energy_get(struct hl_device *hdev, +int hl_fw_cpucp_total_energy_get(struct hl_device *hdev, u64 *total_energy); int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, diff --git a/drivers/misc/habanalabs/common/habanalabs_ioctl.c b/drivers/misc/habanalabs/common/habanalabs_ioctl.c index 18ee14b4b0e1..07317ea49129 100644 --- a/drivers/misc/habanalabs/common/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/common/habanalabs_ioctl.c @@ -65,14 +65,14 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) hw_ip.dram_enabled = 1; hw_ip.num_of_events = prop->num_of_events; - memcpy(hw_ip.armcp_version, prop->armcp_info.armcp_version, + memcpy(hw_ip.cpucp_version, prop->cpucp_info.cpucp_version, min(VERSION_MAX_LEN, HL_INFO_VERSION_MAX_LEN)); - memcpy(hw_ip.card_name, prop->armcp_info.card_name, + memcpy(hw_ip.card_name, prop->cpucp_info.card_name, min(CARD_NAME_MAX_LEN, HL_INFO_CARD_NAME_MAX_LEN)); - hw_ip.armcp_cpld_version = le32_to_cpu(prop->armcp_info.cpld_version); - hw_ip.module_id = le32_to_cpu(prop->armcp_info.card_location); + hw_ip.cpld_version = le32_to_cpu(prop->cpucp_info.cpld_version); + hw_ip.module_id = le32_to_cpu(prop->cpucp_info.card_location); hw_ip.psoc_pci_pll_nr = prop->psoc_pci_pll_nr; hw_ip.psoc_pci_pll_nf = prop->psoc_pci_pll_nf; @@ -288,7 +288,7 @@ static int pci_counters_info(struct hl_fpriv *hpriv, struct hl_info_args *args) if ((!max_size) || (!out)) return -EINVAL; - rc = hl_fw_armcp_pci_counters_get(hdev, &pci_counters); + rc = hl_fw_cpucp_pci_counters_get(hdev, &pci_counters); if (rc) return rc; @@ -369,7 +369,7 @@ static int total_energy_consumption_info(struct hl_fpriv *hpriv, if ((!max_size) || (!out)) return -EINVAL; - rc = hl_fw_armcp_total_energy_get(hdev, + rc = hl_fw_cpucp_total_energy_get(hdev, &total_energy.total_energy_consumption); if (rc) return rc; diff --git a/drivers/misc/habanalabs/common/hwmon.c b/drivers/misc/habanalabs/common/hwmon.c index b997336fa75f..2ac29cb2fe61 100644 --- a/drivers/misc/habanalabs/common/hwmon.c +++ b/drivers/misc/habanalabs/common/hwmon.c @@ -13,7 +13,7 @@ #define HWMON_NR_SENSOR_TYPES (hwmon_pwm + 1) int hl_build_hwmon_channel_info(struct hl_device *hdev, - struct armcp_sensor *sensors_arr) + struct cpucp_sensor *sensors_arr) { u32 counts[HWMON_NR_SENSOR_TYPES] = {0}; u32 *sensors_by_type[HWMON_NR_SENSOR_TYPES] = {NULL}; @@ -24,7 +24,7 @@ int hl_build_hwmon_channel_info(struct hl_device *hdev, enum hwmon_sensor_types type; int rc, i, j; - for (i = 0 ; i < ARMCP_MAX_SENSORS ; i++) { + for (i = 0 ; i < CPUCP_MAX_SENSORS ; i++) { type = le32_to_cpu(sensors_arr[i].type); if ((type == 0) && (sensors_arr[i].flags == 0)) @@ -311,13 +311,13 @@ static const struct hwmon_ops hl_hwmon_ops = { int hl_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr, long *value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEMPERATURE_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEMPERATURE_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); @@ -337,13 +337,13 @@ int hl_get_temperature(struct hl_device *hdev, int hl_set_temperature(struct hl_device *hdev, int sensor_index, u32 attr, long value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEMPERATURE_SET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEMPERATURE_SET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); pkt.value = __cpu_to_le64(value); @@ -362,13 +362,13 @@ int hl_set_temperature(struct hl_device *hdev, int hl_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr, long *value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_VOLTAGE_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_VOLTAGE_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); @@ -388,13 +388,13 @@ int hl_get_voltage(struct hl_device *hdev, int hl_get_current(struct hl_device *hdev, int sensor_index, u32 attr, long *value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_CURRENT_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_CURRENT_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); @@ -414,13 +414,13 @@ int hl_get_current(struct hl_device *hdev, int hl_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr, long *value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_FAN_SPEED_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_FAN_SPEED_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); @@ -440,13 +440,13 @@ int hl_get_fan_speed(struct hl_device *hdev, int hl_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, long *value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_PWM_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_PWM_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); @@ -466,13 +466,13 @@ int hl_get_pwm_info(struct hl_device *hdev, void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, long value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_PWM_SET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_PWM_SET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); pkt.value = cpu_to_le64(value); @@ -489,13 +489,13 @@ void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, int hl_set_voltage(struct hl_device *hdev, int sensor_index, u32 attr, long value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_VOLTAGE_SET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_VOLTAGE_SET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); pkt.value = __cpu_to_le64(value); @@ -514,13 +514,13 @@ int hl_set_voltage(struct hl_device *hdev, int hl_set_current(struct hl_device *hdev, int sensor_index, u32 attr, long value) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_CURRENT_SET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_CURRENT_SET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.sensor_index = __cpu_to_le16(sensor_index); pkt.type = __cpu_to_le16(attr); pkt.value = __cpu_to_le64(value); @@ -549,7 +549,7 @@ int hl_hwmon_init(struct hl_device *hdev) hdev->hl_chip_info->ops = &hl_hwmon_ops; hdev->hwmon_dev = hwmon_device_register_with_info(dev, - prop->armcp_info.card_name, hdev, + prop->cpucp_info.card_name, hdev, hdev->hl_chip_info, NULL); if (IS_ERR(hdev->hwmon_dev)) { rc = PTR_ERR(hdev->hwmon_dev); diff --git a/drivers/misc/habanalabs/common/irq.c b/drivers/misc/habanalabs/common/irq.c index c8db717023f5..d20e40a53d70 100644 --- a/drivers/misc/habanalabs/common/irq.c +++ b/drivers/misc/habanalabs/common/irq.c @@ -11,7 +11,7 @@ /** * struct hl_eqe_work - This structure is used to schedule work of EQ - * entry and armcp_reset event + * entry and cpucp_reset event * * @eq_work: workqueue object to run when EQ entry is received * @hdev: pointer to device structure diff --git a/drivers/misc/habanalabs/common/sysfs.c b/drivers/misc/habanalabs/common/sysfs.c index 5ae484cc84cd..3ceae87016b1 100644 --- a/drivers/misc/habanalabs/common/sysfs.c +++ b/drivers/misc/habanalabs/common/sysfs.c @@ -11,18 +11,18 @@ long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr) { - struct armcp_packet pkt; + struct cpucp_packet pkt; long result; int rc; memset(&pkt, 0, sizeof(pkt)); if (curr) - pkt.ctl = cpu_to_le32(ARMCP_PACKET_FREQUENCY_CURR_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_FREQUENCY_CURR_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); else - pkt.ctl = cpu_to_le32(ARMCP_PACKET_FREQUENCY_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_FREQUENCY_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.pll_index = cpu_to_le32(pll_index); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), @@ -40,13 +40,13 @@ long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr) void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_FREQUENCY_SET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_FREQUENCY_SET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.pll_index = cpu_to_le32(pll_index); pkt.value = cpu_to_le64(freq); @@ -61,14 +61,14 @@ void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq) u64 hl_get_max_power(struct hl_device *hdev) { - struct armcp_packet pkt; + struct cpucp_packet pkt; long result; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_MAX_POWER_GET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_MAX_POWER_GET << + CPUCP_PKT_CTL_OPCODE_SHIFT); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, &result); @@ -83,13 +83,13 @@ u64 hl_get_max_power(struct hl_device *hdev) void hl_set_max_power(struct hl_device *hdev) { - struct armcp_packet pkt; + struct cpucp_packet pkt; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_MAX_POWER_SET << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_MAX_POWER_SET << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.value = cpu_to_le64(hdev->max_power); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), @@ -112,7 +112,7 @@ static ssize_t armcp_kernel_ver_show(struct device *dev, { struct hl_device *hdev = dev_get_drvdata(dev); - return sprintf(buf, "%s", hdev->asic_prop.armcp_info.kernel_version); + return sprintf(buf, "%s", hdev->asic_prop.cpucp_info.kernel_version); } static ssize_t armcp_ver_show(struct device *dev, struct device_attribute *attr, @@ -120,7 +120,7 @@ static ssize_t armcp_ver_show(struct device *dev, struct device_attribute *attr, { struct hl_device *hdev = dev_get_drvdata(dev); - return sprintf(buf, "%s\n", hdev->asic_prop.armcp_info.armcp_version); + return sprintf(buf, "%s\n", hdev->asic_prop.cpucp_info.cpucp_version); } static ssize_t cpld_ver_show(struct device *dev, struct device_attribute *attr, @@ -129,7 +129,23 @@ static ssize_t cpld_ver_show(struct device *dev, struct device_attribute *attr, struct hl_device *hdev = dev_get_drvdata(dev); return sprintf(buf, "0x%08x\n", - hdev->asic_prop.armcp_info.cpld_version); + hdev->asic_prop.cpucp_info.cpld_version); +} + +static ssize_t cpucp_kernel_ver_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s", hdev->asic_prop.cpucp_info.kernel_version); +} + +static ssize_t cpucp_ver_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", hdev->asic_prop.cpucp_info.cpucp_version); } static ssize_t infineon_ver_show(struct device *dev, @@ -138,7 +154,7 @@ static ssize_t infineon_ver_show(struct device *dev, struct hl_device *hdev = dev_get_drvdata(dev); return sprintf(buf, "0x%04x\n", - hdev->asic_prop.armcp_info.infineon_version); + hdev->asic_prop.cpucp_info.infineon_version); } static ssize_t fuse_ver_show(struct device *dev, struct device_attribute *attr, @@ -146,7 +162,7 @@ static ssize_t fuse_ver_show(struct device *dev, struct device_attribute *attr, { struct hl_device *hdev = dev_get_drvdata(dev); - return sprintf(buf, "%s\n", hdev->asic_prop.armcp_info.fuse_version); + return sprintf(buf, "%s\n", hdev->asic_prop.cpucp_info.fuse_version); } static ssize_t thermal_ver_show(struct device *dev, @@ -154,7 +170,7 @@ static ssize_t thermal_ver_show(struct device *dev, { struct hl_device *hdev = dev_get_drvdata(dev); - return sprintf(buf, "%s", hdev->asic_prop.armcp_info.thermal_version); + return sprintf(buf, "%s", hdev->asic_prop.cpucp_info.thermal_version); } static ssize_t preboot_btl_ver_show(struct device *dev, @@ -356,6 +372,8 @@ out: static DEVICE_ATTR_RO(armcp_kernel_ver); static DEVICE_ATTR_RO(armcp_ver); static DEVICE_ATTR_RO(cpld_ver); +static DEVICE_ATTR_RO(cpucp_kernel_ver); +static DEVICE_ATTR_RO(cpucp_ver); static DEVICE_ATTR_RO(device_type); static DEVICE_ATTR_RO(fuse_ver); static DEVICE_ATTR_WO(hard_reset); @@ -380,6 +398,8 @@ static struct attribute *hl_dev_attrs[] = { &dev_attr_armcp_kernel_ver.attr, &dev_attr_armcp_ver.attr, &dev_attr_cpld_ver.attr, + &dev_attr_cpucp_kernel_ver.attr, + &dev_attr_cpucp_ver.attr, &dev_attr_device_type.attr, &dev_attr_fuse_ver.attr, &dev_attr_hard_reset.attr, diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 4a4327d9cbbf..076a7697f85d 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -359,7 +359,7 @@ static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel, u32 tpc_id); static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev); -static int gaudi_armcp_info_get(struct hl_device *hdev); +static int gaudi_cpucp_info_get(struct hl_device *hdev); static void gaudi_disable_clock_gating(struct hl_device *hdev); static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid); @@ -465,7 +465,7 @@ static int gaudi_get_fixed_properties(struct hl_device *hdev) prop->pcie_dbi_base_address = mmPCIE_DBI_BASE; prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; - strncpy(prop->armcp_info.card_name, GAUDI_DEFAULT_CARD_NAME, + strncpy(prop->cpucp_info.card_name, GAUDI_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN); prop->max_pending_cs = GAUDI_MAX_PENDING_CS; @@ -786,13 +786,13 @@ static int gaudi_late_init(struct hl_device *hdev) struct gaudi_device *gaudi = hdev->asic_specific; int rc; - rc = gaudi->armcp_info_get(hdev); + rc = gaudi->cpucp_info_get(hdev); if (rc) { - dev_err(hdev->dev, "Failed to get armcp info\n"); + dev_err(hdev->dev, "Failed to get cpucp info\n"); return rc; } - rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS); if (rc) { dev_err(hdev->dev, "Failed to enable PCI access from CPU\n"); return rc; @@ -817,7 +817,7 @@ static int gaudi_late_init(struct hl_device *hdev) return 0; disable_pci_access: - hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS); return rc; } @@ -987,7 +987,7 @@ static int gaudi_sw_init(struct hl_device *hdev) } } - gaudi->armcp_info_get = gaudi_armcp_info_get; + gaudi->cpucp_info_get = gaudi_cpucp_info_get; gaudi->max_freq_value = GAUDI_MAX_CLK_FREQ; @@ -3078,7 +3078,7 @@ static int gaudi_suspend(struct hl_device *hdev) { int rc; - rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS); if (rc) dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); @@ -6053,7 +6053,7 @@ static int gaudi_send_heartbeat(struct hl_device *hdev) return hl_fw_send_heartbeat(hdev); } -static int gaudi_armcp_info_get(struct hl_device *hdev) +static int gaudi_cpucp_info_get(struct hl_device *hdev) { struct gaudi_device *gaudi = hdev->asic_specific; struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -6062,19 +6062,19 @@ static int gaudi_armcp_info_get(struct hl_device *hdev) if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) return 0; - rc = hl_fw_armcp_info_get(hdev); + rc = hl_fw_cpucp_info_get(hdev); if (rc) return rc; - if (!strlen(prop->armcp_info.card_name)) - strncpy(prop->armcp_info.card_name, GAUDI_DEFAULT_CARD_NAME, + if (!strlen(prop->cpucp_info.card_name)) + strncpy(prop->cpucp_info.card_name, GAUDI_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN); - hdev->card_type = le32_to_cpu(hdev->asic_prop.armcp_info.card_type); + hdev->card_type = le32_to_cpu(hdev->asic_prop.cpucp_info.card_type); - if (hdev->card_type == armcp_card_type_pci) + if (hdev->card_type == cpucp_card_type_pci) prop->max_power_default = MAX_POWER_DEFAULT_PCI; - else if (hdev->card_type == armcp_card_type_pmc) + else if (hdev->card_type == cpucp_card_type_pmc) prop->max_power_default = MAX_POWER_DEFAULT_PMC; hdev->max_power = prop->max_power_default; diff --git a/drivers/misc/habanalabs/gaudi/gaudiP.h b/drivers/misc/habanalabs/gaudi/gaudiP.h index 1368f6298c80..b86eb98b145c 100644 --- a/drivers/misc/habanalabs/gaudi/gaudiP.h +++ b/drivers/misc/habanalabs/gaudi/gaudiP.h @@ -216,7 +216,7 @@ struct gaudi_internal_qman_info { /** * struct gaudi_device - ASIC specific manage structure. - * @armcp_info_get: get information on device from ArmCP + * @cpucp_info_get: get information on device from CPU-CP * @hw_queues_lock: protects the H/W queues from concurrent access. * @clk_gate_mutex: protects code areas that require clock gating to be disabled * temporarily @@ -239,7 +239,7 @@ struct gaudi_internal_qman_info { * 8-bit value so use u8. */ struct gaudi_device { - int (*armcp_info_get)(struct hl_device *hdev); + int (*cpucp_info_get)(struct hl_device *hdev); /* TODO: remove hw_queues_lock after moving to scheduler code */ spinlock_t hw_queues_lock; diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 5fb3565c80c5..c41f2917863b 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -449,7 +449,7 @@ int goya_get_fixed_properties(struct hl_device *hdev) prop->pcie_dbi_base_address = mmPCIE_DBI_BASE; prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; - strncpy(prop->armcp_info.card_name, GOYA_DEFAULT_CARD_NAME, + strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN); prop->max_pending_cs = GOYA_MAX_PENDING_CS; @@ -727,9 +727,9 @@ int goya_late_init(struct hl_device *hdev) if (rc) return rc; - rc = goya_armcp_info_get(hdev); + rc = goya_cpucp_info_get(hdev); if (rc) { - dev_err(hdev->dev, "Failed to get armcp info %d\n", rc); + dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc); return rc; } @@ -739,7 +739,7 @@ int goya_late_init(struct hl_device *hdev) */ WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); - rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS); if (rc) { dev_err(hdev->dev, "Failed to enable PCI access from CPU %d\n", rc); @@ -2648,7 +2648,7 @@ int goya_suspend(struct hl_device *hdev) { int rc; - rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS); if (rc) dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); @@ -4500,14 +4500,14 @@ static void goya_print_irq_info(struct hl_device *hdev, u16 event_type, static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr, size_t irq_arr_size) { - struct armcp_unmask_irq_arr_packet *pkt; + struct cpucp_unmask_irq_arr_packet *pkt; size_t total_pkt_size; long result; int rc; int irq_num_entries, irq_arr_index; __le32 *goya_irq_arr; - total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) + + total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) + irq_arr_size; /* data should be aligned to 8 bytes in order to ArmCP to copy it */ @@ -4534,8 +4534,8 @@ static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr, goya_irq_arr[irq_arr_index] = cpu_to_le32(irq_arr[irq_arr_index]); - pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << + CPUCP_PKT_CTL_OPCODE_SHIFT); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, total_pkt_size, 0, &result); @@ -4560,14 +4560,14 @@ static int goya_soft_reset_late_init(struct hl_device *hdev) static int goya_unmask_irq(struct hl_device *hdev, u16 event_type) { - struct armcp_packet pkt; + struct cpucp_packet pkt; long result; int rc; memset(&pkt, 0, sizeof(pkt)); - pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ << - ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ << + CPUCP_PKT_CTL_OPCODE_SHIFT); pkt.value = cpu_to_le64(event_type); rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), @@ -5103,7 +5103,7 @@ int goya_send_heartbeat(struct hl_device *hdev) return hl_fw_send_heartbeat(hdev); } -int goya_armcp_info_get(struct hl_device *hdev) +int goya_cpucp_info_get(struct hl_device *hdev) { struct goya_device *goya = hdev->asic_specific; struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -5113,11 +5113,11 @@ int goya_armcp_info_get(struct hl_device *hdev) if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) return 0; - rc = hl_fw_armcp_info_get(hdev); + rc = hl_fw_cpucp_info_get(hdev); if (rc) return rc; - dram_size = le64_to_cpu(prop->armcp_info.dram_size); + dram_size = le64_to_cpu(prop->cpucp_info.dram_size); if (dram_size) { if ((!is_power_of_2(dram_size)) || (dram_size < DRAM_PHYS_DEFAULT_SIZE)) { @@ -5131,8 +5131,8 @@ int goya_armcp_info_get(struct hl_device *hdev) prop->dram_end_address = prop->dram_base_address + dram_size; } - if (!strlen(prop->armcp_info.card_name)) - strncpy(prop->armcp_info.card_name, GOYA_DEFAULT_CARD_NAME, + if (!strlen(prop->cpucp_info.card_name)) + strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN); return 0; diff --git a/drivers/misc/habanalabs/goya/goyaP.h b/drivers/misc/habanalabs/goya/goyaP.h index bb7474ee9784..09b4006d4dc3 100644 --- a/drivers/misc/habanalabs/goya/goyaP.h +++ b/drivers/misc/habanalabs/goya/goyaP.h @@ -207,7 +207,7 @@ void goya_set_max_power(struct hl_device *hdev, u64 value); void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq); void goya_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_attr_grp); -int goya_armcp_info_get(struct hl_device *hdev); +int goya_cpucp_info_get(struct hl_device *hdev); int goya_debug_coresight(struct hl_device *hdev, void *data); void goya_halt_coresight(struct hl_device *hdev); diff --git a/drivers/misc/habanalabs/include/common/armcp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h similarity index 63% rename from drivers/misc/habanalabs/include/common/armcp_if.h rename to drivers/misc/habanalabs/include/common/cpucp_if.h index 4d78898524e9..1e8480e978e2 100644 --- a/drivers/misc/habanalabs/include/common/armcp_if.h +++ b/drivers/misc/habanalabs/include/common/cpucp_if.h @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2016-2020 HabanaLabs, Ltd. + * Copyright 2020 HabanaLabs, Ltd. * All Rights Reserved. * */ -#ifndef ARMCP_IF_H -#define ARMCP_IF_H +#ifndef CPUCP_IF_H +#define CPUCP_IF_H #include @@ -50,16 +50,16 @@ enum pq_init_status { }; /* - * ArmCP Primary Queue Packets + * CpuCP Primary Queue Packets * * During normal operation, the host's kernel driver needs to send various - * messages to ArmCP, usually either to SET some value into a H/W periphery or + * messages to CpuCP, usually either to SET some value into a H/W periphery or * to GET the current value of some H/W periphery. For example, SET the * frequency of MME/TPC and GET the value of the thermal sensor. * * These messages can be initiated either by the User application or by the * host's driver itself, e.g. power management code. In either case, the - * communication from the host's driver to ArmCP will *always* be in + * communication from the host's driver to CpuCP will *always* be in * synchronous mode, meaning that the host will send a single message and poll * until the message was acknowledged and the results are ready (if results are * needed). @@ -73,21 +73,20 @@ enum pq_init_status { * * The message, inputs/outputs (if relevant) and fence object will be located * on the device DDR at an address that will be determined by the host's driver. - * During device initialization phase, the host will pass to ArmCP that address. + * During device initialization phase, the host will pass to CpuCP that address. * Most of the message types will contain inputs/outputs inside the message * itself. The common part of each message will contain the opcode of the * message (its type) and a field representing a fence object. * - * When the host's driver wishes to send a message to ArmCP, it will write the - * message contents to the device DDR, clear the fence object and then write the - * value 484 to the mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR register to issue - * the 484 interrupt-id to the ARM core. + * When the host's driver wishes to send a message to CPU CP, it will write the + * message contents to the device DDR, clear the fence object and then write to + * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. * - * Upon receiving the 484 interrupt-id, ArmCP will read the message from the - * DDR. In case the message is a SET operation, ArmCP will first perform the + * Upon receiving the interrupt (#121), CpuCP will read the message from the + * DDR. In case the message is a SET operation, CpuCP will first perform the * operation and then write to the fence object on the device DDR. In case the - * message is a GET operation, ArmCP will first fill the results section on the - * device DDR and then write to the fence object. If an error occurred, ArmCP + * message is a GET operation, CpuCP will first fill the results section on the + * device DDR and then write to the fence object. If an error occurred, CpuCP * will fill the rc field with the right error code. * * In the meantime, the host's driver will poll on the fence object. Once the @@ -96,167 +95,167 @@ enum pq_init_status { * driver. * * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 - * so the value being put by the host's driver matches the value read by ArmCP + * so the value being put by the host's driver matches the value read by CpuCP * * Non-QMAN packets should be limited to values 1 through (2^8 - 1) * * Detailed description: * - * ARMCP_PACKET_DISABLE_PCI_ACCESS - + * CPUCP_PACKET_DISABLE_PCI_ACCESS - * After receiving this packet the embedded CPU must NOT issue PCI * transactions (read/write) towards the Host CPU. This also include * sending MSI-X interrupts. * This packet is usually sent before the device is moved to D3Hot state. * - * ARMCP_PACKET_ENABLE_PCI_ACCESS - + * CPUCP_PACKET_ENABLE_PCI_ACCESS - * After receiving this packet the embedded CPU is allowed to issue PCI * transactions towards the Host CPU, including sending MSI-X interrupts. * This packet is usually send after the device is moved to D0 state. * - * ARMCP_PACKET_TEMPERATURE_GET - + * CPUCP_PACKET_TEMPERATURE_GET - * Fetch the current temperature / Max / Max Hyst / Critical / * Critical Hyst of a specified thermal sensor. The packet's * arguments specify the desired sensor and the field to get. * - * ARMCP_PACKET_VOLTAGE_GET - + * CPUCP_PACKET_VOLTAGE_GET - * Fetch the voltage / Max / Min of a specified sensor. The packet's * arguments specify the sensor and type. * - * ARMCP_PACKET_CURRENT_GET - + * CPUCP_PACKET_CURRENT_GET - * Fetch the current / Max / Min of a specified sensor. The packet's * arguments specify the sensor and type. * - * ARMCP_PACKET_FAN_SPEED_GET - + * CPUCP_PACKET_FAN_SPEED_GET - * Fetch the speed / Max / Min of a specified fan. The packet's * arguments specify the sensor and type. * - * ARMCP_PACKET_PWM_GET - + * CPUCP_PACKET_PWM_GET - * Fetch the pwm value / mode of a specified pwm. The packet's * arguments specify the sensor and type. * - * ARMCP_PACKET_PWM_SET - + * CPUCP_PACKET_PWM_SET - * Set the pwm value / mode of a specified pwm. The packet's * arguments specify the sensor, type and value. * - * ARMCP_PACKET_FREQUENCY_SET - + * CPUCP_PACKET_FREQUENCY_SET - * Set the frequency of a specified PLL. The packet's arguments specify * the PLL and the desired frequency. The actual frequency in the device * might differ from the requested frequency. * - * ARMCP_PACKET_FREQUENCY_GET - + * CPUCP_PACKET_FREQUENCY_GET - * Fetch the frequency of a specified PLL. The packet's arguments specify * the PLL. * - * ARMCP_PACKET_LED_SET - + * CPUCP_PACKET_LED_SET - * Set the state of a specified led. The packet's arguments * specify the led and the desired state. * - * ARMCP_PACKET_I2C_WR - + * CPUCP_PACKET_I2C_WR - * Write 32-bit value to I2C device. The packet's arguments specify the * I2C bus, address and value. * - * ARMCP_PACKET_I2C_RD - + * CPUCP_PACKET_I2C_RD - * Read 32-bit value from I2C device. The packet's arguments specify the * I2C bus and address. * - * ARMCP_PACKET_INFO_GET - + * CPUCP_PACKET_INFO_GET - * Fetch information from the device as specified in the packet's - * structure. The host's driver passes the max size it allows the ArmCP to + * structure. The host's driver passes the max size it allows the CpuCP to * write to the structure, to prevent data corruption in case of * mismatched driver/FW versions. * - * ARMCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed + * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed * - * ARMCP_PACKET_UNMASK_RAZWI_IRQ - + * CPUCP_PACKET_UNMASK_RAZWI_IRQ - * Unmask the given IRQ. The IRQ number is specified in the value field. * The packet is sent after receiving an interrupt and printing its * relevant information. * - * ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - + * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - * Unmask the given IRQs. The IRQs numbers are specified in an array right - * after the armcp_packet structure, where its first element is the array + * after the cpucp_packet structure, where its first element is the array * length. The packet is sent after a soft reset was done in order to * handle any interrupts that were sent during the reset process. * - * ARMCP_PACKET_TEST - - * Test packet for ArmCP connectivity. The CPU will put the fence value + * CPUCP_PACKET_TEST - + * Test packet for CpuCP connectivity. The CPU will put the fence value * in the result field. * - * ARMCP_PACKET_FREQUENCY_CURR_GET - + * CPUCP_PACKET_FREQUENCY_CURR_GET - * Fetch the current frequency of a specified PLL. The packet's arguments * specify the PLL. * - * ARMCP_PACKET_MAX_POWER_GET - + * CPUCP_PACKET_MAX_POWER_GET - * Fetch the maximal power of the device. * - * ARMCP_PACKET_MAX_POWER_SET - + * CPUCP_PACKET_MAX_POWER_SET - * Set the maximal power of the device. The packet's arguments specify * the power. * - * ARMCP_PACKET_EEPROM_DATA_GET - - * Get EEPROM data from the ArmCP kernel. The buffer is specified in the + * CPUCP_PACKET_EEPROM_DATA_GET - + * Get EEPROM data from the CpuCP kernel. The buffer is specified in the * addr field. The CPU will put the returned data size in the result * field. In addition, the host's driver passes the max size it allows the - * ArmCP to write to the structure, to prevent data corruption in case of + * CpuCP to write to the structure, to prevent data corruption in case of * mismatched driver/FW versions. * - * ARMCP_PACKET_TEMPERATURE_SET - + * CPUCP_PACKET_TEMPERATURE_SET - * Set the value of the offset property of a specified thermal sensor. * The packet's arguments specify the desired sensor and the field to * set. * - * ARMCP_PACKET_VOLTAGE_SET - + * CPUCP_PACKET_VOLTAGE_SET - * Trigger the reset_history property of a specified voltage sensor. * The packet's arguments specify the desired sensor and the field to * set. * - * ARMCP_PACKET_CURRENT_SET - + * CPUCP_PACKET_CURRENT_SET - * Trigger the reset_history property of a specified current sensor. * The packet's arguments specify the desired sensor and the field to * set. */ -enum armcp_packet_id { - ARMCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ - ARMCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ - ARMCP_PACKET_TEMPERATURE_GET, /* sysfs */ - ARMCP_PACKET_VOLTAGE_GET, /* sysfs */ - ARMCP_PACKET_CURRENT_GET, /* sysfs */ - ARMCP_PACKET_FAN_SPEED_GET, /* sysfs */ - ARMCP_PACKET_PWM_GET, /* sysfs */ - ARMCP_PACKET_PWM_SET, /* sysfs */ - ARMCP_PACKET_FREQUENCY_SET, /* sysfs */ - ARMCP_PACKET_FREQUENCY_GET, /* sysfs */ - ARMCP_PACKET_LED_SET, /* debugfs */ - ARMCP_PACKET_I2C_WR, /* debugfs */ - ARMCP_PACKET_I2C_RD, /* debugfs */ - ARMCP_PACKET_INFO_GET, /* IOCTL */ - ARMCP_PACKET_FLASH_PROGRAM_REMOVED, - ARMCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ - ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ - ARMCP_PACKET_TEST, /* internal */ - ARMCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ - ARMCP_PACKET_MAX_POWER_GET, /* sysfs */ - ARMCP_PACKET_MAX_POWER_SET, /* sysfs */ - ARMCP_PACKET_EEPROM_DATA_GET, /* sysfs */ - ARMCP_RESERVED, - ARMCP_PACKET_TEMPERATURE_SET, /* sysfs */ - ARMCP_PACKET_VOLTAGE_SET, /* sysfs */ - ARMCP_PACKET_CURRENT_SET, /* sysfs */ - ARMCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ - ARMCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ - ARMCP_PACKET_TOTAL_ENERGY_GET, /* internal */ +enum cpucp_packet_id { + CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ + CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ + CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ + CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ + CPUCP_PACKET_CURRENT_GET, /* sysfs */ + CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ + CPUCP_PACKET_PWM_GET, /* sysfs */ + CPUCP_PACKET_PWM_SET, /* sysfs */ + CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ + CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ + CPUCP_PACKET_LED_SET, /* debugfs */ + CPUCP_PACKET_I2C_WR, /* debugfs */ + CPUCP_PACKET_I2C_RD, /* debugfs */ + CPUCP_PACKET_INFO_GET, /* IOCTL */ + CPUCP_PACKET_FLASH_PROGRAM_REMOVED, + CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ + CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ + CPUCP_PACKET_TEST, /* internal */ + CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ + CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ + CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ + CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ + CPUCP_RESERVED, + CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ + CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ + CPUCP_PACKET_CURRENT_SET, /* sysfs */ + CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ + CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ + CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ }; -#define ARMCP_PACKET_FENCE_VAL 0xFE8CE7A5 +#define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 -#define ARMCP_PKT_CTL_RC_SHIFT 12 -#define ARMCP_PKT_CTL_RC_MASK 0x0000F000 +#define CPUCP_PKT_CTL_RC_SHIFT 12 +#define CPUCP_PKT_CTL_RC_MASK 0x0000F000 -#define ARMCP_PKT_CTL_OPCODE_SHIFT 16 -#define ARMCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 +#define CPUCP_PKT_CTL_OPCODE_SHIFT 16 +#define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 -struct armcp_packet { +struct cpucp_packet { union { __le64 value; /* For SET packets */ __le64 result; /* For GET packets */ @@ -289,70 +288,70 @@ struct armcp_packet { /* For led set */ __le32 led_index; - /* For get Armcp info/EEPROM data */ + /* For get CpuCP info/EEPROM data */ __le32 data_max_size; }; __le32 reserved; }; -struct armcp_unmask_irq_arr_packet { - struct armcp_packet armcp_pkt; +struct cpucp_unmask_irq_arr_packet { + struct cpucp_packet cpucp_pkt; __le32 length; __le32 irqs[0]; }; -enum armcp_packet_rc { - armcp_packet_success, - armcp_packet_invalid, - armcp_packet_fault +enum cpucp_packet_rc { + cpucp_packet_success, + cpucp_packet_invalid, + cpucp_packet_fault }; /* - * armcp_temp_type should adhere to hwmon_temp_attributes + * cpucp_temp_type should adhere to hwmon_temp_attributes * defined in Linux kernel hwmon.h file */ -enum armcp_temp_type { - armcp_temp_input, - armcp_temp_max = 6, - armcp_temp_max_hyst, - armcp_temp_crit, - armcp_temp_crit_hyst, - armcp_temp_offset = 19, - armcp_temp_highest = 22, - armcp_temp_reset_history = 23 +enum cpucp_temp_type { + cpucp_temp_input, + cpucp_temp_max = 6, + cpucp_temp_max_hyst, + cpucp_temp_crit, + cpucp_temp_crit_hyst, + cpucp_temp_offset = 19, + cpucp_temp_highest = 22, + cpucp_temp_reset_history = 23 }; -enum armcp_in_attributes { - armcp_in_input, - armcp_in_min, - armcp_in_max, - armcp_in_highest = 7, - armcp_in_reset_history +enum cpucp_in_attributes { + cpucp_in_input, + cpucp_in_min, + cpucp_in_max, + cpucp_in_highest = 7, + cpucp_in_reset_history }; -enum armcp_curr_attributes { - armcp_curr_input, - armcp_curr_min, - armcp_curr_max, - armcp_curr_highest = 7, - armcp_curr_reset_history +enum cpucp_curr_attributes { + cpucp_curr_input, + cpucp_curr_min, + cpucp_curr_max, + cpucp_curr_highest = 7, + cpucp_curr_reset_history }; -enum armcp_fan_attributes { - armcp_fan_input, - armcp_fan_min = 2, - armcp_fan_max +enum cpucp_fan_attributes { + cpucp_fan_input, + cpucp_fan_min = 2, + cpucp_fan_max }; -enum armcp_pwm_attributes { - armcp_pwm_input, - armcp_pwm_enable +enum cpucp_pwm_attributes { + cpucp_pwm_input, + cpucp_pwm_enable }; -enum armcp_pcie_throughput_attributes { - armcp_pcie_throughput_tx, - armcp_pcie_throughput_rx +enum cpucp_pcie_throughput_attributes { + cpucp_pcie_throughput_tx, + cpucp_pcie_throughput_rx }; /* Event Queue Packets */ @@ -362,32 +361,32 @@ struct eq_generic_event { }; /* - * ArmCP info + * CpuCP info */ #define CARD_NAME_MAX_LEN 16 #define VERSION_MAX_LEN 128 -#define ARMCP_MAX_SENSORS 128 +#define CPUCP_MAX_SENSORS 128 -struct armcp_sensor { +struct cpucp_sensor { __le32 type; __le32 flags; }; /** - * struct armcp_card_types - ASIC card type. - * @armcp_card_type_pci: PCI card. - * @armcp_card_type_pmc: PCI Mezzanine Card. + * struct cpucp_card_types - ASIC card type. + * @cpucp_card_type_pci: PCI card. + * @cpucp_card_type_pmc: PCI Mezzanine Card. */ -enum armcp_card_types { - armcp_card_type_pci, - armcp_card_type_pmc +enum cpucp_card_types { + cpucp_card_type_pci, + cpucp_card_type_pmc }; /** - * struct armcp_info - Info from ArmCP that is necessary to the host's driver + * struct cpucp_info - Info from CpuCP that is necessary to the host's driver * @sensors: available sensors description. - * @kernel_version: ArmCP linux kernel version. + * @kernel_version: CpuCP linux kernel version. * @reserved: reserved field. * @card_type: card configuration type. * @card_location: in a server, each card has different connections topology @@ -396,12 +395,12 @@ enum armcp_card_types { * @infineon_version: Infineon main DC-DC version. * @fuse_version: silicon production FUSE information. * @thermal_version: thermald S/W version. - * @armcp_version: ArmCP S/W version. + * @cpucp_version: CpuCP S/W version. * @dram_size: available DRAM size. * @card_name: card name that will be displayed in HWMON subsystem on the host */ -struct armcp_info { - struct armcp_sensor sensors[ARMCP_MAX_SENSORS]; +struct cpucp_info { + struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; __u8 kernel_version[VERSION_MAX_LEN]; __le32 reserved; __le32 card_type; @@ -410,9 +409,9 @@ struct armcp_info { __le32 infineon_version; __u8 fuse_version[VERSION_MAX_LEN]; __u8 thermal_version[VERSION_MAX_LEN]; - __u8 armcp_version[VERSION_MAX_LEN]; + __u8 cpucp_version[VERSION_MAX_LEN]; __le64 dram_size; char card_name[CARD_NAME_MAX_LEN]; }; -#endif /* ARMCP_IF_H */ +#endif /* CPUCP_IF_H */ diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index 6803991726e8..a2dcad29340f 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -297,7 +297,7 @@ struct hl_info_hw_ip_info { __u32 device_id; /* PCI Device ID */ __u32 module_id; /* For mezzanine cards in servers (From OCP spec.) */ __u32 reserved[2]; - __u32 armcp_cpld_version; + __u32 cpld_version; __u32 psoc_pci_pll_nr; __u32 psoc_pci_pll_nf; __u32 psoc_pci_pll_od; @@ -305,7 +305,7 @@ struct hl_info_hw_ip_info { __u8 tpc_enabled_mask; __u8 dram_enabled; __u8 pad[2]; - __u8 armcp_version[HL_INFO_VERSION_MAX_LEN]; + __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; }; From f763946aefe67b3ea58696b75a930ba1ed886a83 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sat, 29 Aug 2020 11:24:03 +0300 Subject: [PATCH 21/46] habanalabs: cast to u64 before shift > 31 bits When shifting a boolean variable by more than 31 bits and putting the result into a u64 variable, we need to cast the boolean into unsigned 64 bits to prevent possible overflow. Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudi.c | 8 +++++--- drivers/misc/habanalabs/goya/goya.c | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 076a7697f85d..084019788e11 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -6114,7 +6114,7 @@ static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask, is_idle &= is_eng_idle; if (mask) - *mask |= !is_eng_idle << + *mask |= ((u64) !is_eng_idle) << (GAUDI_ENGINE_ID_DMA_0 + dma_id); if (s) seq_printf(s, fmt, dma_id, @@ -6137,7 +6137,8 @@ static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask, is_idle &= is_eng_idle; if (mask) - *mask |= !is_eng_idle << (GAUDI_ENGINE_ID_TPC_0 + i); + *mask |= ((u64) !is_eng_idle) << + (GAUDI_ENGINE_ID_TPC_0 + i); if (s) seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N", @@ -6165,7 +6166,8 @@ static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask, is_idle &= is_eng_idle; if (mask) - *mask |= !is_eng_idle << (GAUDI_ENGINE_ID_MME_0 + i); + *mask |= ((u64) !is_eng_idle) << + (GAUDI_ENGINE_ID_MME_0 + i); if (s) { if (!is_slave) seq_printf(s, fmt, i, diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index c41f2917863b..88847eb1b472 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -5173,7 +5173,8 @@ static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask, is_idle &= is_eng_idle; if (mask) - *mask |= !is_eng_idle << (GOYA_ENGINE_ID_DMA_0 + i); + *mask |= ((u64) !is_eng_idle) << + (GOYA_ENGINE_ID_DMA_0 + i); if (s) seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N", qm_glbl_sts0, dma_core_sts0); @@ -5196,7 +5197,8 @@ static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask, is_idle &= is_eng_idle; if (mask) - *mask |= !is_eng_idle << (GOYA_ENGINE_ID_TPC_0 + i); + *mask |= ((u64) !is_eng_idle) << + (GOYA_ENGINE_ID_TPC_0 + i); if (s) seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N", qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts); @@ -5216,7 +5218,7 @@ static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask, is_idle &= is_eng_idle; if (mask) - *mask |= !is_eng_idle << GOYA_ENGINE_ID_MME_0; + *mask |= ((u64) !is_eng_idle) << GOYA_ENGINE_ID_MME_0; if (s) { seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0, cmdq_glbl_sts0, mme_arch_sts); From 3174ac9bb1045946ff563aa01d679809e87fb2db Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sat, 29 Aug 2020 11:51:39 +0300 Subject: [PATCH 22/46] habanalabs: restructure hl_mmap Arrange the hl_mmap code to be more structured and expandable for the future. Add better defines that describe our usage of the vm_pgoff. Note that I shamelessly took the code and defines from the amdkfd driver (my previous driver). Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/command_buffer.c | 2 +- drivers/misc/habanalabs/common/device.c | 8 ++++++-- drivers/misc/habanalabs/common/habanalabs.h | 14 +++++++++++++- 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_buffer.c b/drivers/misc/habanalabs/common/command_buffer.c index e4bbe6a8e00f..68dfbafe3354 100644 --- a/drivers/misc/habanalabs/common/command_buffer.c +++ b/drivers/misc/habanalabs/common/command_buffer.c @@ -183,7 +183,7 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, * idr is 32-bit so we can safely OR it with a mask that is above * 32 bit */ - *handle = cb->id | HL_MMAP_CB_MASK; + *handle = cb->id | HL_MMAP_TYPE_CB; *handle <<= PAGE_SHIFT; hl_debugfs_add_cb(cb); diff --git a/drivers/misc/habanalabs/common/device.c b/drivers/misc/habanalabs/common/device.c index 6e916cc22a4c..aa7fa9e94651 100644 --- a/drivers/misc/habanalabs/common/device.c +++ b/drivers/misc/habanalabs/common/device.c @@ -123,9 +123,13 @@ static int hl_device_release_ctrl(struct inode *inode, struct file *filp) static int hl_mmap(struct file *filp, struct vm_area_struct *vma) { struct hl_fpriv *hpriv = filp->private_data; + unsigned long vm_pgoff; - if ((vma->vm_pgoff & HL_MMAP_CB_MASK) == HL_MMAP_CB_MASK) { - vma->vm_pgoff ^= HL_MMAP_CB_MASK; + vm_pgoff = vma->vm_pgoff; + vma->vm_pgoff = HL_MMAP_OFFSET_VALUE_GET(vm_pgoff); + + switch (vm_pgoff & HL_MMAP_TYPE_MASK) { + case HL_MMAP_TYPE_CB: return hl_cb_mmap(hpriv, vma); } diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 6912f88a4b01..cdb7a672ed30 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -22,7 +22,19 @@ #define HL_NAME "habanalabs" -#define HL_MMAP_CB_MASK (0x8000000000000000ull >> PAGE_SHIFT) +/* Use upper bits of mmap offset to store habana driver specific information. + * bits[63:62] - Encode mmap type + * bits[45:0] - mmap offset value + * + * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these + * defines are w.r.t to PAGE_SIZE + */ +#define HL_MMAP_TYPE_SHIFT (62 - PAGE_SHIFT) +#define HL_MMAP_TYPE_MASK (0x3ull << HL_MMAP_TYPE_SHIFT) +#define HL_MMAP_TYPE_CB (0x2ull << HL_MMAP_TYPE_SHIFT) + +#define HL_MMAP_OFFSET_VALUE_MASK (0x3FFFFFFFFFFFull >> PAGE_SHIFT) +#define HL_MMAP_OFFSET_VALUE_GET(off) (off & HL_MMAP_OFFSET_VALUE_MASK) #define HL_PENDING_RESET_PER_SEC 30 From c5e0ec66f01d6621a64837428efcbbe731d90cd5 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sat, 29 Aug 2020 11:55:15 +0300 Subject: [PATCH 23/46] habanalabs: clear vm_pgoff before doing the mmap The driver use vm_pgoff to hold the CB idr handle. Before we actually call the mapping function, we need to clear the handle so there won't be any garbage left in vm_pgoff. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/command_buffer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/habanalabs/common/command_buffer.c b/drivers/misc/habanalabs/common/command_buffer.c index 68dfbafe3354..6563e4dfe7b6 100644 --- a/drivers/misc/habanalabs/common/command_buffer.c +++ b/drivers/misc/habanalabs/common/command_buffer.c @@ -304,7 +304,11 @@ int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma) u32 handle, user_cb_size; int rc; + /* We use the page offset to hold the idr and thus we need to clear + * it before doing the mmap itself + */ handle = vma->vm_pgoff; + vma->vm_pgoff = 0; /* reference was taken here */ cb = hl_cb_get(hdev, &hpriv->cb_mgr, handle); From 0db575350cb1a2fa724f0198fd40b2c91ace5cb7 Mon Sep 17 00:00:00 2001 From: Hillf Danton Date: Sun, 23 Aug 2020 07:32:42 +0800 Subject: [PATCH 24/46] habanalabs: make use of dma_mmap_coherent Add dma_mmap_coherent() for goya and gaudi to match their use of dma_alloc_coherent(), see the Link tag for why. Link: https://lore.kernel.org/lkml/20200609091727.GA23814@lst.de/ Cc: Christoph Hellwig Cc: Zhang Li Cc: Ding Z Nan Signed-off-by: Hillf Danton Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/command_buffer.c | 9 ++------- drivers/misc/habanalabs/common/habanalabs.h | 2 +- drivers/misc/habanalabs/gaudi/gaudi.c | 7 +++---- drivers/misc/habanalabs/goya/goya.c | 7 +++---- 4 files changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_buffer.c b/drivers/misc/habanalabs/common/command_buffer.c index 6563e4dfe7b6..ba63cee74050 100644 --- a/drivers/misc/habanalabs/common/command_buffer.c +++ b/drivers/misc/habanalabs/common/command_buffer.c @@ -300,7 +300,6 @@ int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma) { struct hl_device *hdev = hpriv->hdev; struct hl_cb *cb; - phys_addr_t address; u32 handle, user_cb_size; int rc; @@ -360,12 +359,8 @@ int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma) vma->vm_private_data = cb; - /* Calculate address for CB */ - address = virt_to_phys((void *) (uintptr_t) cb->kernel_address); - - rc = hdev->asic_funcs->cb_mmap(hdev, vma, cb->kernel_address, - address, cb->size); - + rc = hdev->asic_funcs->cb_mmap(hdev, vma, (void *) cb->kernel_address, + cb->bus_address, cb->size); if (rc) { spin_lock(&cb->lock); cb->mmap = false; diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index cdb7a672ed30..6ea8ae616cf4 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -710,7 +710,7 @@ struct hl_asic_funcs { int (*suspend)(struct hl_device *hdev); int (*resume)(struct hl_device *hdev); int (*cb_mmap)(struct hl_device *hdev, struct vm_area_struct *vma, - u64 kaddress, phys_addr_t paddress, u32 size); + void *cpu_addr, dma_addr_t dma_addr, size_t size); void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi); void (*pqe_write)(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd); diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 084019788e11..bc7e7e3ba3a8 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -3091,17 +3091,16 @@ static int gaudi_resume(struct hl_device *hdev) } static int gaudi_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma, - u64 kaddress, phys_addr_t paddress, u32 size) + void *cpu_addr, dma_addr_t dma_addr, size_t size) { int rc; vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_DONTCOPY | VM_NORESERVE; - rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT, - size, vma->vm_page_prot); + rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, dma_addr, size); if (rc) - dev_err(hdev->dev, "remap_pfn_range error %d", rc); + dev_err(hdev->dev, "dma_mmap_coherent error %d", rc); return rc; } diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 88847eb1b472..94b7958ba5fb 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -2661,17 +2661,16 @@ int goya_resume(struct hl_device *hdev) } static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma, - u64 kaddress, phys_addr_t paddress, u32 size) + void *cpu_addr, dma_addr_t dma_addr, size_t size) { int rc; vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_DONTCOPY | VM_NORESERVE; - rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT, - size, vma->vm_page_prot); + rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, dma_addr, size); if (rc) - dev_err(hdev->dev, "remap_pfn_range error %d", rc); + dev_err(hdev->dev, "dma_mmap_coherent error %d", rc); return rc; } From 975ab7b32b90c97046ddbdd53798391b7d8a6a1e Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Tue, 1 Sep 2020 11:22:05 +0300 Subject: [PATCH 25/46] habanalabs: count dropped CS because max CS in-flight There is a case where the user reaches the maximum number of CS in-flight. In that case, the driver rejects the new CS of the user with EAGAIN. Count that event so the user can query the driver later to see if it happened. Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/command_submission.c | 5 ++++- include/uapi/misc/habanalabs.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/common/command_submission.c b/drivers/misc/habanalabs/common/command_submission.c index a811a9fdf13b..470bffbe9bdc 100644 --- a/drivers/misc/habanalabs/common/command_submission.c +++ b/drivers/misc/habanalabs/common/command_submission.c @@ -252,6 +252,8 @@ static void cs_counters_aggregate(struct hl_device *hdev, struct hl_ctx *ctx) ctx->cs_counters.parsing_drop_cnt; hdev->aggregated_cs_counters.queue_full_drop_cnt += ctx->cs_counters.queue_full_drop_cnt; + hdev->aggregated_cs_counters.max_cs_in_flight_drop_cnt += + ctx->cs_counters.max_cs_in_flight_drop_cnt; } static void cs_do_release(struct kref *ref) @@ -431,8 +433,9 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, (hdev->asic_prop.max_pending_cs - 1)]; if (other && !completion_done(&other->completion)) { - dev_dbg(hdev->dev, + dev_dbg_ratelimited(hdev->dev, "Rejecting CS because of too many in-flights CS\n"); + ctx->cs_counters.max_cs_in_flight_drop_cnt++; rc = -EAGAIN; goto free_fence; } diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index a2dcad29340f..69fb44d35292 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -401,12 +401,14 @@ struct hl_info_sync_manager { * @parsing_drop_cnt: dropped due to error in packet parsing * @queue_full_drop_cnt: dropped due to queue full * @device_in_reset_drop_cnt: dropped due to device in reset + * @max_cs_in_flight_drop_cnt: dropped due to maximum CS in-flight */ struct hl_cs_counters { __u64 out_of_mem_drop_cnt; __u64 parsing_drop_cnt; __u64 queue_full_drop_cnt; __u64 device_in_reset_drop_cnt; + __u64 max_cs_in_flight_drop_cnt; }; struct hl_info_cs_counters { From 6138bbe911264198ba16659c333084ab4bfb0c73 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Fri, 4 Sep 2020 20:18:16 +0300 Subject: [PATCH 26/46] habanalabs: rename ArmCP to CPU-CP There were a couple of comments where the name ArmCP was still used. Rename it to CPU-CP. In addition, rename ArmCP or ARM in log messages to "device CPU". Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/firmware_if.c | 17 ++++++++------- drivers/misc/habanalabs/common/habanalabs.h | 22 ++++++++++---------- drivers/misc/habanalabs/gaudi/gaudi.c | 4 ++-- drivers/misc/habanalabs/goya/goya.c | 2 +- 4 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c index f2a38e95359a..4409962d30ae 100644 --- a/drivers/misc/habanalabs/common/firmware_if.c +++ b/drivers/misc/habanalabs/common/firmware_if.c @@ -175,7 +175,7 @@ int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) + irq_arr_size; - /* data should be aligned to 8 bytes in order to ArmCP to copy it */ + /* data should be aligned to 8 bytes in order to CPU-CP to copy it */ total_pkt_size = (total_pkt_size + 0x7) & ~0x7; /* total_pkt_size is casted to u16 later on */ @@ -283,7 +283,7 @@ int hl_fw_cpucp_info_get(struct hl_device *hdev) &cpucp_info_dma_addr); if (!cpucp_info_cpu_addr) { dev_err(hdev->dev, - "Failed to allocate DMA memory for ArmCP info packet\n"); + "Failed to allocate DMA memory for CPU-CP info packet\n"); return -ENOMEM; } @@ -298,7 +298,7 @@ int hl_fw_cpucp_info_get(struct hl_device *hdev) HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, - "Failed to handle ArmCP info pkt, error %d\n", rc); + "Failed to handle CPU-CP info pkt, error %d\n", rc); goto out; } @@ -333,7 +333,7 @@ int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size) max_size, &eeprom_info_dma_addr); if (!eeprom_info_cpu_addr) { dev_err(hdev->dev, - "Failed to allocate DMA memory for ArmCP EEPROM packet\n"); + "Failed to allocate DMA memory for CPU-CP EEPROM packet\n"); return -ENOMEM; } @@ -349,7 +349,8 @@ int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size) if (rc) { dev_err(hdev->dev, - "Failed to handle ArmCP EEPROM packet, error %d\n", rc); + "Failed to handle CPU-CP EEPROM packet, error %d\n", + rc); goto out; } @@ -379,7 +380,7 @@ int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, - "Failed to handle ArmCP PCI info pkt, error %d\n", rc); + "Failed to handle CPU-CP PCI info pkt, error %d\n", rc); return rc; } counters->rx_throughput = result; @@ -390,7 +391,7 @@ int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, - "Failed to handle ArmCP PCI info pkt, error %d\n", rc); + "Failed to handle CPU-CP PCI info pkt, error %d\n", rc); return rc; } counters->tx_throughput = result; @@ -403,7 +404,7 @@ int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, HL_CPUCP_INFO_TIMEOUT_USEC, &result); if (rc) { dev_err(hdev->dev, - "Failed to handle ArmCP PCI info pkt, error %d\n", rc); + "Failed to handle CPU-CP PCI info pkt, error %d\n", rc); return rc; } counters->replay_cnt = (u32) result; diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 6ea8ae616cf4..b56410d75065 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -466,7 +466,7 @@ struct hl_cs_job; #define HL_EQ_LENGTH 64 #define HL_EQ_SIZE_IN_BYTES (HL_EQ_LENGTH * HL_EQ_ENTRY_SIZE) -/* Host <-> ArmCP shared memory size */ +/* Host <-> CPU-CP shared memory size */ #define HL_CPU_ACCESSIBLE_MEM_SIZE SZ_2M /** @@ -648,7 +648,7 @@ enum div_select_defs { * @debugfs_read32: debug interface for reading u32 from DRAM/SRAM. * @debugfs_write32: debug interface for writing u32 to DRAM/SRAM. * @add_device_attr: add ASIC specific device attributes. - * @handle_eqe: handle event queue entry (IRQ) from ArmCP. + * @handle_eqe: handle event queue entry (IRQ) from CPU-CP. * @set_pll_profile: change PLL profile (manual/automatic). * @get_events_stat: retrieve event queue entries histogram. * @read_pte: read MMU page table entry from DRAM. @@ -657,7 +657,7 @@ enum div_select_defs { * (L1 only) or hard (L0 & L1) flush. * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with * ASID-VA-size mask. - * @send_heartbeat: send is-alive packet to ArmCP and verify response. + * @send_heartbeat: send is-alive packet to CPU-CP and verify response. * @set_clock_gating: enable/disable clock gating per engine according to * clock gating mask in hdev * @disable_clock_gating: disable clock gating completely @@ -1438,8 +1438,8 @@ struct hl_device_idle_busy_ts { * @dev: related kernel basic device structure. * @dev_ctrl: related kernel device structure for the control device * @work_freq: delayed work to lower device frequency if possible. - * @work_heartbeat: delayed work for ArmCP is-alive check. - * @asic_name: ASIC specific nmae. + * @work_heartbeat: delayed work for CPU-CP is-alive check. + * @asic_name: ASIC specific name. * @asic_type: ASIC specific type. * @completion_queue: array of hl_cq. * @cq_wq: work queues of completion queues for executing work in process @@ -1450,14 +1450,14 @@ struct hl_device_idle_busy_ts { * @hw_queues_mirror_list: CS mirror list for TDR. * @hw_queues_mirror_lock: protects hw_queues_mirror_list. * @kernel_cb_mgr: command buffer manager for creating/destroying/handling CGs. - * @event_queue: event queue for IRQ from ArmCP. + * @event_queue: event queue for IRQ from CPU-CP. * @dma_pool: DMA pool for small allocations. - * @cpu_accessible_dma_mem: Host <-> ArmCP shared memory CPU address. - * @cpu_accessible_dma_address: Host <-> ArmCP shared memory DMA address. - * @cpu_accessible_dma_pool: Host <-> ArmCP shared memory pool. + * @cpu_accessible_dma_mem: Host <-> CPU-CP shared memory CPU address. + * @cpu_accessible_dma_address: Host <-> CPU-CP shared memory DMA address. + * @cpu_accessible_dma_pool: Host <-> CPU-CP shared memory pool. * @asid_bitmap: holds used/available ASIDs. * @asid_mutex: protects asid_bitmap. - * @send_cpu_message_lock: enforces only one message in Host <-> ArmCP queue. + * @send_cpu_message_lock: enforces only one message in Host <-> CPU-CP queue. * @debug_lock: protects critical section of setting debug mode for device * @asic_prop: ASIC specific immutable properties. * @asic_funcs: ASIC specific functions. @@ -1511,7 +1511,7 @@ struct hl_device_idle_busy_ts { * @late_init_done: is late init stage was done during initialization. * @hwmon_initialized: is H/W monitor sensors was initialized. * @hard_reset_pending: is there a hard reset work pending. - * @heartbeat: is heartbeat sanity check towards ArmCP enabled. + * @heartbeat: is heartbeat sanity check towards CPU-CP enabled. * @reset_on_lockup: true if a reset should be done in case of stuck CS, false * otherwise. * @dram_supports_virtual_memory: is MMU enabled towards DRAM. diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index bc7e7e3ba3a8..7946179632fb 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -2854,7 +2854,7 @@ static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout) if (err) { dev_err(hdev->dev, - "Failed to communicate with ARM CPU (ArmCP timeout)\n"); + "Failed to communicate with Device CPU (CPU-CP timeout)\n"); return -EIO; } @@ -5616,7 +5616,7 @@ static bool gaudi_tpc_read_interrupts(struct hl_device *hdev, u8 tpc_id, bool soft_reset_required = false; /* Accessing the TPC_INTR_CAUSE registers requires disabling the clock - * gating, and thus cannot be done in ArmCP and should be done instead + * gating, and thus cannot be done in CPU-CP and should be done instead * by the driver. */ diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 94b7958ba5fb..fb7e4f50c198 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -4509,7 +4509,7 @@ static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr, total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) + irq_arr_size; - /* data should be aligned to 8 bytes in order to ArmCP to copy it */ + /* data should be aligned to 8 bytes in order to CPU-CP to copy it */ total_pkt_size = (total_pkt_size + 0x7) & ~0x7; /* total_pkt_size is casted to u16 later on */ From b01a971f80be339fb072044ef201ac724db9b58c Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Fri, 4 Sep 2020 20:21:39 +0300 Subject: [PATCH 27/46] habanalabs: remove unused ASIC function pointer Old function pointer that was left when the call to this function pointer was removed. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/habanalabs.h | 5 ----- drivers/misc/habanalabs/gaudi/gaudi.c | 1 - drivers/misc/habanalabs/goya/goya.c | 1 - 3 files changed, 7 deletions(-) diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index b56410d75065..ec765320159a 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -675,8 +675,6 @@ enum div_select_defs { * ASIC * @get_hw_state: retrieve the H/W state * @pci_bars_map: Map PCI BARs. - * @set_dram_bar_base: Set DRAM BAR to map specific device address. Returns - * old address the bar pointed to or U64_MAX for failure * @init_iatu: Initialize the iATU unit inside the PCI controller. * @rreg: Read a register. Needed for simulator support. * @wreg: Write a register. Needed for simulator support. @@ -779,7 +777,6 @@ struct hl_asic_funcs { u16 len, u32 timeout, long *result); enum hl_device_hw_state (*get_hw_state)(struct hl_device *hdev); int (*pci_bars_map)(struct hl_device *hdev); - u64 (*set_dram_bar_base)(struct hl_device *hdev, u64 addr); int (*init_iatu)(struct hl_device *hdev); u32 (*rreg)(struct hl_device *hdev, u32 reg); void (*wreg)(struct hl_device *hdev, u32 reg, u32 val); @@ -1874,8 +1871,6 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3], bool is_wc[3]); int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data); -int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar, - u64 addr); int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region, struct hl_inbound_pci_region *pci_region); int hl_pci_set_outbound_region(struct hl_device *hdev, diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 7946179632fb..483989500863 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -6642,7 +6642,6 @@ static const struct hl_asic_funcs gaudi_funcs = { .send_cpu_message = gaudi_send_cpu_message, .get_hw_state = gaudi_get_hw_state, .pci_bars_map = gaudi_pci_bars_map, - .set_dram_bar_base = gaudi_set_hbm_bar_base, .init_iatu = gaudi_init_iatu, .rreg = hl_rreg, .wreg = hl_wreg, diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index fb7e4f50c198..804c83eb12b7 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -5377,7 +5377,6 @@ static const struct hl_asic_funcs goya_funcs = { .send_cpu_message = goya_send_cpu_message, .get_hw_state = goya_get_hw_state, .pci_bars_map = goya_pci_bars_map, - .set_dram_bar_base = goya_set_ddr_bar_base, .init_iatu = goya_init_iatu, .rreg = hl_rreg, .wreg = hl_wreg, From ae926514dd62673bc1a2513e5271d1d6d3d473b5 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Fri, 4 Sep 2020 20:22:35 +0300 Subject: [PATCH 28/46] habanalabs: remove unused define Cleanup the code. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudiP.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudiP.h b/drivers/misc/habanalabs/gaudi/gaudiP.h index b86eb98b145c..dd222bc128f9 100644 --- a/drivers/misc/habanalabs/gaudi/gaudiP.h +++ b/drivers/misc/habanalabs/gaudi/gaudiP.h @@ -35,8 +35,6 @@ #error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES" #endif -#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */ - #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ #define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */ From 763a0b4d81f60beb835dc3e8991aa9e1ed9f71b1 Mon Sep 17 00:00:00 2001 From: Ofir Bitton Date: Fri, 4 Sep 2020 21:33:53 +0300 Subject: [PATCH 29/46] habanalabs: Fix alignment issue in cpucp_info structure Because the device CPU compiler aligns structures to 8 bytes, struct cpucp_info has an alignment issue as some parts in the structure are not aligned to 8 bytes. It is preferred that we explicitly insert placeholders inside the structure to avoid confusion in order to validate this scenario, we printed both pointers: __u8 cpucp_version[VERSION_MAX_LEN]; (0xffff899c67ed4cbc) __le64 dram_size; (0xffff899c67ed4d40) we see difference of 132 bytes although the first array is only 128 bytes long, Meaning compiler added a 4 byte padding. Signed-off-by: Ofir Bitton Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/include/common/cpucp_if.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/habanalabs/include/common/cpucp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h index 1e8480e978e2..dcde440427b4 100644 --- a/drivers/misc/habanalabs/include/common/cpucp_if.h +++ b/drivers/misc/habanalabs/include/common/cpucp_if.h @@ -410,6 +410,7 @@ struct cpucp_info { __u8 fuse_version[VERSION_MAX_LEN]; __u8 thermal_version[VERSION_MAX_LEN]; __u8 cpucp_version[VERSION_MAX_LEN]; + __le32 reserved2; __le64 dram_size; char card_name[CARD_NAME_MAX_LEN]; }; From 5a1b861daab8379d792bfae917f317708d1c99d2 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Fri, 4 Sep 2020 21:36:46 +0300 Subject: [PATCH 30/46] habanalabs: increase PQ COMP_OFFSET by one nibble For future ASICs, we increase this field by one nibble. This field was not used by the current ASICs so this change doesn't break anything. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/include/common/qman_if.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/include/common/qman_if.h b/drivers/misc/habanalabs/include/common/qman_if.h index 0fdb49188ed7..7ed7739575ee 100644 --- a/drivers/misc/habanalabs/include/common/qman_if.h +++ b/drivers/misc/habanalabs/include/common/qman_if.h @@ -40,7 +40,7 @@ struct hl_bd { */ #define BD_CTL_COMP_OFFSET_SHIFT 16 -#define BD_CTL_COMP_OFFSET_MASK 0x00FF0000 +#define BD_CTL_COMP_OFFSET_MASK 0x0FFF0000 #define BD_CTL_COMP_DATA_SHIFT 0 #define BD_CTL_COMP_DATA_MASK 0x0000FFFF From 1fb2f3743754994fec412f63a12cbc4d72f49e38 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Fri, 4 Sep 2020 21:39:14 +0300 Subject: [PATCH 31/46] habanalabs: check flag before reset because of f/w event For consistency with GAUDI code, add check of the relevant flag in the device structure before resetting the GOYA device in case of firmware event. Reviewed-by: Tomer Tayar Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/goya/goya.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 804c83eb12b7..46a900fb3ef8 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -4644,7 +4644,8 @@ void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry) case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC: case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET: goya_print_irq_info(hdev, event_type, false); - hl_device_reset(hdev, true, false); + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); break; case GOYA_ASYNC_EVENT_ID_PCIE_DEC: From 7c52fb0a096aecd6b7ef474e9037db2194570162 Mon Sep 17 00:00:00 2001 From: Omer Shpigelman Date: Sun, 28 Jun 2020 21:15:53 +0300 Subject: [PATCH 32/46] habanalabs: use smallest possible alignment for virtual addresses Change the acquiring of a device virtual address for mapping by using the smallest possible alignment, rather than the biggest, depending on the page size used by the user for allocating the memory. This will lower the virtual space memory consumption. Signed-off-by: Omer Shpigelman Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/memory.c | 86 ++++++++++++++----------- 1 file changed, 48 insertions(+), 38 deletions(-) diff --git a/drivers/misc/habanalabs/common/memory.c b/drivers/misc/habanalabs/common/memory.c index 5ff4688683fd..3324332811bc 100644 --- a/drivers/misc/habanalabs/common/memory.c +++ b/drivers/misc/habanalabs/common/memory.c @@ -505,41 +505,32 @@ static inline int add_va_block(struct hl_device *hdev, } /* - * get_va_block - get a virtual block with the requested size - * - * @hdev : pointer to the habanalabs device structure - * @va_range : pointer to the virtual addresses range - * @size : requested block size - * @hint_addr : hint for request address by the user - * @is_userptr : is host or DRAM memory + * get_va_block() - get a virtual block for the given size and alignment. + * @hdev: pointer to the habanalabs device structure. + * @va_range: pointer to the virtual addresses range. + * @size: requested block size. + * @hint_addr: hint for requested address by the user. + * @va_block_align: required alignment of the virtual block start address. * * This function does the following: * - Iterate on the virtual block list to find a suitable virtual block for the - * requested size - * - Reserve the requested block and update the list - * - Return the start address of the virtual block + * given size and alignment. + * - Reserve the requested block and update the list. + * - Return the start address of the virtual block. */ -static u64 get_va_block(struct hl_device *hdev, - struct hl_va_range *va_range, u64 size, u64 hint_addr, - bool is_userptr) +static u64 get_va_block(struct hl_device *hdev, struct hl_va_range *va_range, + u64 size, u64 hint_addr, u32 va_block_align) { struct hl_vm_va_block *va_block, *new_va_block = NULL; - u64 valid_start, valid_size, prev_start, prev_end, page_mask, + u64 valid_start, valid_size, prev_start, prev_end, align_mask, res_valid_start = 0, res_valid_size = 0; - u32 page_size; bool add_prev = false; - if (is_userptr) - /* - * We cannot know if the user allocated memory with huge pages - * or not, hence we continue with the biggest possible - * granularity. - */ - page_size = hdev->asic_prop.pmmu_huge.page_size; - else - page_size = hdev->asic_prop.dmmu.page_size; + align_mask = ~((u64)va_block_align - 1); - page_mask = ~((u64)page_size - 1); + /* check if hint_addr is aligned */ + if (hint_addr & (va_block_align - 1)) + hint_addr = 0; mutex_lock(&va_range->lock); @@ -549,9 +540,9 @@ static u64 get_va_block(struct hl_device *hdev, /* calc the first possible aligned addr */ valid_start = va_block->start; - if (valid_start & (page_size - 1)) { - valid_start &= page_mask; - valid_start += page_size; + if (valid_start & (va_block_align - 1)) { + valid_start &= align_mask; + valid_start += va_block_align; if (valid_start > va_block->end) continue; } @@ -863,7 +854,7 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, struct hl_va_range *va_range; enum vm_type_t *vm_type; u64 ret_vaddr, hint_addr; - u32 handle = 0; + u32 handle = 0, va_block_align; int rc; bool is_userptr = args->flags & HL_MEM_USERPTR; @@ -873,6 +864,8 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, if (is_userptr) { u64 addr = args->map_host.host_virt_addr, size = args->map_host.mem_size; + u32 page_size = hdev->asic_prop.pmmu.page_size, + huge_page_size = hdev->asic_prop.pmmu_huge.page_size; rc = dma_map_host_va(hdev, addr, size, &userptr); if (rc) { @@ -892,6 +885,27 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, vm_type = (enum vm_type_t *) userptr; hint_addr = args->map_host.hint_addr; handle = phys_pg_pack->handle; + + /* get required alignment */ + if (phys_pg_pack->page_size == page_size) { + va_range = ctx->host_va_range; + + /* + * huge page alignment may be needed in case of regular + * page mapping, depending on the host VA alignment + */ + if (addr & (huge_page_size - 1)) + va_block_align = page_size; + else + va_block_align = huge_page_size; + } else { + /* + * huge page alignment is needed in case of huge page + * mapping + */ + va_range = ctx->host_huge_va_range; + va_block_align = huge_page_size; + } } else { handle = lower_32_bits(args->map_device.handle); @@ -912,6 +926,10 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, vm_type = (enum vm_type_t *) phys_pg_pack; hint_addr = args->map_device.hint_addr; + + /* DRAM VA alignment is the same as the DRAM page size */ + va_range = ctx->dram_va_range; + va_block_align = hdev->asic_prop.dmmu.page_size; } /* @@ -933,16 +951,8 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, goto hnode_err; } - if (is_userptr) - if (phys_pg_pack->page_size == hdev->asic_prop.pmmu.page_size) - va_range = ctx->host_va_range; - else - va_range = ctx->host_huge_va_range; - else - va_range = ctx->dram_va_range; - ret_vaddr = get_va_block(hdev, va_range, phys_pg_pack->total_size, - hint_addr, is_userptr); + hint_addr, va_block_align); if (!ret_vaddr) { dev_err(hdev->dev, "no available va block for handle %u\n", handle); From c91324f41b27fc3dc7c2000426b1591a7f6d575c Mon Sep 17 00:00:00 2001 From: Moti Haimovski Date: Wed, 12 Aug 2020 11:40:08 +0300 Subject: [PATCH 33/46] habanalabs: rename mmu.c to mmu_v1.c In the future we will have MMU v2 code, so we need to prepare the driver for it. The first step is to rename the current MMU file to mmu_v1.c. Signed-off-by: Moti Haimovski Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/Makefile | 4 ++-- drivers/misc/habanalabs/common/{mmu.c => mmu_v1.c} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename drivers/misc/habanalabs/common/{mmu.c => mmu_v1.c} (100%) diff --git a/drivers/misc/habanalabs/common/Makefile b/drivers/misc/habanalabs/common/Makefile index b984bfa4face..e8ed12810517 100644 --- a/drivers/misc/habanalabs/common/Makefile +++ b/drivers/misc/habanalabs/common/Makefile @@ -3,5 +3,5 @@ HL_COMMON_FILES := common/habanalabs_drv.o common/device.o common/context.o \ common/asid.o common/habanalabs_ioctl.o \ common/command_buffer.o common/hw_queue.o common/irq.o \ common/sysfs.o common/hwmon.o common/memory.o \ - common/command_submission.o common/mmu.o common/firmware_if.o \ - common/pci.o + common/command_submission.o common/mmu_v1.o \ + common/firmware_if.o common/pci.o diff --git a/drivers/misc/habanalabs/common/mmu.c b/drivers/misc/habanalabs/common/mmu_v1.c similarity index 100% rename from drivers/misc/habanalabs/common/mmu.c rename to drivers/misc/habanalabs/common/mmu_v1.c From d83fe66928b2ff50367c983c345d17f7b8769235 Mon Sep 17 00:00:00 2001 From: Moti Haimovski Date: Wed, 12 Aug 2020 13:33:44 +0300 Subject: [PATCH 34/46] habanalabs: refactor MMU as device-oriented As preparation to MMU v2, rework MMU to be device oriented instantiated according to the device in hand. Signed-off-by: Moti Haimovski Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/Makefile | 2 +- drivers/misc/habanalabs/common/device.c | 6 + drivers/misc/habanalabs/common/habanalabs.h | 49 +++- drivers/misc/habanalabs/common/mmu.c | 309 ++++++++++++++++++++ drivers/misc/habanalabs/common/mmu_v1.c | 270 +++-------------- 5 files changed, 409 insertions(+), 227 deletions(-) create mode 100644 drivers/misc/habanalabs/common/mmu.c diff --git a/drivers/misc/habanalabs/common/Makefile b/drivers/misc/habanalabs/common/Makefile index e8ed12810517..eccd8c7dc62d 100644 --- a/drivers/misc/habanalabs/common/Makefile +++ b/drivers/misc/habanalabs/common/Makefile @@ -3,5 +3,5 @@ HL_COMMON_FILES := common/habanalabs_drv.o common/device.o common/context.o \ common/asid.o common/habanalabs_ioctl.o \ common/command_buffer.o common/hw_queue.o common/irq.o \ common/sysfs.o common/hwmon.o common/memory.o \ - common/command_submission.o common/mmu_v1.o \ + common/command_submission.o common/mmu.o common/mmu_v1.o \ common/firmware_if.o common/pci.o diff --git a/drivers/misc/habanalabs/common/device.c b/drivers/misc/habanalabs/common/device.c index aa7fa9e94651..196e35d71118 100644 --- a/drivers/misc/habanalabs/common/device.c +++ b/drivers/misc/habanalabs/common/device.c @@ -321,6 +321,10 @@ static int device_early_init(struct hl_device *hdev) goto free_chip_info; } + rc = hl_mmu_if_set_funcs(hdev); + if (rc) + goto free_idle_busy_ts_arr; + hl_cb_mgr_init(&hdev->kernel_cb_mgr); mutex_init(&hdev->send_cpu_message_lock); @@ -334,6 +338,8 @@ static int device_early_init(struct hl_device *hdev) return 0; +free_idle_busy_ts_arr: + kfree(hdev->idle_busy_ts_arr); free_chip_info: kfree(hdev->hl_chip_info); free_eq_wq: diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index ec765320159a..15e746a5fe35 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -1423,6 +1423,44 @@ struct hl_device_idle_busy_ts { ktime_t busy_to_idle_ts; }; + +/** + * struct hl_mmu_priv - used for holding per-device mmu internal information. + * @mmu_pgt_pool: pool of page tables used by MMU for allocating hops. + * @mmu_shadow_hop0: shadow array of hop0 tables. + */ +struct hl_mmu_priv { + struct gen_pool *mmu_pgt_pool; + void *mmu_shadow_hop0; +}; + +/** + * struct hl_mmu_funcs - Device related MMU functions. + * @init: initialize the MMU module. + * @fini: release the MMU module. + * @ctx_init: Initialize a context for using the MMU module. + * @ctx_fini: disable a ctx from using the mmu module. + * @map: maps a virtual address to physical address for a context. + * @unmap: unmap a virtual address of a context. + * @flush: flush all writes from all cores to reach device MMU. + * @swap_out: marks all mapping of the given context as swapped out. + * @swap_in: marks all mapping of the given context as swapped in. + */ +struct hl_mmu_funcs { + int (*init)(struct hl_device *hdev); + void (*fini)(struct hl_device *hdev); + int (*ctx_init)(struct hl_ctx *ctx); + void (*ctx_fini)(struct hl_ctx *ctx); + int (*map)(struct hl_ctx *ctx, + u64 virt_addr, u64 phys_addr, u32 page_size, + bool is_dram_addr); + int (*unmap)(struct hl_ctx *ctx, + u64 virt_addr, bool is_dram_addr); + void (*flush)(struct hl_ctx *ctx); + void (*swap_out)(struct hl_ctx *ctx); + void (*swap_in)(struct hl_ctx *ctx); +}; + /** * struct hl_device - habanalabs device structure. * @pdev: pointer to PCI device, can be NULL in case of simulator device. @@ -1459,10 +1497,8 @@ struct hl_device_idle_busy_ts { * @asic_prop: ASIC specific immutable properties. * @asic_funcs: ASIC specific functions. * @asic_specific: ASIC specific information to use only from ASIC files. - * @mmu_pgt_pool: pool of available MMU hops. * @vm: virtual memory manager for MMU. * @mmu_cache_lock: protects MMU cache invalidation as it can serve one context. - * @mmu_shadow_hop0: shadow mapping of the MMU hop 0 zone. * @hwmon_dev: H/W monitor device. * @pm_mng_profile: current power management profile. * @hl_chip_info: ASIC's sensors information. @@ -1480,6 +1516,8 @@ struct hl_device_idle_busy_ts { * @idle_busy_ts_arr: array to hold time stamps of transitions from idle to busy * and vice-versa * @aggregated_cs_counters: aggregated cs counters among all contexts + * @mmu_priv: device-specific MMU data. + * @mmu_func: device-related MMU functions. * @dram_used_mem: current DRAM memory consumption. * @timeout_jiffies: device CS timeout value. * @max_power: the max power of the device, as configured by the sysadmin. This @@ -1564,10 +1602,8 @@ struct hl_device { struct asic_fixed_properties asic_prop; const struct hl_asic_funcs *asic_funcs; void *asic_specific; - struct gen_pool *mmu_pgt_pool; struct hl_vm vm; struct mutex mmu_cache_lock; - void *mmu_shadow_hop0; struct device *hwmon_dev; enum hl_pm_mng_profile pm_mng_profile; struct hwmon_chip_info *hl_chip_info; @@ -1591,6 +1627,9 @@ struct hl_device { struct hl_cs_counters aggregated_cs_counters; + struct hl_mmu_priv mmu_priv; + struct hl_mmu_funcs mmu_func; + atomic64_t dram_used_mem; u64 timeout_jiffies; u64 max_power; @@ -1842,6 +1881,8 @@ int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size, bool flush_pte); void hl_mmu_swap_out(struct hl_ctx *ctx); void hl_mmu_swap_in(struct hl_ctx *ctx); +int hl_mmu_if_set_funcs(struct hl_device *hdev); +void hl_mmu_v1_set_funcs(struct hl_device *hdev); int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name, void __iomem *dst); diff --git a/drivers/misc/habanalabs/common/mmu.c b/drivers/misc/habanalabs/common/mmu.c new file mode 100644 index 000000000000..b5058798aeb9 --- /dev/null +++ b/drivers/misc/habanalabs/common/mmu.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include + +#include "habanalabs.h" + +static bool is_dram_va(struct hl_device *hdev, u64 virt_addr) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size, + prop->dmmu.start_addr, + prop->dmmu.end_addr); +} + +/** + * hl_mmu_init() - initialize the MMU module. + * @hdev: habanalabs device structure. + * + * This function does the following: + * - Create a pool of pages for pgt_infos. + * - Create a shadow table for pgt + * + * Return: 0 for success, non-zero for failure. + */ +int hl_mmu_init(struct hl_device *hdev) +{ + if (hdev->mmu_enable) + return hdev->mmu_func.init(hdev); + + return 0; +} + +/** + * hl_mmu_fini() - release the MMU module. + * @hdev: habanalabs device structure. + * + * This function does the following: + * - Disable MMU in H/W. + * - Free the pgt_infos pool. + * + * All contexts should be freed before calling this function. + */ +void hl_mmu_fini(struct hl_device *hdev) +{ + if (hdev->mmu_enable) + hdev->mmu_func.fini(hdev); +} + +/** + * hl_mmu_ctx_init() - initialize a context for using the MMU module. + * @ctx: pointer to the context structure to initialize. + * + * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all + * page tables hops related to this context. + * Return: 0 on success, non-zero otherwise. + */ +int hl_mmu_ctx_init(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + + if (hdev->mmu_enable) + return hdev->mmu_func.ctx_init(ctx); + + return 0; +} + +/* + * hl_mmu_ctx_fini - disable a ctx from using the mmu module + * + * @ctx: pointer to the context structure + * + * This function does the following: + * - Free any pgts which were not freed yet + * - Free the mutex + * - Free DRAM default page mapping hops + */ +void hl_mmu_ctx_fini(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + + if (hdev->mmu_enable) + hdev->mmu_func.ctx_fini(ctx); +} + +/* + * hl_mmu_unmap - unmaps a virtual addr + * + * @ctx: pointer to the context structure + * @virt_addr: virt addr to map from + * @page_size: size of the page to unmap + * @flush_pte: whether to do a PCI flush + * + * This function does the following: + * - Check that the virt addr is mapped + * - Unmap the virt addr and frees pgts if possible + * - Returns 0 on success, -EINVAL if the given addr is not mapped + * + * Because this function changes the page tables in the device and because it + * changes the MMU hash, it must be protected by a lock. + * However, because it maps only a single page, the lock should be implemented + * in a higher level in order to protect the entire mapping of the memory area + * + * For optimization reasons PCI flush may be requested once after unmapping of + * large area. + */ +int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size, + bool flush_pte) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_mmu_properties *mmu_prop; + u64 real_virt_addr; + u32 real_page_size, npages; + int i, rc = 0; + bool is_dram_addr; + + if (!hdev->mmu_enable) + return 0; + + is_dram_addr = is_dram_va(hdev, virt_addr); + + if (is_dram_addr) + mmu_prop = &prop->dmmu; + else if ((page_size % prop->pmmu_huge.page_size) == 0) + mmu_prop = &prop->pmmu_huge; + else + mmu_prop = &prop->pmmu; + + /* + * The H/W handles mapping of specific page sizes. Hence if the page + * size is bigger, we break it to sub-pages and unmap them separately. + */ + if ((page_size % mmu_prop->page_size) == 0) { + real_page_size = mmu_prop->page_size; + } else { + dev_err(hdev->dev, + "page size of %u is not %uKB aligned, can't unmap\n", + page_size, mmu_prop->page_size >> 10); + + return -EFAULT; + } + + npages = page_size / real_page_size; + real_virt_addr = virt_addr; + + for (i = 0 ; i < npages ; i++) { + rc = hdev->mmu_func.unmap(ctx, real_virt_addr, is_dram_addr); + if (rc) + break; + + real_virt_addr += real_page_size; + } + + if (flush_pte) + hdev->mmu_func.flush(ctx); + + return rc; +} + +/* + * hl_mmu_map - maps a virtual addr to physical addr + * + * @ctx: pointer to the context structure + * @virt_addr: virt addr to map from + * @phys_addr: phys addr to map to + * @page_size: physical page size + * @flush_pte: whether to do a PCI flush + * + * This function does the following: + * - Check that the virt addr is not mapped + * - Allocate pgts as necessary in order to map the virt addr to the phys + * - Returns 0 on success, -EINVAL if addr is already mapped, or -ENOMEM. + * + * Because this function changes the page tables in the device and because it + * changes the MMU hash, it must be protected by a lock. + * However, because it maps only a single page, the lock should be implemented + * in a higher level in order to protect the entire mapping of the memory area + * + * For optimization reasons PCI flush may be requested once after mapping of + * large area. + */ +int hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size, + bool flush_pte) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_mmu_properties *mmu_prop; + u64 real_virt_addr, real_phys_addr; + u32 real_page_size, npages; + int i, rc, mapped_cnt = 0; + bool is_dram_addr; + + if (!hdev->mmu_enable) + return 0; + + is_dram_addr = is_dram_va(hdev, virt_addr); + + if (is_dram_addr) + mmu_prop = &prop->dmmu; + else if ((page_size % prop->pmmu_huge.page_size) == 0) + mmu_prop = &prop->pmmu_huge; + else + mmu_prop = &prop->pmmu; + + /* + * The H/W handles mapping of specific page sizes. Hence if the page + * size is bigger, we break it to sub-pages and map them separately. + */ + if ((page_size % mmu_prop->page_size) == 0) { + real_page_size = mmu_prop->page_size; + } else { + dev_err(hdev->dev, + "page size of %u is not %uKB aligned, can't unmap\n", + page_size, mmu_prop->page_size >> 10); + + return -EFAULT; + } + + WARN_ONCE((phys_addr & (real_page_size - 1)), + "Mapping 0x%llx with page size of 0x%x is erroneous! Address must be divisible by page size", + phys_addr, real_page_size); + + npages = page_size / real_page_size; + real_virt_addr = virt_addr; + real_phys_addr = phys_addr; + + for (i = 0 ; i < npages ; i++) { + rc = hdev->mmu_func.map(ctx, real_virt_addr, real_phys_addr, + real_page_size, is_dram_addr); + if (rc) + goto err; + + real_virt_addr += real_page_size; + real_phys_addr += real_page_size; + mapped_cnt++; + } + + if (flush_pte) + hdev->mmu_func.flush(ctx); + + return 0; + +err: + real_virt_addr = virt_addr; + for (i = 0 ; i < mapped_cnt ; i++) { + if (hdev->mmu_func.unmap(ctx, real_virt_addr, is_dram_addr)) + dev_warn_ratelimited(hdev->dev, + "failed to unmap va: 0x%llx\n", real_virt_addr); + + real_virt_addr += real_page_size; + } + + hdev->mmu_func.flush(ctx); + + return rc; +} + +/* + * hl_mmu_swap_out - marks all mapping of the given ctx as swapped out + * + * @ctx: pointer to the context structure + * + */ +void hl_mmu_swap_out(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + + if (hdev->mmu_enable) + hdev->mmu_func.swap_out(ctx); +} + +/* + * hl_mmu_swap_in - marks all mapping of the given ctx as swapped in + * + * @ctx: pointer to the context structure + * + */ +void hl_mmu_swap_in(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + + if (hdev->mmu_enable) + hdev->mmu_func.swap_in(ctx); +} + +int hl_mmu_if_set_funcs(struct hl_device *hdev) +{ + if (!hdev->mmu_enable) + return 0; + + switch (hdev->asic_type) { + case ASIC_GOYA: + case ASIC_GAUDI: + hl_mmu_v1_set_funcs(hdev); + break; + default: + dev_err(hdev->dev, "Unrecognized ASIC type %d\n", + hdev->asic_type); + return -EOPNOTSUPP; + } + + return 0; +} diff --git a/drivers/misc/habanalabs/common/mmu_v1.c b/drivers/misc/habanalabs/common/mmu_v1.c index 3fc0f497fab3..8d1eb5265419 100644 --- a/drivers/misc/habanalabs/common/mmu_v1.c +++ b/drivers/misc/habanalabs/common/mmu_v1.c @@ -29,7 +29,7 @@ static void _free_hop(struct hl_ctx *ctx, struct pgt_info *pgt_info) { struct hl_device *hdev = ctx->hdev; - gen_pool_free(hdev->mmu_pgt_pool, pgt_info->phys_addr, + gen_pool_free(hdev->mmu_priv.mmu_pgt_pool, pgt_info->phys_addr, hdev->asic_prop.mmu_hop_table_size); hash_del(&pgt_info->node); kfree((u64 *) (uintptr_t) pgt_info->shadow_addr); @@ -54,7 +54,7 @@ static u64 alloc_hop(struct hl_ctx *ctx) if (!pgt_info) return ULLONG_MAX; - phys_addr = (u64) gen_pool_alloc(hdev->mmu_pgt_pool, + phys_addr = (u64) gen_pool_alloc(hdev->mmu_priv.mmu_pgt_pool, prop->mmu_hop_table_size); if (!phys_addr) { dev_err(hdev->dev, "failed to allocate page\n"); @@ -75,7 +75,8 @@ static u64 alloc_hop(struct hl_ctx *ctx) return shadow_addr; shadow_err: - gen_pool_free(hdev->mmu_pgt_pool, phys_addr, prop->mmu_hop_table_size); + gen_pool_free(hdev->mmu_priv.mmu_pgt_pool, phys_addr, + prop->mmu_hop_table_size); pool_add_err: kfree(pgt_info); @@ -90,11 +91,11 @@ static inline u64 get_phys_hop0_addr(struct hl_ctx *ctx) static inline u64 get_hop0_addr(struct hl_ctx *ctx) { - return (u64) (uintptr_t) ctx->hdev->mmu_shadow_hop0 + + return (u64) (uintptr_t) ctx->hdev->mmu_priv.mmu_shadow_hop0 + (ctx->asid * ctx->hdev->asic_prop.mmu_hop_table_size); } -static inline void flush(struct hl_ctx *ctx) +static void flush(struct hl_ctx *ctx) { /* flush all writes from all cores to reach PCI */ mb(); @@ -254,15 +255,6 @@ static inline u64 get_phys_addr(struct hl_ctx *ctx, u64 shadow_addr) return phys_hop_addr + pte_offset; } -static bool is_dram_va(struct hl_device *hdev, u64 virt_addr) -{ - struct asic_fixed_properties *prop = &hdev->asic_prop; - - return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size, - prop->dmmu.start_addr, - prop->dmmu.end_addr); -} - static int dram_default_mapping_init(struct hl_ctx *ctx) { struct hl_device *hdev = ctx->hdev; @@ -413,7 +405,7 @@ static void dram_default_mapping_fini(struct hl_ctx *ctx) } /** - * hl_mmu_init() - initialize the MMU module. + * hl_mmu_v1_init() - initialize the MMU module. * @hdev: habanalabs device structure. * * This function does the following: @@ -422,23 +414,20 @@ static void dram_default_mapping_fini(struct hl_ctx *ctx) * * Return: 0 for success, non-zero for failure. */ -int hl_mmu_init(struct hl_device *hdev) +static int hl_mmu_v1_init(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; int rc; - if (!hdev->mmu_enable) - return 0; - - hdev->mmu_pgt_pool = + hdev->mmu_priv.mmu_pgt_pool = gen_pool_create(__ffs(prop->mmu_hop_table_size), -1); - if (!hdev->mmu_pgt_pool) { + if (!hdev->mmu_priv.mmu_pgt_pool) { dev_err(hdev->dev, "Failed to create page gen pool\n"); return -ENOMEM; } - rc = gen_pool_add(hdev->mmu_pgt_pool, prop->mmu_pgt_addr + + rc = gen_pool_add(hdev->mmu_priv.mmu_pgt_pool, prop->mmu_pgt_addr + prop->mmu_hop0_tables_total_size, prop->mmu_pgt_size - prop->mmu_hop0_tables_total_size, -1); @@ -447,10 +436,10 @@ int hl_mmu_init(struct hl_device *hdev) goto err_pool_add; } - hdev->mmu_shadow_hop0 = kvmalloc_array(prop->max_asid, - prop->mmu_hop_table_size, - GFP_KERNEL | __GFP_ZERO); - if (ZERO_OR_NULL_PTR(hdev->mmu_shadow_hop0)) { + hdev->mmu_priv.mmu_shadow_hop0 = kvmalloc_array(prop->max_asid, + prop->mmu_hop_table_size, + GFP_KERNEL | __GFP_ZERO); + if (ZERO_OR_NULL_PTR(hdev->mmu_priv.mmu_shadow_hop0)) { rc = -ENOMEM; goto err_pool_add; } @@ -460,7 +449,7 @@ int hl_mmu_init(struct hl_device *hdev) return 0; err_pool_add: - gen_pool_destroy(hdev->mmu_pgt_pool); + gen_pool_destroy(hdev->mmu_priv.mmu_pgt_pool); return rc; } @@ -475,15 +464,12 @@ err_pool_add: * * All contexts should be freed before calling this function. */ -void hl_mmu_fini(struct hl_device *hdev) +static void hl_mmu_v1_fini(struct hl_device *hdev) { - if (!hdev->mmu_enable) - return; - /* MMU H/W fini was already done in device hw_fini() */ - kvfree(hdev->mmu_shadow_hop0); - gen_pool_destroy(hdev->mmu_pgt_pool); + kvfree(hdev->mmu_priv.mmu_shadow_hop0); + gen_pool_destroy(hdev->mmu_priv.mmu_pgt_pool); } /** @@ -494,13 +480,8 @@ void hl_mmu_fini(struct hl_device *hdev) * page tables hops related to this context. * Return: 0 on success, non-zero otherwise. */ -int hl_mmu_ctx_init(struct hl_ctx *ctx) +static int hl_mmu_v1_ctx_init(struct hl_ctx *ctx) { - struct hl_device *hdev = ctx->hdev; - - if (!hdev->mmu_enable) - return 0; - mutex_init(&ctx->mmu_lock); hash_init(ctx->mmu_shadow_hash); @@ -517,16 +498,13 @@ int hl_mmu_ctx_init(struct hl_ctx *ctx) * - Free the mutex * - Free DRAM default page mapping hops */ -void hl_mmu_ctx_fini(struct hl_ctx *ctx) +static void hl_mmu_v1_ctx_fini(struct hl_ctx *ctx) { struct hl_device *hdev = ctx->hdev; struct pgt_info *pgt_info; struct hlist_node *tmp; int i; - if (!hdev->mmu_enable) - return; - dram_default_mapping_fini(ctx); if (!hash_empty(ctx->mmu_shadow_hash)) @@ -543,7 +521,8 @@ void hl_mmu_ctx_fini(struct hl_ctx *ctx) mutex_destroy(&ctx->mmu_lock); } -static int _hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, bool is_dram_addr) +static int _hl_mmu_v1_unmap(struct hl_ctx *ctx, + u64 virt_addr, bool is_dram_addr) { struct hl_device *hdev = ctx->hdev; struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -676,82 +655,7 @@ not_mapped: return -EINVAL; } -/* - * hl_mmu_unmap - unmaps a virtual addr - * - * @ctx: pointer to the context structure - * @virt_addr: virt addr to map from - * @page_size: size of the page to unmap - * @flush_pte: whether to do a PCI flush - * - * This function does the following: - * - Check that the virt addr is mapped - * - Unmap the virt addr and frees pgts if possible - * - Returns 0 on success, -EINVAL if the given addr is not mapped - * - * Because this function changes the page tables in the device and because it - * changes the MMU hash, it must be protected by a lock. - * However, because it maps only a single page, the lock should be implemented - * in a higher level in order to protect the entire mapping of the memory area - * - * For optimization reasons PCI flush may be requested once after unmapping of - * large area. - */ -int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size, - bool flush_pte) -{ - struct hl_device *hdev = ctx->hdev; - struct asic_fixed_properties *prop = &hdev->asic_prop; - struct hl_mmu_properties *mmu_prop; - u64 real_virt_addr; - u32 real_page_size, npages; - int i, rc = 0; - bool is_dram_addr; - - if (!hdev->mmu_enable) - return 0; - - is_dram_addr = is_dram_va(hdev, virt_addr); - - if (is_dram_addr) - mmu_prop = &prop->dmmu; - else if ((page_size % prop->pmmu_huge.page_size) == 0) - mmu_prop = &prop->pmmu_huge; - else - mmu_prop = &prop->pmmu; - - /* - * The H/W handles mapping of specific page sizes. Hence if the page - * size is bigger, we break it to sub-pages and unmap them separately. - */ - if ((page_size % mmu_prop->page_size) == 0) { - real_page_size = mmu_prop->page_size; - } else { - dev_err(hdev->dev, - "page size of %u is not %uKB aligned, can't unmap\n", - page_size, mmu_prop->page_size >> 10); - - return -EFAULT; - } - - npages = page_size / real_page_size; - real_virt_addr = virt_addr; - - for (i = 0 ; i < npages ; i++) { - rc = _hl_mmu_unmap(ctx, real_virt_addr, is_dram_addr); - if (rc) - break; - - real_virt_addr += real_page_size; - } - - if (flush_pte) - flush(ctx); - - return rc; -} - -static int _hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, +static int _hl_mmu_v1_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size, bool is_dram_addr) { struct hl_device *hdev = ctx->hdev; @@ -917,121 +821,43 @@ err: } /* - * hl_mmu_map - maps a virtual addr to physical addr - * - * @ctx: pointer to the context structure - * @virt_addr: virt addr to map from - * @phys_addr: phys addr to map to - * @page_size: physical page size - * @flush_pte: whether to do a PCI flush - * - * This function does the following: - * - Check that the virt addr is not mapped - * - Allocate pgts as necessary in order to map the virt addr to the phys - * - Returns 0 on success, -EINVAL if addr is already mapped, or -ENOMEM. - * - * Because this function changes the page tables in the device and because it - * changes the MMU hash, it must be protected by a lock. - * However, because it maps only a single page, the lock should be implemented - * in a higher level in order to protect the entire mapping of the memory area - * - * For optimization reasons PCI flush may be requested once after mapping of - * large area. - */ -int hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size, - bool flush_pte) -{ - struct hl_device *hdev = ctx->hdev; - struct asic_fixed_properties *prop = &hdev->asic_prop; - struct hl_mmu_properties *mmu_prop; - u64 real_virt_addr, real_phys_addr; - u32 real_page_size, npages; - int i, rc, mapped_cnt = 0; - bool is_dram_addr; - - if (!hdev->mmu_enable) - return 0; - - is_dram_addr = is_dram_va(hdev, virt_addr); - - if (is_dram_addr) - mmu_prop = &prop->dmmu; - else if ((page_size % prop->pmmu_huge.page_size) == 0) - mmu_prop = &prop->pmmu_huge; - else - mmu_prop = &prop->pmmu; - - /* - * The H/W handles mapping of specific page sizes. Hence if the page - * size is bigger, we break it to sub-pages and map them separately. - */ - if ((page_size % mmu_prop->page_size) == 0) { - real_page_size = mmu_prop->page_size; - } else { - dev_err(hdev->dev, - "page size of %u is not %uKB aligned, can't unmap\n", - page_size, mmu_prop->page_size >> 10); - - return -EFAULT; - } - - WARN_ONCE((phys_addr & (real_page_size - 1)), - "Mapping 0x%llx with page size of 0x%x is erroneous! Address must be divisible by page size", - phys_addr, real_page_size); - - npages = page_size / real_page_size; - real_virt_addr = virt_addr; - real_phys_addr = phys_addr; - - for (i = 0 ; i < npages ; i++) { - rc = _hl_mmu_map(ctx, real_virt_addr, real_phys_addr, - real_page_size, is_dram_addr); - if (rc) - goto err; - - real_virt_addr += real_page_size; - real_phys_addr += real_page_size; - mapped_cnt++; - } - - if (flush_pte) - flush(ctx); - - return 0; - -err: - real_virt_addr = virt_addr; - for (i = 0 ; i < mapped_cnt ; i++) { - if (_hl_mmu_unmap(ctx, real_virt_addr, is_dram_addr)) - dev_warn_ratelimited(hdev->dev, - "failed to unmap va: 0x%llx\n", real_virt_addr); - - real_virt_addr += real_page_size; - } - - flush(ctx); - - return rc; -} - -/* - * hl_mmu_swap_out - marks all mapping of the given ctx as swapped out + * hl_mmu_v1_swap_out - marks all mapping of the given ctx as swapped out * * @ctx: pointer to the context structure * */ -void hl_mmu_swap_out(struct hl_ctx *ctx) +static void hl_mmu_v1_swap_out(struct hl_ctx *ctx) { } /* - * hl_mmu_swap_in - marks all mapping of the given ctx as swapped in + * hl_mmu_v1_swap_in - marks all mapping of the given ctx as swapped in * * @ctx: pointer to the context structure * */ -void hl_mmu_swap_in(struct hl_ctx *ctx) +static void hl_mmu_v1_swap_in(struct hl_ctx *ctx) { } + +/* + * hl_mmu_v1_prepare - prepare mmu for working with mmu v1 + * + * @hdev: pointer to the device structure + */ +void hl_mmu_v1_set_funcs(struct hl_device *hdev) +{ + struct hl_mmu_funcs *mmu = &hdev->mmu_func; + + mmu->init = hl_mmu_v1_init; + mmu->fini = hl_mmu_v1_fini; + mmu->ctx_init = hl_mmu_v1_ctx_init; + mmu->ctx_fini = hl_mmu_v1_ctx_fini; + mmu->map = _hl_mmu_v1_map; + mmu->unmap = _hl_mmu_v1_unmap; + mmu->flush = flush; + mmu->swap_out = hl_mmu_v1_swap_out; + mmu->swap_in = hl_mmu_v1_swap_in; +} From 7edf341b9ef5012408a2ddac7ba30bc94e1dffaf Mon Sep 17 00:00:00 2001 From: Moti Haimovski Date: Sun, 23 Aug 2020 13:23:13 +0300 Subject: [PATCH 35/46] habanalabs: add num_hops to hl_mmu_properties This commit adds the number of HOPs supported by the device to the device MMU properties. Signed-off-by: Moti Haimovski Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/habanalabs.h | 6 ++++++ drivers/misc/habanalabs/gaudi/gaudi.c | 1 + drivers/misc/habanalabs/goya/goya.c | 2 ++ drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h | 2 ++ 4 files changed, 11 insertions(+) diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 15e746a5fe35..8ef61926ed3b 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -236,12 +236,15 @@ enum hl_device_hw_state { * @hop2_shift: shift of hop 2 mask. * @hop3_shift: shift of hop 3 mask. * @hop4_shift: shift of hop 4 mask. + * @hop5_shift: shift of hop 5 mask. * @hop0_mask: mask to get the PTE address in hop 0. * @hop1_mask: mask to get the PTE address in hop 1. * @hop2_mask: mask to get the PTE address in hop 2. * @hop3_mask: mask to get the PTE address in hop 3. * @hop4_mask: mask to get the PTE address in hop 4. + * @hop5_mask: mask to get the PTE address in hop 5. * @page_size: default page size used to allocate memory. + * @num_hops: The amount of hops supported by the translation table. */ struct hl_mmu_properties { u64 start_addr; @@ -251,12 +254,15 @@ struct hl_mmu_properties { u64 hop2_shift; u64 hop3_shift; u64 hop4_shift; + u64 hop5_shift; u64 hop0_mask; u64 hop1_mask; u64 hop2_mask; u64 hop3_mask; u64 hop4_mask; + u64 hop5_mask; u32 page_size; + u32 num_hops; }; /** diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 483989500863..bf010ff31ced 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -441,6 +441,7 @@ static int gaudi_get_fixed_properties(struct hl_device *hdev) prop->pmmu.end_addr = (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1; prop->pmmu.page_size = PAGE_SIZE_4KB; + prop->pmmu.num_hops = MMU_ARCH_5_HOPS; /* PMMU and HPMMU are the same except of page size */ memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 46a900fb3ef8..6f831cc54d37 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -426,12 +426,14 @@ int goya_get_fixed_properties(struct hl_device *hdev) prop->dmmu.start_addr = VA_DDR_SPACE_START; prop->dmmu.end_addr = VA_DDR_SPACE_END; prop->dmmu.page_size = PAGE_SIZE_2MB; + prop->dmmu.num_hops = MMU_ARCH_5_HOPS; /* shifts and masks are the same in PMMU and DMMU */ memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu)); prop->pmmu.start_addr = VA_HOST_SPACE_START; prop->pmmu.end_addr = VA_HOST_SPACE_END; prop->pmmu.page_size = PAGE_SIZE_4KB; + prop->pmmu.num_hops = MMU_ARCH_5_HOPS; /* PMMU and HPMMU are the same except of page size */ memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h index 468bb045fbd1..dedf20e8f956 100644 --- a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h @@ -29,6 +29,8 @@ #define HOP3_SHIFT 21 #define HOP4_SHIFT 12 +#define MMU_ARCH_5_HOPS 5 + #define HOP_PHYS_ADDR_MASK (~FLAGS_MASK) #define HL_PTE_SIZE sizeof(u64) From 214afa974dd40a100765d912d005193d4907e0f0 Mon Sep 17 00:00:00 2001 From: Moti Haimovski Date: Thu, 13 Aug 2020 16:54:50 +0300 Subject: [PATCH 36/46] habanalabs: add debugfs support for MMU with 6 HOPs This commit modify the existing debugfs code to support future devices that have a 6 HOPs MMU implementation instead of 5 HOPs implementation. Signed-off-by: Moti Haimovski Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/debugfs.c | 70 ++++++++++++++++++++---- 1 file changed, 60 insertions(+), 10 deletions(-) diff --git a/drivers/misc/habanalabs/common/debugfs.c b/drivers/misc/habanalabs/common/debugfs.c index c27c0f94c97a..5d4665d2a0fb 100644 --- a/drivers/misc/habanalabs/common/debugfs.c +++ b/drivers/misc/habanalabs/common/debugfs.c @@ -354,6 +354,14 @@ static inline u64 get_hop4_pte_addr(struct hl_ctx *ctx, mmu_specs->hop4_shift); } +static inline u64 get_hop5_pte_addr(struct hl_ctx *ctx, + struct hl_mmu_properties *mmu_specs, + u64 hop_addr, u64 vaddr) +{ + return get_hopN_pte_addr(ctx, hop_addr, vaddr, mmu_specs->hop5_mask, + mmu_specs->hop5_shift); +} + static inline u64 get_next_hop_addr(u64 curr_pte) { if (curr_pte & PAGE_PRESENT_MASK) @@ -377,6 +385,7 @@ static int mmu_show(struct seq_file *s, void *data) hop2_addr = 0, hop2_pte_addr = 0, hop2_pte = 0, hop3_addr = 0, hop3_pte_addr = 0, hop3_pte = 0, hop4_addr = 0, hop4_pte_addr = 0, hop4_pte = 0, + hop5_addr = 0, hop5_pte_addr = 0, hop5_pte = 0, virt_addr = dev_entry->mmu_addr; if (!hdev->mmu_enable) @@ -428,20 +437,49 @@ static int mmu_show(struct seq_file *s, void *data) hop3_pte_addr = get_hop3_pte_addr(ctx, mmu_prop, hop3_addr, virt_addr); hop3_pte = hdev->asic_funcs->read_pte(hdev, hop3_pte_addr); - if (!(hop3_pte & LAST_MASK)) { + if (mmu_prop->num_hops == MMU_ARCH_5_HOPS) { + if (!(hop3_pte & LAST_MASK)) { + hop4_addr = get_next_hop_addr(hop3_pte); + + if (hop4_addr == ULLONG_MAX) + goto not_mapped; + + hop4_pte_addr = get_hop4_pte_addr(ctx, mmu_prop, + hop4_addr, virt_addr); + hop4_pte = hdev->asic_funcs->read_pte(hdev, + hop4_pte_addr); + if (!(hop4_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + } else { + if (!(hop3_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + } + } else { hop4_addr = get_next_hop_addr(hop3_pte); if (hop4_addr == ULLONG_MAX) goto not_mapped; - hop4_pte_addr = get_hop4_pte_addr(ctx, mmu_prop, hop4_addr, - virt_addr); - hop4_pte = hdev->asic_funcs->read_pte(hdev, hop4_pte_addr); - if (!(hop4_pte & PAGE_PRESENT_MASK)) - goto not_mapped; - } else { - if (!(hop3_pte & PAGE_PRESENT_MASK)) - goto not_mapped; + hop4_pte_addr = get_hop4_pte_addr(ctx, mmu_prop, + hop4_addr, virt_addr); + hop4_pte = hdev->asic_funcs->read_pte(hdev, + hop4_pte_addr); + if (!(hop4_pte & LAST_MASK)) { + hop5_addr = get_next_hop_addr(hop4_pte); + + if (hop5_addr == ULLONG_MAX) + goto not_mapped; + + hop5_pte_addr = get_hop5_pte_addr(ctx, mmu_prop, + hop5_addr, virt_addr); + hop5_pte = hdev->asic_funcs->read_pte(hdev, + hop5_pte_addr); + if (!(hop5_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + } else { + if (!(hop4_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + } } seq_printf(s, "asid: %u, virt_addr: 0x%llx\n", @@ -463,10 +501,22 @@ static int mmu_show(struct seq_file *s, void *data) seq_printf(s, "hop3_pte_addr: 0x%llx\n", hop3_pte_addr); seq_printf(s, "hop3_pte: 0x%llx\n", hop3_pte); - if (!(hop3_pte & LAST_MASK)) { + if (mmu_prop->num_hops == MMU_ARCH_5_HOPS) { + if (!(hop3_pte & LAST_MASK)) { + seq_printf(s, "hop4_addr: 0x%llx\n", hop4_addr); + seq_printf(s, "hop4_pte_addr: 0x%llx\n", hop4_pte_addr); + seq_printf(s, "hop4_pte: 0x%llx\n", hop4_pte); + } + } else { seq_printf(s, "hop4_addr: 0x%llx\n", hop4_addr); seq_printf(s, "hop4_pte_addr: 0x%llx\n", hop4_pte_addr); seq_printf(s, "hop4_pte: 0x%llx\n", hop4_pte); + + if (!(hop4_pte & LAST_MASK)) { + seq_printf(s, "hop5_addr: 0x%llx\n", hop5_addr); + seq_printf(s, "hop5_pte_addr: 0x%llx\n", hop5_pte_addr); + seq_printf(s, "hop5_pte: 0x%llx\n", hop5_pte); + } } goto out; From 230b9b7d45b6d466afd1b6e82dddc252756c5c9c Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Tue, 8 Sep 2020 15:17:03 +0300 Subject: [PATCH 37/46] habanalabs/gaudi: increase timeout for boot fit load The firmware running in the boot stage takes more time to execute due to increased security mechanisms. Therefore, we need to increase the timeout we wait for the boot fit to finish loading. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudiP.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudiP.h b/drivers/misc/habanalabs/gaudi/gaudiP.h index dd222bc128f9..b70b810c21c9 100644 --- a/drivers/misc/habanalabs/gaudi/gaudiP.h +++ b/drivers/misc/habanalabs/gaudi/gaudiP.h @@ -42,7 +42,7 @@ #define MAX_POWER_DEFAULT_PCI 200000 /* 200W */ #define MAX_POWER_DEFAULT_PMC 350000 /* 350W */ -#define GAUDI_CPU_TIMEOUT_USEC 15000000 /* 15s */ +#define GAUDI_CPU_TIMEOUT_USEC 30000000 /* 30s */ #define TPC_ENABLED_MASK 0xFF From 681a22f55f1506023da06ebf660a4a252b35bc93 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Mon, 7 Sep 2020 18:08:51 +0300 Subject: [PATCH 38/46] habanalabs: allow to wait on CS without sleep The user sometimes wants to check if a CS has completed to clean resources. In that case, the user doesn't want to sleep but just to check if the CS has finished and continue with his code. Add a new definition to the API of the wait on CS. The new definition says that if the timeout is 0, the driver won't sleep at all but return immediately after checking if the CS has finished. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/command_submission.c | 7 +++++-- include/uapi/misc/habanalabs.h | 3 +++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_submission.c b/drivers/misc/habanalabs/common/command_submission.c index 470bffbe9bdc..b2b974ecc431 100644 --- a/drivers/misc/habanalabs/common/command_submission.c +++ b/drivers/misc/habanalabs/common/command_submission.c @@ -1180,8 +1180,11 @@ static long _hl_cs_wait_ioctl(struct hl_device *hdev, "Can't wait on CS %llu because current CS is at seq %llu\n", seq, ctx->cs_sequence); } else if (fence) { - rc = wait_for_completion_interruptible_timeout( - &fence->completion, timeout); + if (!timeout_us) + rc = completion_done(&fence->completion); + else + rc = wait_for_completion_interruptible_timeout( + &fence->completion, timeout); if (fence->error == -ETIMEDOUT) rc = -ETIMEDOUT; diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index 69fb44d35292..d449f8a31ce6 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -914,6 +914,9 @@ struct hl_debug_args { * inside the kernel until the CS has finished or until the user-requested * timeout has expired. * + * If the timeout value is 0, the driver won't sleep at all. It will check + * the status of the CS and return immediately + * * The return value of the IOCTL is a standard Linux error code. The possible * values are: * From 448f63badcac6e24031cbfd6952245d02c38fa84 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 9 Sep 2020 10:39:00 +0300 Subject: [PATCH 39/46] habanalabs: no need for DMA_SHARED_BUFFER Now that the driver no longer uses dma_buf, we can remove the select of DMA_SHARED_BUFFER from kconfig. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/misc/habanalabs/Kconfig b/drivers/misc/habanalabs/Kconfig index 8eb5d38c618e..1640340d3e62 100644 --- a/drivers/misc/habanalabs/Kconfig +++ b/drivers/misc/habanalabs/Kconfig @@ -7,7 +7,6 @@ config HABANA_AI tristate "HabanaAI accelerators (habanalabs)" depends on PCI && HAS_IOMEM select FRAME_VECTOR - select DMA_SHARED_BUFFER select GENERIC_ALLOCATOR select HWMON help From fa8641a14f2841e1712e554ebfa58f1ac7b7db1b Mon Sep 17 00:00:00 2001 From: Tomer Tayar Date: Mon, 7 Sep 2020 17:36:41 +0300 Subject: [PATCH 40/46] habanalabs: Save context in a command buffer object Future changes require using a context while handling a command buffer, and thus need to save the context in the command buffer object. Signed-off-by: Tomer Tayar Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../misc/habanalabs/common/command_buffer.c | 22 +++++++++++-------- drivers/misc/habanalabs/common/debugfs.c | 2 +- drivers/misc/habanalabs/common/habanalabs.h | 9 ++++---- drivers/misc/habanalabs/gaudi/gaudi.c | 10 +++++---- drivers/misc/habanalabs/goya/goya.c | 10 +++++---- 5 files changed, 31 insertions(+), 22 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_buffer.c b/drivers/misc/habanalabs/common/command_buffer.c index ba63cee74050..0cb556fb4a8b 100644 --- a/drivers/misc/habanalabs/common/command_buffer.c +++ b/drivers/misc/habanalabs/common/command_buffer.c @@ -47,6 +47,8 @@ static void cb_release(struct kref *ref) hl_debugfs_remove_cb(cb); + hl_ctx_put(cb->ctx); + cb_do_release(hdev, cb); } @@ -107,11 +109,12 @@ static struct hl_cb *hl_cb_alloc(struct hl_device *hdev, u32 cb_size, } int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, - u32 cb_size, u64 *handle, int ctx_id, bool internal_cb) + struct hl_ctx *ctx, u32 cb_size, bool internal_cb, + u64 *handle) { struct hl_cb *cb; bool alloc_new_cb = true; - int rc; + int rc, ctx_id = ctx->asid; /* * Can't use generic function to check this because of special case @@ -163,7 +166,8 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, } cb->hdev = hdev; - cb->ctx_id = ctx_id; + cb->ctx = ctx; + hl_ctx_get(hdev, cb->ctx); spin_lock(&mgr->cb_lock); rc = idr_alloc(&mgr->cb_handles, cb, 1, 0, GFP_ATOMIC); @@ -191,6 +195,7 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, return 0; release_cb: + hl_ctx_put(cb->ctx); cb_do_release(hdev, cb); out_err: *handle = 0; @@ -250,9 +255,8 @@ int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data) args->in.cb_size, HL_MAX_CB_SIZE); rc = -EINVAL; } else { - rc = hl_cb_create(hdev, &hpriv->cb_mgr, - args->in.cb_size, &handle, - hpriv->ctx->asid, false); + rc = hl_cb_create(hdev, &hpriv->cb_mgr, hpriv->ctx, + args->in.cb_size, false, &handle); } memset(args, 0, sizeof(*args)); @@ -424,7 +428,7 @@ void hl_cb_mgr_fini(struct hl_device *hdev, struct hl_cb_mgr *mgr) if (kref_put(&cb->refcount, cb_release) != 1) dev_err(hdev->dev, "CB %d for CTX ID %d is still alive\n", - id, cb->ctx_id); + id, cb->ctx->asid); } idr_destroy(&mgr->cb_handles); @@ -437,8 +441,8 @@ struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size, struct hl_cb *cb; int rc; - rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, cb_size, &cb_handle, - HL_KERNEL_ASID_ID, internal_cb); + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, cb_size, + internal_cb, &cb_handle); if (rc) { dev_err(hdev->dev, "Failed to allocate CB for the kernel driver %d\n", rc); diff --git a/drivers/misc/habanalabs/common/debugfs.c b/drivers/misc/habanalabs/common/debugfs.c index 5d4665d2a0fb..912ddfa360b1 100644 --- a/drivers/misc/habanalabs/common/debugfs.c +++ b/drivers/misc/habanalabs/common/debugfs.c @@ -111,7 +111,7 @@ static int command_buffers_show(struct seq_file *s, void *data) } seq_printf(s, " %03llu %d 0x%08x %d %d %d\n", - cb->id, cb->ctx_id, cb->size, + cb->id, cb->ctx->asid, cb->size, kref_read(&cb->refcount), cb->mmap, cb->cs_cnt); } diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 8ef61926ed3b..88c68b664ef6 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -417,6 +417,7 @@ struct hl_cb_mgr { * struct hl_cb - describes a Command Buffer. * @refcount: reference counter for usage of the CB. * @hdev: pointer to device this CB belongs to. + * @ctx: pointer to the CB owner's context. * @lock: spinlock to protect mmap/cs flows. * @debugfs_list: node in debugfs list of command buffers. * @pool_list: node in pool list of command buffers. @@ -426,7 +427,6 @@ struct hl_cb_mgr { * @mmap_size: Holds the CB's size that was mmaped. * @size: holds the CB's size. * @cs_cnt: holds number of CS that this CB participates in. - * @ctx_id: holds the ID of the owner's context. * @mmap: true if the CB is currently mmaped to user. * @is_pool: true if CB was acquired from the pool, false otherwise. * @is_internal: internaly allocated @@ -434,6 +434,7 @@ struct hl_cb_mgr { struct hl_cb { struct kref refcount; struct hl_device *hdev; + struct hl_ctx *ctx; spinlock_t lock; struct list_head debugfs_list; struct list_head pool_list; @@ -443,7 +444,6 @@ struct hl_cb { u32 mmap_size; u32 size; u32 cs_cnt; - u32 ctx_id; u8 mmap; u8 is_pool; u8 is_internal; @@ -1838,8 +1838,9 @@ void hl_sysfs_fini(struct hl_device *hdev); int hl_hwmon_init(struct hl_device *hdev); void hl_hwmon_fini(struct hl_device *hdev); -int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, u32 cb_size, - u64 *handle, int ctx_id, bool internal_cb); +int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, + struct hl_ctx *ctx, u32 cb_size, bool internal_cb, + u64 *handle); int hl_cb_destroy(struct hl_device *hdev, struct hl_cb_mgr *mgr, u64 cb_handle); int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma); struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr, diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index bf010ff31ced..b51cc6c1d541 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -4114,8 +4114,9 @@ static int gaudi_parse_cb_mmu(struct hl_device *hdev, parser->patched_cb_size = parser->user_cb_size + sizeof(struct packet_msg_prot) * 2; - rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, parser->patched_cb_size, - &patched_cb_handle, HL_KERNEL_ASID_ID, false); + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, + parser->patched_cb_size, false, + &patched_cb_handle); if (rc) { dev_err(hdev->dev, @@ -4187,8 +4188,9 @@ static int gaudi_parse_cb_no_mmu(struct hl_device *hdev, if (rc) goto free_userptr; - rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, parser->patched_cb_size, - &patched_cb_handle, HL_KERNEL_ASID_ID, false); + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, + parser->patched_cb_size, false, + &patched_cb_handle); if (rc) { dev_err(hdev->dev, "Failed to allocate patched CB for DMA CS %d\n", rc); diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 6f831cc54d37..6c81a4b148de 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -3810,8 +3810,9 @@ static int goya_parse_cb_mmu(struct hl_device *hdev, parser->patched_cb_size = parser->user_cb_size + sizeof(struct packet_msg_prot) * 2; - rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, parser->patched_cb_size, - &patched_cb_handle, HL_KERNEL_ASID_ID, false); + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, + parser->patched_cb_size, false, + &patched_cb_handle); if (rc) { dev_err(hdev->dev, @@ -3883,8 +3884,9 @@ static int goya_parse_cb_no_mmu(struct hl_device *hdev, if (rc) goto free_userptr; - rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, parser->patched_cb_size, - &patched_cb_handle, HL_KERNEL_ASID_ID, false); + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, + parser->patched_cb_size, false, + &patched_cb_handle); if (rc) { dev_err(hdev->dev, "Failed to allocate patched CB for DMA CS %d\n", rc); From ef6a0f6caa4a5dbfbb42b642e23fb06182798d30 Mon Sep 17 00:00:00 2001 From: Tomer Tayar Date: Thu, 9 Jul 2020 16:17:48 +0300 Subject: [PATCH 41/46] habanalabs: Add an option to map CB to device MMU There are cases in which the device should access the host memory of a CB through the device MMU, and thus this memory should be mapped. The patch adds a flag to the CB IOCTL, in which a user can ask the driver to perform the mapping when creating a CB. The mapping is allowed only if a dedicated VA range was allocated for the specific ASIC. Signed-off-by: Tomer Tayar Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- .../misc/habanalabs/common/command_buffer.c | 196 +++++++++++++++++- drivers/misc/habanalabs/common/context.c | 12 +- drivers/misc/habanalabs/common/habanalabs.h | 20 +- drivers/misc/habanalabs/gaudi/gaudi.c | 4 +- drivers/misc/habanalabs/goya/goya.c | 4 +- include/uapi/misc/habanalabs.h | 12 +- 6 files changed, 237 insertions(+), 11 deletions(-) diff --git a/drivers/misc/habanalabs/common/command_buffer.c b/drivers/misc/habanalabs/common/command_buffer.c index 0cb556fb4a8b..901e213daf40 100644 --- a/drivers/misc/habanalabs/common/command_buffer.c +++ b/drivers/misc/habanalabs/common/command_buffer.c @@ -13,6 +13,131 @@ #include #include +static int cb_map_mem(struct hl_ctx *ctx, struct hl_cb *cb) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_vm_va_block *va_block, *tmp; + dma_addr_t bus_addr; + u64 virt_addr; + u32 page_size = prop->pmmu.page_size; + s32 offset; + int rc; + + if (!hdev->supports_cb_mapping) { + dev_err_ratelimited(hdev->dev, + "Cannot map CB because no VA range is allocated for CB mapping\n"); + return -EINVAL; + } + + if (!hdev->mmu_enable) { + dev_err_ratelimited(hdev->dev, + "Cannot map CB because MMU is disabled\n"); + return -EINVAL; + } + + INIT_LIST_HEAD(&cb->va_block_list); + + for (bus_addr = cb->bus_address; + bus_addr < cb->bus_address + cb->size; + bus_addr += page_size) { + + virt_addr = (u64) gen_pool_alloc(ctx->cb_va_pool, page_size); + if (!virt_addr) { + dev_err(hdev->dev, + "Failed to allocate device virtual address for CB\n"); + rc = -ENOMEM; + goto err_va_pool_free; + } + + va_block = kzalloc(sizeof(*va_block), GFP_KERNEL); + if (!va_block) { + rc = -ENOMEM; + gen_pool_free(ctx->cb_va_pool, virt_addr, page_size); + goto err_va_pool_free; + } + + va_block->start = virt_addr; + va_block->end = virt_addr + page_size; + va_block->size = page_size; + list_add_tail(&va_block->node, &cb->va_block_list); + } + + mutex_lock(&ctx->mmu_lock); + + bus_addr = cb->bus_address; + offset = 0; + list_for_each_entry(va_block, &cb->va_block_list, node) { + rc = hl_mmu_map(ctx, va_block->start, bus_addr, va_block->size, + list_is_last(&va_block->node, + &cb->va_block_list)); + if (rc) { + dev_err(hdev->dev, "Failed to map VA %#llx to CB\n", + va_block->start); + goto err_va_umap; + } + + bus_addr += va_block->size; + offset += va_block->size; + } + + hdev->asic_funcs->mmu_invalidate_cache(hdev, false, VM_TYPE_USERPTR); + + mutex_unlock(&ctx->mmu_lock); + + cb->is_mmu_mapped = true; + + return 0; + +err_va_umap: + list_for_each_entry(va_block, &cb->va_block_list, node) { + if (offset <= 0) + break; + hl_mmu_unmap(ctx, va_block->start, va_block->size, + offset <= va_block->size); + offset -= va_block->size; + } + + hdev->asic_funcs->mmu_invalidate_cache(hdev, true, VM_TYPE_USERPTR); + + mutex_unlock(&ctx->mmu_lock); + +err_va_pool_free: + list_for_each_entry_safe(va_block, tmp, &cb->va_block_list, node) { + gen_pool_free(ctx->cb_va_pool, va_block->start, va_block->size); + list_del(&va_block->node); + kfree(va_block); + } + + return rc; +} + +static void cb_unmap_mem(struct hl_ctx *ctx, struct hl_cb *cb) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm_va_block *va_block, *tmp; + + mutex_lock(&ctx->mmu_lock); + + list_for_each_entry(va_block, &cb->va_block_list, node) + if (hl_mmu_unmap(ctx, va_block->start, va_block->size, + list_is_last(&va_block->node, + &cb->va_block_list))) + dev_warn_ratelimited(hdev->dev, + "Failed to unmap CB's va 0x%llx\n", + va_block->start); + + hdev->asic_funcs->mmu_invalidate_cache(hdev, true, VM_TYPE_USERPTR); + + mutex_unlock(&ctx->mmu_lock); + + list_for_each_entry_safe(va_block, tmp, &cb->va_block_list, node) { + gen_pool_free(ctx->cb_va_pool, va_block->start, va_block->size); + list_del(&va_block->node); + kfree(va_block); + } +} + static void cb_fini(struct hl_device *hdev, struct hl_cb *cb) { if (cb->is_internal) @@ -47,6 +172,9 @@ static void cb_release(struct kref *ref) hl_debugfs_remove_cb(cb); + if (cb->is_mmu_mapped) + cb_unmap_mem(cb->ctx, cb); + hl_ctx_put(cb->ctx); cb_do_release(hdev, cb); @@ -110,7 +238,7 @@ static struct hl_cb *hl_cb_alloc(struct hl_device *hdev, u32 cb_size, int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, struct hl_ctx *ctx, u32 cb_size, bool internal_cb, - u64 *handle) + bool map_cb, u64 *handle) { struct hl_cb *cb; bool alloc_new_cb = true; @@ -169,13 +297,26 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, cb->ctx = ctx; hl_ctx_get(hdev, cb->ctx); + if (map_cb) { + if (ctx_id == HL_KERNEL_ASID_ID) { + dev_err(hdev->dev, + "CB mapping is not supported for kernel context\n"); + rc = -EINVAL; + goto release_cb; + } + + rc = cb_map_mem(ctx, cb); + if (rc) + goto release_cb; + } + spin_lock(&mgr->cb_lock); rc = idr_alloc(&mgr->cb_handles, cb, 1, 0, GFP_ATOMIC); spin_unlock(&mgr->cb_lock); if (rc < 0) { dev_err(hdev->dev, "Failed to allocate IDR for a new CB\n"); - goto release_cb; + goto unmap_mem; } cb->id = (u64) rc; @@ -194,6 +335,9 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, return 0; +unmap_mem: + if (cb->is_mmu_mapped) + cb_unmap_mem(cb->ctx, cb); release_cb: hl_ctx_put(cb->ctx); cb_do_release(hdev, cb); @@ -256,7 +400,9 @@ int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data) rc = -EINVAL; } else { rc = hl_cb_create(hdev, &hpriv->cb_mgr, hpriv->ctx, - args->in.cb_size, false, &handle); + args->in.cb_size, false, + !!(args->in.flags & HL_CB_FLAGS_MAP), + &handle); } memset(args, 0, sizeof(*args)); @@ -442,7 +588,7 @@ struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size, int rc; rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, cb_size, - internal_cb, &cb_handle); + internal_cb, false, &cb_handle); if (rc) { dev_err(hdev->dev, "Failed to allocate CB for the kernel driver %d\n", rc); @@ -498,3 +644,45 @@ int hl_cb_pool_fini(struct hl_device *hdev) return 0; } + +int hl_cb_va_pool_init(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc; + + if (!hdev->supports_cb_mapping) + return 0; + + ctx->cb_va_pool = gen_pool_create(__ffs(prop->pmmu.page_size), -1); + if (!ctx->cb_va_pool) { + dev_err(hdev->dev, + "Failed to create VA gen pool for CB mapping\n"); + return -ENOMEM; + } + + rc = gen_pool_add(ctx->cb_va_pool, prop->cb_va_start_addr, + prop->cb_va_end_addr - prop->cb_va_start_addr, -1); + if (rc) { + dev_err(hdev->dev, + "Failed to add memory to VA gen pool for CB mapping\n"); + goto err_pool_destroy; + } + + return 0; + +err_pool_destroy: + gen_pool_destroy(ctx->cb_va_pool); + + return rc; +} + +void hl_cb_va_pool_fini(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + + if (!hdev->supports_cb_mapping) + return; + + gen_pool_destroy(ctx->cb_va_pool); +} diff --git a/drivers/misc/habanalabs/common/context.c b/drivers/misc/habanalabs/common/context.c index b168a9fce817..df8171a2226c 100644 --- a/drivers/misc/habanalabs/common/context.c +++ b/drivers/misc/habanalabs/common/context.c @@ -37,6 +37,7 @@ static void hl_ctx_fini(struct hl_ctx *ctx) if ((hdev->in_debug) && (hdev->compute_ctx == ctx)) hl_device_set_debug_mode(hdev, false); + hl_cb_va_pool_fini(ctx); hl_vm_ctx_fini(ctx); hl_asid_free(hdev, ctx->asid); } else { @@ -155,15 +156,24 @@ int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx) goto err_asid_free; } + rc = hl_cb_va_pool_init(ctx); + if (rc) { + dev_err(hdev->dev, + "Failed to init VA pool for mapped CB\n"); + goto err_vm_ctx_fini; + } + rc = hdev->asic_funcs->ctx_init(ctx); if (rc) { dev_err(hdev->dev, "ctx_init failed\n"); - goto err_vm_ctx_fini; + goto err_cb_va_pool_fini; } } return 0; +err_cb_va_pool_fini: + hl_cb_va_pool_fini(ctx); err_vm_ctx_fini: hl_vm_ctx_fini(ctx); err_asid_free: diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 88c68b664ef6..eaa9bf3f82a3 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -291,6 +291,10 @@ struct hl_mmu_properties { * @pcie_aux_dbi_reg_addr: Address of the PCIE_AUX DBI register. * @mmu_pgt_addr: base physical address in DRAM of MMU page tables. * @mmu_dram_default_page_addr: DRAM default page physical address. + * @cb_va_start_addr: virtual start address of command buffers which are mapped + * to the device's MMU. + * @cb_va_end_addr: virtual end address of command buffers which are mapped to + * the device's MMU. * @mmu_pgt_size: MMU page tables total size. * @mmu_pte_size: PTE size in MMU page tables. * @mmu_hop_table_size: MMU hop table size. @@ -339,6 +343,8 @@ struct asic_fixed_properties { u64 pcie_aux_dbi_reg_addr; u64 mmu_pgt_addr; u64 mmu_dram_default_page_addr; + u64 cb_va_start_addr; + u64 cb_va_end_addr; u32 mmu_pgt_size; u32 mmu_pte_size; u32 mmu_hop_table_size; @@ -421,6 +427,8 @@ struct hl_cb_mgr { * @lock: spinlock to protect mmap/cs flows. * @debugfs_list: node in debugfs list of command buffers. * @pool_list: node in pool list of command buffers. + * @va_block_list: list of virtual addresses blocks of the CB if it is mapped to + * the device's MMU. * @id: the CB's ID. * @kernel_address: Holds the CB's kernel virtual address. * @bus_address: Holds the CB's DMA address. @@ -430,6 +438,7 @@ struct hl_cb_mgr { * @mmap: true if the CB is currently mmaped to user. * @is_pool: true if CB was acquired from the pool, false otherwise. * @is_internal: internaly allocated + * @is_mmu_mapped: true if the CB is mapped to the device's MMU. */ struct hl_cb { struct kref refcount; @@ -438,6 +447,7 @@ struct hl_cb { spinlock_t lock; struct list_head debugfs_list; struct list_head pool_list; + struct list_head va_block_list; u64 id; u64 kernel_address; dma_addr_t bus_address; @@ -447,6 +457,7 @@ struct hl_cb { u8 mmap; u8 is_pool; u8 is_internal; + u8 is_mmu_mapped; }; @@ -843,6 +854,8 @@ struct hl_va_range { * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifying the * MMU hash or walking the PGT requires talking this lock. * @debugfs_list: node in debugfs list of contexts. + * @cb_va_pool: device VA pool for command buffers which are mapped to the + * device's MMU. * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed * to user so user could inquire about CS. It is used as * index to cs_pending array. @@ -874,6 +887,7 @@ struct hl_ctx { struct mutex mmu_lock; struct list_head debugfs_list; struct hl_cs_counters cs_counters; + struct gen_pool *cb_va_pool; u64 cs_sequence; u64 *dram_default_hops; spinlock_t cs_lock; @@ -1574,6 +1588,7 @@ struct hl_mmu_funcs { * @sync_stream_queue_idx: helper index for sync stream queues initialization. * @supports_coresight: is CoreSight supported. * @supports_soft_reset: is soft reset supported. + * @supports_cb_mapping: is mapping a CB to the device's MMU supported. */ struct hl_device { struct pci_dev *pdev; @@ -1673,6 +1688,7 @@ struct hl_device { u8 sync_stream_queue_idx; u8 supports_coresight; u8 supports_soft_reset; + u8 supports_cb_mapping; /* Parameters for bring-up */ u8 mmu_enable; @@ -1840,7 +1856,7 @@ void hl_hwmon_fini(struct hl_device *hdev); int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, struct hl_ctx *ctx, u32 cb_size, bool internal_cb, - u64 *handle); + bool map_cb, u64 *handle); int hl_cb_destroy(struct hl_device *hdev, struct hl_cb_mgr *mgr, u64 cb_handle); int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma); struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr, @@ -1852,6 +1868,8 @@ struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size, bool internal_cb); int hl_cb_pool_init(struct hl_device *hdev); int hl_cb_pool_fini(struct hl_device *hdev); +int hl_cb_va_pool_init(struct hl_ctx *ctx); +void hl_cb_va_pool_fini(struct hl_ctx *ctx); void hl_cs_rollback_all(struct hl_device *hdev); struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index b51cc6c1d541..6f7f6ad7a358 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -4115,7 +4115,7 @@ static int gaudi_parse_cb_mmu(struct hl_device *hdev, sizeof(struct packet_msg_prot) * 2; rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, - parser->patched_cb_size, false, + parser->patched_cb_size, false, false, &patched_cb_handle); if (rc) { @@ -4189,7 +4189,7 @@ static int gaudi_parse_cb_no_mmu(struct hl_device *hdev, goto free_userptr; rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, - parser->patched_cb_size, false, + parser->patched_cb_size, false, false, &patched_cb_handle); if (rc) { dev_err(hdev->dev, diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 6c81a4b148de..5cddd46a8fb8 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -3811,7 +3811,7 @@ static int goya_parse_cb_mmu(struct hl_device *hdev, sizeof(struct packet_msg_prot) * 2; rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, - parser->patched_cb_size, false, + parser->patched_cb_size, false, false, &patched_cb_handle); if (rc) { @@ -3885,7 +3885,7 @@ static int goya_parse_cb_no_mmu(struct hl_device *hdev, goto free_userptr; rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx, - parser->patched_cb_size, false, + parser->patched_cb_size, false, false, &patched_cb_handle); if (rc) { dev_err(hdev->dev, diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index d449f8a31ce6..9705b8adb60c 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -462,6 +462,9 @@ struct hl_info_args { /* 2MB minus 32 bytes for 2xMSG_PROT */ #define HL_MAX_CB_SIZE (0x200000 - 32) +/* Indicates whether the command buffer should be mapped to the device's MMU */ +#define HL_CB_FLAGS_MAP 0x1 + struct hl_cb_in { /* Handle of CB or 0 if we want to create one */ __u64 cb_handle; @@ -473,7 +476,8 @@ struct hl_cb_in { __u32 cb_size; /* Context ID - Currently not in use */ __u32 ctx_id; - __u32 pad; + /* HL_CB_FLAGS_* */ + __u32 flags; }; struct hl_cb_out { @@ -856,6 +860,12 @@ struct hl_debug_args { * When creating a new CB, the IOCTL returns a handle of it, and the user-space * process needs to use that handle to mmap the buffer so it can access them. * + * In some instances, the device must access the command buffer through the + * device's MMU, and thus its memory should be mapped. In these cases, user can + * indicate the driver that such a mapping is required. + * The resulting device virtual address will be used internally by the driver, + * and won't be returned to user. + * */ #define HL_IOCTL_CB \ _IOWR('H', 0x02, union hl_cb_args) From 219b8f2ff024a7f8f2cd1a9a0a1d7651c1a02737 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Thu, 10 Sep 2020 16:37:59 +0300 Subject: [PATCH 42/46] habanalabs: update firmware interface file Add new packet to fetch PLL information from firmware. This will be needed in the future when the driver won't be able to access the PLL registers directly Signed-off-by: Oded Gabbay --- .../misc/habanalabs/include/common/cpucp_if.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/misc/habanalabs/include/common/cpucp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h index dcde440427b4..2a5c9cb3d505 100644 --- a/drivers/misc/habanalabs/include/common/cpucp_if.h +++ b/drivers/misc/habanalabs/include/common/cpucp_if.h @@ -213,6 +213,12 @@ enum pq_init_status { * Trigger the reset_history property of a specified current sensor. * The packet's arguments specify the desired sensor and the field to * set. + * + * CPUCP_PACKET_PLL_REG_GET + * Fetch register of PLL from the required PLL IP. + * The packet's arguments specify the PLL IP and the register to get. + * Each register is 32-bit value which is returned in result field. + * */ enum cpucp_packet_id { @@ -245,6 +251,7 @@ enum cpucp_packet_id { CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ + CPUCP_PACKET_PLL_REG_GET, /* internal */ }; #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 @@ -279,6 +286,11 @@ struct cpucp_packet { __u8 pad; /* unused */ }; + struct {/* For PLL register fetch */ + __le16 pll_type; + __le16 pll_reg; + }; + /* For any general request */ __le32 index; @@ -354,6 +366,19 @@ enum cpucp_pcie_throughput_attributes { cpucp_pcie_throughput_rx }; +enum cpucp_pll_reg_attributes { + cpucp_pll_nr_reg, + cpucp_pll_nf_reg, + cpucp_pll_od_reg, + cpucp_pll_div_factor_reg, + cpucp_pll_div_sel_reg +}; + +enum cpucp_pll_type_attributes { + cpucp_pll_cpu, + cpucp_pll_pci, +}; + /* Event Queue Packets */ struct eq_generic_event { From dbf053c42994460d5228e6cef3f69d3c91e52a92 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sun, 13 Sep 2020 15:35:33 +0300 Subject: [PATCH 43/46] habanalabs/gaudi: remove axi drain support AXI drain is broken in GAUDI so remove support for enabling it. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudi.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 6f7f6ad7a358..2c10e3f92c86 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -2885,22 +2885,6 @@ static void gaudi_pre_hw_init(struct hl_device *hdev) */ RREG32(mmPCIE_WRAP_LBW_PROT_OVR); - if (hdev->axi_drain) { - WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, - 1 << PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT); - WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, - 1 << PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT); - - /* Perform read to flush the DRAIN cfg */ - RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); - } else { - WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, 0); - WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, 0); - - /* Perform read to flush the DRAIN cfg */ - RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); - } - /* Configure the reset registers. Must be done as early as possible * in case we fail during H/W initialization */ From d1f3633599a9178572f3b25f9f23cd9dc423a9fa Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Mon, 14 Sep 2020 09:26:54 +0300 Subject: [PATCH 44/46] habanalabs/gaudi: fix DMA completions max outstanding to 15 This is a workaround for H/W bug H3-2116, where if there are more than 16 outstanding completions in the DMA transpose engine, there can be a deadlock in the engine. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 2c10e3f92c86..86650be5898f 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -1918,6 +1918,9 @@ static void gaudi_init_dma_core(struct hl_device *hdev, int dma_id) WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0); WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0); + /* WA for H/W bug H3-2116 */ + WREG32(mmDMA0_CORE_LBW_MAX_OUTSTAND + dma_offset, 15); + /* STOP_ON bit implies no completion to operation in case of RAZWI */ if (hdev->stop_on_err) dma_err_cfg |= 1 << DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT; From 57799ce9f85c23ecbbc9d356969ea54bd6b8a647 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sun, 13 Sep 2020 15:51:28 +0300 Subject: [PATCH 45/46] habanalabs: add indication of security-enabled F/W Future F/W versions will have enhanced security measures and the driver won't be able to do certain configurations that it always did and those configurations will be done by the firmware. We use the firmware's preboot version to determine whether security measures are enabled or not. Because we need this very early in our code, the read of the preboot version is moved to the earliest possible place, right after the device's PCI initialization. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/common/firmware_if.c | 55 +++++++++++++++++--- drivers/misc/habanalabs/common/habanalabs.h | 8 ++- drivers/misc/habanalabs/common/pci.c | 16 +++++- drivers/misc/habanalabs/gaudi/gaudi.c | 28 ++++++---- drivers/misc/habanalabs/goya/goya.c | 7 ++- 5 files changed, 94 insertions(+), 20 deletions(-) diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c index 4409962d30ae..cd41c7ceb0e7 100644 --- a/drivers/misc/habanalabs/common/firmware_if.c +++ b/drivers/misc/habanalabs/common/firmware_if.c @@ -474,8 +474,11 @@ static void fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg) "Device boot error - NIC F/W initialization failed\n"); } -static void hl_detect_cpu_boot_status(struct hl_device *hdev, u32 status) +static void detect_cpu_boot_status(struct hl_device *hdev, u32 status) { + /* Some of the status codes below are deprecated in newer f/w + * versions but we keep them here for backward compatibility + */ switch (status) { case CPU_BOOT_STATUS_NA: dev_err(hdev->dev, @@ -521,6 +524,48 @@ static void hl_detect_cpu_boot_status(struct hl_device *hdev, u32 status) } } +int hl_fw_read_preboot_ver(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 boot_err0_reg, u32 timeout) +{ + u32 status; + int rc; + + if (!hdev->cpu_enable) + return 0; + + /* Need to check two possible scenarios: + * + * CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT - for newer firmwares where + * the preboot is waiting for the boot fit + * + * All other status values - for older firmwares where the uboot was + * loaded from the FLASH + */ + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + (status == CPU_BOOT_STATUS_IN_UBOOT) || + (status == CPU_BOOT_STATUS_DRAM_RDY) || + (status == CPU_BOOT_STATUS_NIC_FW_RDY) || + (status == CPU_BOOT_STATUS_READY_TO_BOOT) || + (status == CPU_BOOT_STATUS_SRAM_AVAIL) || + (status == CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT), + 10000, + timeout); + + if (rc) { + dev_err(hdev->dev, "Failed to read preboot version\n"); + detect_cpu_boot_status(hdev, status); + fw_read_errors(hdev, boot_err0_reg); + return -EIO; + } + + hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_PREBOOT); + + return 0; +} + int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, u32 boot_err0_reg, bool skip_bmc, @@ -586,15 +631,11 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, 10000, cpu_timeout); - /* Read U-Boot, preboot versions now in case we will later fail */ + /* Read U-Boot version now in case we will later fail */ hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_UBOOT); - hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_PREBOOT); - /* Some of the status codes below are deprecated in newer f/w - * versions but we keep them here for backward compatibility - */ if (rc) { - hl_detect_cpu_boot_status(hdev, status); + detect_cpu_boot_status(hdev, status); rc = -EIO; goto out; } diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index eaa9bf3f82a3..80d4d7385ffe 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -320,6 +320,8 @@ struct hl_mmu_properties { * @first_available_user_mon: first monitor available for the user * @tpc_enabled_mask: which TPCs are enabled. * @completion_queues_count: number of completion queues. + * @fw_security_disabled: true if security measures are disabled in firmware, + * false otherwise */ struct asic_fixed_properties { struct hw_queue_properties *hw_queues_props; @@ -370,6 +372,7 @@ struct asic_fixed_properties { u16 first_available_user_mon[HL_MAX_DCORES]; u8 tpc_enabled_mask; u8 completion_queues_count; + u8 fw_security_disabled; }; /** @@ -1933,6 +1936,8 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, u32 boot_err0_reg, bool skip_bmc, u32 cpu_timeout, u32 boot_fit_timeout); +int hl_fw_read_preboot_ver(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 boot_err0_reg, u32 timeout); int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3], bool is_wc[3]); @@ -1941,7 +1946,8 @@ int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region, struct hl_inbound_pci_region *pci_region); int hl_pci_set_outbound_region(struct hl_device *hdev, struct hl_outbound_pci_region *pci_region); -int hl_pci_init(struct hl_device *hdev); +int hl_pci_init(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 boot_err0_reg, u32 preboot_ver_timeout); void hl_pci_fini(struct hl_device *hdev); long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr); diff --git a/drivers/misc/habanalabs/common/pci.c b/drivers/misc/habanalabs/common/pci.c index 923b2606e29f..4327e5704ebb 100644 --- a/drivers/misc/habanalabs/common/pci.c +++ b/drivers/misc/habanalabs/common/pci.c @@ -338,12 +338,17 @@ static int hl_pci_set_dma_mask(struct hl_device *hdev) /** * hl_pci_init() - PCI initialization code. * @hdev: Pointer to hl_device structure. + * @cpu_boot_status_reg: status register of the device's CPU + * @boot_err0_reg: boot error register of the device's CPU + * @preboot_ver_timeout: how much to wait before bailing out on reading + * the preboot version * * Set DMA masks, initialize the PCI controller and map the PCI BARs. * * Return: 0 on success, non-zero for failure. */ -int hl_pci_init(struct hl_device *hdev) +int hl_pci_init(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 boot_err0_reg, u32 preboot_ver_timeout) { struct pci_dev *pdev = hdev->pdev; int rc; @@ -375,6 +380,15 @@ int hl_pci_init(struct hl_device *hdev) if (rc) goto unmap_pci_bars; + /* Before continuing in the initialization, we need to read the preboot + * version to determine whether we run with a security-enabled firmware + * The check will be done in each ASIC's specific code + */ + rc = hl_fw_read_preboot_ver(hdev, cpu_boot_status_reg, boot_err0_reg, + preboot_ver_timeout); + if (rc) + goto unmap_pci_bars; + return 0; unmap_pci_bars: diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 86650be5898f..1b51e670bd4e 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -599,10 +599,15 @@ static int gaudi_early_init(struct hl_device *hdev) prop->dram_pci_bar_size = pci_resource_len(pdev, HBM_BAR_ID); - rc = hl_pci_init(hdev); + rc = hl_pci_init(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, + mmCPU_BOOT_ERR0, GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC); if (rc) goto free_queue_props; + /* GAUDI Firmware does not yet support security */ + prop->fw_security_disabled = true; + dev_info(hdev->dev, "firmware-level security is disabled\n"); + return 0; free_queue_props: @@ -2871,6 +2876,18 @@ static void gaudi_pre_hw_init(struct hl_device *hdev) /* Perform read from the device to make sure device is up */ RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + /* Set the access through PCI bars (Linux driver only) as + * secured + */ + WREG32(mmPCIE_WRAP_LBW_PROT_OVR, + (PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK | + PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK)); + + /* Perform read to flush the waiting writes to ensure + * configuration was set in the device + */ + RREG32(mmPCIE_WRAP_LBW_PROT_OVR); + /* * Let's mark in the H/W that we have reached this point. We check * this value in the reset_before_init function to understand whether @@ -2879,15 +2896,6 @@ static void gaudi_pre_hw_init(struct hl_device *hdev) */ WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); - /* Set the access through PCI bars (Linux driver only) as secured */ - WREG32(mmPCIE_WRAP_LBW_PROT_OVR, (PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK | - PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK)); - - /* Perform read to flush the waiting writes to ensure configuration - * was set in the device - */ - RREG32(mmPCIE_WRAP_LBW_PROT_OVR); - /* Configure the reset registers. Must be done as early as possible * in case we fail during H/W initialization */ diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 5cddd46a8fb8..5db52064ed9e 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -600,10 +600,15 @@ static int goya_early_init(struct hl_device *hdev) prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID); - rc = hl_pci_init(hdev); + rc = hl_pci_init(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, + mmCPU_BOOT_ERR0, GOYA_BOOT_FIT_REQ_TIMEOUT_USEC); if (rc) goto free_queue_props; + /* Goya Firmware does not support security */ + prop->fw_security_disabled = true; + dev_info(hdev->dev, "firmware-level security is disabled\n"); + if (!hdev->pldm) { val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK) From f279e5cd95058ddbb8f86e1c32f25d36502a115c Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Thu, 17 Sep 2020 17:57:03 +0300 Subject: [PATCH 46/46] habanalabs: update scratchpad register map Our firmware use some scratchpad registers in the device for different roles. Update the file to the latest version of the firmware code. Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h | 1 + drivers/misc/habanalabs/include/goya/goya_reg_map.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h index f25c60a2c243..977fb341a6e7 100644 --- a/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h @@ -12,6 +12,7 @@ * PSOC scratch-pad registers */ #define mmHW_STATE mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 +#define mmFUSE_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 #define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 #define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 #define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 diff --git a/drivers/misc/habanalabs/include/goya/goya_reg_map.h b/drivers/misc/habanalabs/include/goya/goya_reg_map.h index 0195f62d7254..e56124265a05 100644 --- a/drivers/misc/habanalabs/include/goya/goya_reg_map.h +++ b/drivers/misc/habanalabs/include/goya/goya_reg_map.h @@ -22,6 +22,7 @@ #define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 #define mmCPU_CQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 #define mmCPU_CQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 +#define mmFUSE_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 #define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 #define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 #define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25