forked from Minki/linux
Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner', 'clk-samsung', 'clk-doc' and 'clk-unused' into clk-next
- Remove various unused variables in clk drivers * clk-renesas: clk: renesas: rcar-gen3: Update description for RZ/G2 clk: renesas: cpg-mssr: Add support for R-Car V3U clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0 dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions dt-bindings: power: Add r8a779a0 SYSC power domain definitions clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) clk: renesas: r8a7742: Add clk entry for VSPR * clk-amlogic: clk: meson: make shipped controller configurable clk: meson: g12a: mark fclk_div2 as critical clk: meson: axg-audio: fix g12a tdmout sclk inverter clk: meson: axg-audio: separate axg and g12a regmap tables clk: meson: add sclk-ws driver * clk-allwinner: clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL clk: sunxi-ng: add support for the Allwinner A100 CCU dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU * clk-samsung: clk: s2mps11: initialize driver via module_platform_driver clk: samsung: Use cached clk_hws instead of __clk_lookup() calls clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions clk: samsung: Add clk ID definitions for the CPU parent clocks clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d clk: samsung: Keep top BPLL mux on Exynos542x enabled * clk-doc: clk: davinci: add missing kerneldoc clk: fixed: add missing kerneldoc * clk-unused: clk: socfpga: agilex: Remove unused variable 'cntr_mux' clk: si5341: drop unused 'err' variable clk: mmp: pxa1928: drop unused 'clk' variable clk: at91: drop unused at91sam9g45_pcr_layout
This commit is contained in:
commit
9d3261628a
@ -36,6 +36,8 @@ properties:
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- allwinner,sun9i-a80-ccu
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- allwinner,sun50i-a64-ccu
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- allwinner,sun50i-a64-r-ccu
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- allwinner,sun50i-a100-ccu
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- allwinner,sun50i-a100-r-ccu
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- allwinner,sun50i-h5-ccu
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- allwinner,sun50i-h6-ccu
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- allwinner,sun50i-h6-r-ccu
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@ -78,6 +80,7 @@ if:
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- allwinner,sun8i-a83t-r-ccu
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- allwinner,sun8i-h3-r-ccu
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- allwinner,sun50i-a64-r-ccu
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- allwinner,sun50i-a100-r-ccu
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- allwinner,sun50i-h6-r-ccu
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then:
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@ -94,7 +97,9 @@ else:
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if:
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properties:
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compatible:
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const: allwinner,sun50i-h6-ccu
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enum:
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- allwinner,sun50i-a100-ccu
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- allwinner,sun50i-h6-ccu
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then:
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properties:
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@ -46,13 +46,6 @@ static const struct {
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{ .n = "pck1", .p = "prog1", .id = 9 },
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};
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static const struct clk_pcr_layout at91sam9g45_pcr_layout = {
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.offset = 0x10c,
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.cmd = BIT(12),
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.pid_mask = GENMASK(5, 0),
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.div_mask = GENMASK(17, 16),
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};
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struct pck {
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char *n;
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u8 id;
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@ -206,6 +206,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
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/**
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* of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
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* @node: device node for the clock
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*/
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void __init of_fixed_factor_clk_setup(struct device_node *node)
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{
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@ -168,6 +168,7 @@ static struct clk_hw *_of_fixed_clk_setup(struct device_node *node)
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/**
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* of_fixed_clk_setup() - Setup function for simple fixed rate clock
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* @node: device node for the clock
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*/
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void __init of_fixed_clk_setup(struct device_node *node)
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{
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@ -267,18 +267,7 @@ static struct platform_driver s2mps11_clk_driver = {
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.remove = s2mps11_clk_remove,
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.id_table = s2mps11_clk_id,
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};
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static int __init s2mps11_clk_init(void)
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{
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return platform_driver_register(&s2mps11_clk_driver);
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}
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subsys_initcall(s2mps11_clk_init);
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static void __exit s2mps11_clk_cleanup(void)
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{
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platform_driver_unregister(&s2mps11_clk_driver);
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}
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module_exit(s2mps11_clk_cleanup);
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module_platform_driver(s2mps11_clk_driver);
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MODULE_DESCRIPTION("S2MPS11 Clock Driver");
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MODULE_AUTHOR("Yadwinder Singh Brar <yadi.brar@samsung.com>");
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@ -883,11 +883,9 @@ static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
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static u8 si5341_output_get_parent(struct clk_hw *hw)
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{
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struct clk_si5341_output *output = to_clk_si5341_output(hw);
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int err;
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u32 val;
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err = regmap_read(output->data->regmap,
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SI5341_OUT_MUX_SEL(output), &val);
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regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
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return val & 0x7;
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}
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@ -571,6 +571,7 @@ static const struct clk_ops da8xx_usb1_clk48_ops = {
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/**
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* da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock
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* @dev: The device
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* @regmap: The CFGCHIP regmap
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*/
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static struct da8xx_usb1_clk48 *
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@ -1,4 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menu "Clock support for Amlogic platforms"
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depends on ARCH_MESON || COMPILE_TEST
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config COMMON_CLK_MESON_REGMAP
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tristate
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select REGMAP
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@ -41,8 +44,9 @@ config COMMON_CLK_MESON_CPU_DYNDIV
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON8B
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bool
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depends on ARCH_MESON
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bool "Meson8 SoC Clock controller support"
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depends on ARM
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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@ -54,8 +58,9 @@ config COMMON_CLK_MESON8B
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want peripherals and CPU frequency scaling to work.
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config COMMON_CLK_GXBB
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bool
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depends on ARCH_MESON
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bool "GXBB and GXL SoC clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_VID_PLL_DIV
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@ -69,8 +74,9 @@ config COMMON_CLK_GXBB
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Say Y if you want peripherals and CPU frequency scaling to work.
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config COMMON_CLK_AXG
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bool
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depends on ARCH_MESON
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bool "AXG SoC clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_MPLL
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@ -84,7 +90,7 @@ config COMMON_CLK_AXG
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config COMMON_CLK_AXG_AUDIO
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tristate "Meson AXG Audio Clock Controller Driver"
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depends on ARCH_MESON
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depends on ARM64
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_PHASE
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select COMMON_CLK_MESON_SCLK_DIV
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@ -94,8 +100,9 @@ config COMMON_CLK_AXG_AUDIO
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aka axg, Say Y if you want audio subsystem to work.
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config COMMON_CLK_G12A
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bool
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depends on ARCH_MESON
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bool "G12 and SM1 SoC clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_MPLL
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@ -107,3 +114,4 @@ config COMMON_CLK_G12A
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help
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Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
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devices, aka g12a. Say Y if you want peripherals to work.
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endmenu
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@ -147,6 +147,29 @@
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}, \
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}
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#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \
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_iflags) { \
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.data = &(struct meson_sclk_ws_inv_data) { \
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.ph = { \
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.reg_off = (_reg), \
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.shift = (_shift_ph), \
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.width = (_width), \
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}, \
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.ws = { \
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.reg_off = (_reg), \
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.shift = (_shift_ws), \
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.width = (_width), \
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}, \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = "aud_"#_name, \
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.ops = &meson_clk_phase_ops, \
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.parent_names = (const char *[]){ #_pname }, \
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.num_parents = 1, \
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.flags = (_iflags), \
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}, \
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}
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/* Audio Master Clocks */
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static const struct clk_parent_data mst_mux_parent_data[] = {
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{ .fw_name = "mst_in0", },
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@ -254,6 +277,10 @@ static const struct clk_parent_data tdm_lrclk_parent_data[] = {
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AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29, \
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aud_tdm##_name##_sclk_post_en, \
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CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
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#define AUD_TDM_SCLK_WS(_name, _reg) \
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AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28, \
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aud_tdm##_name##_sclk_post_en, \
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CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
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#define AUD_TDM_LRLCK(_name, _reg) \
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AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
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@ -499,12 +526,6 @@ static struct clk_regmap tdmin_c_sclk =
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AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
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static struct clk_regmap tdmin_lb_sclk =
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AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
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static struct clk_regmap tdmout_a_sclk =
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AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
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static struct clk_regmap tdmout_b_sclk =
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AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
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static struct clk_regmap tdmout_c_sclk =
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AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
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static struct clk_regmap tdmin_a_lrclk =
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AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
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@ -521,6 +542,14 @@ static struct clk_regmap tdmout_b_lrclk =
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static struct clk_regmap tdmout_c_lrclk =
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AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
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/* AXG Clocks */
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static struct clk_regmap axg_tdmout_a_sclk =
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AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
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static struct clk_regmap axg_tdmout_b_sclk =
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AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
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static struct clk_regmap axg_tdmout_c_sclk =
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AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
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/* AXG/G12A Clocks */
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static struct clk_hw axg_aud_top = {
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.init = &(struct clk_init_data) {
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@ -591,7 +620,13 @@ static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
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static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
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sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
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/* G12a/SM1 clocks */
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static struct clk_regmap g12a_tdmout_a_sclk =
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AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
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static struct clk_regmap g12a_tdmout_b_sclk =
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AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
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static struct clk_regmap g12a_tdmout_c_sclk =
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AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
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static struct clk_regmap toram =
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AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
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static struct clk_regmap spdifout_b =
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@ -889,9 +924,9 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
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[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
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[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
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[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
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[AUD_CLKID_TDMOUT_A_SCLK] = &tdmout_a_sclk.hw,
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[AUD_CLKID_TDMOUT_B_SCLK] = &tdmout_b_sclk.hw,
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[AUD_CLKID_TDMOUT_C_SCLK] = &tdmout_c_sclk.hw,
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[AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
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[AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
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[AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
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[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
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[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
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[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
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@ -1026,9 +1061,9 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
@ -1170,9 +1205,9 @@ static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
@ -1209,13 +1244,132 @@ static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
|
||||
};
|
||||
|
||||
|
||||
/* Convenience table to populate regmap in .probe()
|
||||
* Note that this table is shared between both AXG and G12A,
|
||||
* with spdifout_b clocks being exclusive to G12A. Since those
|
||||
* clocks are not declared within the AXG onecell table, we do not
|
||||
* feel the need to have separate AXG/G12A regmap tables.
|
||||
*/
|
||||
/* Convenience table to populate regmap in .probe(). */
|
||||
static struct clk_regmap *const axg_clk_regmaps[] = {
|
||||
&ddr_arb,
|
||||
&pdm,
|
||||
&tdmin_a,
|
||||
&tdmin_b,
|
||||
&tdmin_c,
|
||||
&tdmin_lb,
|
||||
&tdmout_a,
|
||||
&tdmout_b,
|
||||
&tdmout_c,
|
||||
&frddr_a,
|
||||
&frddr_b,
|
||||
&frddr_c,
|
||||
&toddr_a,
|
||||
&toddr_b,
|
||||
&toddr_c,
|
||||
&loopback,
|
||||
&spdifin,
|
||||
&spdifout,
|
||||
&resample,
|
||||
&power_detect,
|
||||
&mst_a_mclk_sel,
|
||||
&mst_b_mclk_sel,
|
||||
&mst_c_mclk_sel,
|
||||
&mst_d_mclk_sel,
|
||||
&mst_e_mclk_sel,
|
||||
&mst_f_mclk_sel,
|
||||
&mst_a_mclk_div,
|
||||
&mst_b_mclk_div,
|
||||
&mst_c_mclk_div,
|
||||
&mst_d_mclk_div,
|
||||
&mst_e_mclk_div,
|
||||
&mst_f_mclk_div,
|
||||
&mst_a_mclk,
|
||||
&mst_b_mclk,
|
||||
&mst_c_mclk,
|
||||
&mst_d_mclk,
|
||||
&mst_e_mclk,
|
||||
&mst_f_mclk,
|
||||
&spdifout_clk_sel,
|
||||
&spdifout_clk_div,
|
||||
&spdifout_clk,
|
||||
&spdifin_clk_sel,
|
||||
&spdifin_clk_div,
|
||||
&spdifin_clk,
|
||||
&pdm_dclk_sel,
|
||||
&pdm_dclk_div,
|
||||
&pdm_dclk,
|
||||
&pdm_sysclk_sel,
|
||||
&pdm_sysclk_div,
|
||||
&pdm_sysclk,
|
||||
&mst_a_sclk_pre_en,
|
||||
&mst_b_sclk_pre_en,
|
||||
&mst_c_sclk_pre_en,
|
||||
&mst_d_sclk_pre_en,
|
||||
&mst_e_sclk_pre_en,
|
||||
&mst_f_sclk_pre_en,
|
||||
&mst_a_sclk_div,
|
||||
&mst_b_sclk_div,
|
||||
&mst_c_sclk_div,
|
||||
&mst_d_sclk_div,
|
||||
&mst_e_sclk_div,
|
||||
&mst_f_sclk_div,
|
||||
&mst_a_sclk_post_en,
|
||||
&mst_b_sclk_post_en,
|
||||
&mst_c_sclk_post_en,
|
||||
&mst_d_sclk_post_en,
|
||||
&mst_e_sclk_post_en,
|
||||
&mst_f_sclk_post_en,
|
||||
&mst_a_sclk,
|
||||
&mst_b_sclk,
|
||||
&mst_c_sclk,
|
||||
&mst_d_sclk,
|
||||
&mst_e_sclk,
|
||||
&mst_f_sclk,
|
||||
&mst_a_lrclk_div,
|
||||
&mst_b_lrclk_div,
|
||||
&mst_c_lrclk_div,
|
||||
&mst_d_lrclk_div,
|
||||
&mst_e_lrclk_div,
|
||||
&mst_f_lrclk_div,
|
||||
&mst_a_lrclk,
|
||||
&mst_b_lrclk,
|
||||
&mst_c_lrclk,
|
||||
&mst_d_lrclk,
|
||||
&mst_e_lrclk,
|
||||
&mst_f_lrclk,
|
||||
&tdmin_a_sclk_sel,
|
||||
&tdmin_b_sclk_sel,
|
||||
&tdmin_c_sclk_sel,
|
||||
&tdmin_lb_sclk_sel,
|
||||
&tdmout_a_sclk_sel,
|
||||
&tdmout_b_sclk_sel,
|
||||
&tdmout_c_sclk_sel,
|
||||
&tdmin_a_sclk_pre_en,
|
||||
&tdmin_b_sclk_pre_en,
|
||||
&tdmin_c_sclk_pre_en,
|
||||
&tdmin_lb_sclk_pre_en,
|
||||
&tdmout_a_sclk_pre_en,
|
||||
&tdmout_b_sclk_pre_en,
|
||||
&tdmout_c_sclk_pre_en,
|
||||
&tdmin_a_sclk_post_en,
|
||||
&tdmin_b_sclk_post_en,
|
||||
&tdmin_c_sclk_post_en,
|
||||
&tdmin_lb_sclk_post_en,
|
||||
&tdmout_a_sclk_post_en,
|
||||
&tdmout_b_sclk_post_en,
|
||||
&tdmout_c_sclk_post_en,
|
||||
&tdmin_a_sclk,
|
||||
&tdmin_b_sclk,
|
||||
&tdmin_c_sclk,
|
||||
&tdmin_lb_sclk,
|
||||
&axg_tdmout_a_sclk,
|
||||
&axg_tdmout_b_sclk,
|
||||
&axg_tdmout_c_sclk,
|
||||
&tdmin_a_lrclk,
|
||||
&tdmin_b_lrclk,
|
||||
&tdmin_c_lrclk,
|
||||
&tdmin_lb_lrclk,
|
||||
&tdmout_a_lrclk,
|
||||
&tdmout_b_lrclk,
|
||||
&tdmout_c_lrclk,
|
||||
};
|
||||
|
||||
static struct clk_regmap *const g12a_clk_regmaps[] = {
|
||||
&ddr_arb,
|
||||
&pdm,
|
||||
&tdmin_a,
|
||||
@ -1328,9 +1482,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
|
||||
&tdmin_b_sclk,
|
||||
&tdmin_c_sclk,
|
||||
&tdmin_lb_sclk,
|
||||
&tdmout_a_sclk,
|
||||
&tdmout_b_sclk,
|
||||
&tdmout_c_sclk,
|
||||
&g12a_tdmout_a_sclk,
|
||||
&g12a_tdmout_b_sclk,
|
||||
&g12a_tdmout_c_sclk,
|
||||
&tdmin_a_lrclk,
|
||||
&tdmin_b_lrclk,
|
||||
&tdmin_c_lrclk,
|
||||
@ -1465,9 +1619,9 @@ static struct clk_regmap *const sm1_clk_regmaps[] = {
|
||||
&tdmin_b_sclk,
|
||||
&tdmin_c_sclk,
|
||||
&tdmin_lb_sclk,
|
||||
&tdmout_a_sclk,
|
||||
&tdmout_b_sclk,
|
||||
&tdmout_c_sclk,
|
||||
&g12a_tdmout_a_sclk,
|
||||
&g12a_tdmout_b_sclk,
|
||||
&g12a_tdmout_c_sclk,
|
||||
&tdmin_a_lrclk,
|
||||
&tdmin_b_lrclk,
|
||||
&tdmin_c_lrclk,
|
||||
@ -1713,8 +1867,8 @@ static const struct audioclk_data axg_audioclk_data = {
|
||||
};
|
||||
|
||||
static const struct audioclk_data g12a_audioclk_data = {
|
||||
.regmap_clks = axg_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
|
||||
.regmap_clks = g12a_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
|
||||
.hw_onecell_data = &g12a_audio_hw_onecell_data,
|
||||
.reset_offset = AUDIO_SW_RESET,
|
||||
.reset_num = 26,
|
||||
|
@ -125,6 +125,62 @@ const struct clk_ops meson_clk_triphase_ops = {
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(meson_clk_triphase_ops);
|
||||
|
||||
/*
|
||||
* This is a special clock for the audio controller.
|
||||
* This drive a bit clock inverter for which the
|
||||
* opposite value of the inverter bit needs to be manually
|
||||
* set into another bit
|
||||
*/
|
||||
static inline struct meson_sclk_ws_inv_data *
|
||||
meson_sclk_ws_inv_data(struct clk_regmap *clk)
|
||||
{
|
||||
return (struct meson_sclk_ws_inv_data *)clk->data;
|
||||
}
|
||||
|
||||
static int meson_sclk_ws_inv_sync(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
|
||||
unsigned int val;
|
||||
|
||||
/* Get phase and sync the inverted value to ws */
|
||||
val = meson_parm_read(clk->map, &tph->ph);
|
||||
meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_sclk_ws_inv_get_phase(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
|
||||
unsigned int val;
|
||||
|
||||
val = meson_parm_read(clk->map, &tph->ph);
|
||||
|
||||
return meson_clk_degrees_from_val(val, tph->ph.width);
|
||||
}
|
||||
|
||||
static int meson_sclk_ws_inv_set_phase(struct clk_hw *hw, int degrees)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
|
||||
unsigned int val;
|
||||
|
||||
val = meson_clk_degrees_to_val(degrees, tph->ph.width);
|
||||
meson_parm_write(clk->map, &tph->ph, val);
|
||||
meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops meson_sclk_ws_inv_ops = {
|
||||
.init = meson_sclk_ws_inv_sync,
|
||||
.get_phase = meson_sclk_ws_inv_get_phase,
|
||||
.set_phase = meson_sclk_ws_inv_set_phase,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(meson_sclk_ws_inv_ops);
|
||||
|
||||
|
||||
MODULE_DESCRIPTION("Amlogic phase driver");
|
||||
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
@ -20,7 +20,13 @@ struct meson_clk_triphase_data {
|
||||
struct parm ph2;
|
||||
};
|
||||
|
||||
struct meson_sclk_ws_inv_data {
|
||||
struct parm ph;
|
||||
struct parm ws;
|
||||
};
|
||||
|
||||
extern const struct clk_ops meson_clk_phase_ops;
|
||||
extern const struct clk_ops meson_clk_triphase_ops;
|
||||
extern const struct clk_ops meson_sclk_ws_inv_ops;
|
||||
|
||||
#endif /* __MESON_CLK_PHASE_H */
|
||||
|
@ -298,6 +298,17 @@ static struct clk_regmap g12a_fclk_div2 = {
|
||||
&g12a_fclk_div2_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* Similar to fclk_div3, it seems that this clock is used by
|
||||
* the resident firmware and is required by the platform to
|
||||
* operate correctly.
|
||||
* Until the following condition are met, we need this clock to
|
||||
* be marked as critical:
|
||||
* a) Mark the clock used by a firmware resource, if possible
|
||||
* b) CCF has a clock hand-off mechanism to make the sure the
|
||||
* clock stays on until the proper driver comes along
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -68,7 +68,6 @@ static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||
|
||||
static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct mmp_clk_unit *unit = &pxa_unit->unit;
|
||||
|
||||
mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
|
||||
@ -77,7 +76,7 @@ static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
|
||||
mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
|
||||
ARRAY_SIZE(fixed_factor_clks));
|
||||
|
||||
clk = mmp_clk_register_factor("uart_pll", "pll1_416",
|
||||
mmp_clk_register_factor("uart_pll", "pll1_416",
|
||||
CLK_SET_RATE_PARENT,
|
||||
pxa_unit->mpmu_base + MPMU_UART_PLL,
|
||||
&uart_factor_masks, uart_factor_tbl,
|
||||
|
@ -401,26 +401,34 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
|
||||
|
||||
/* helper function to register a CPU clock */
|
||||
int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
||||
unsigned int lookup_id, const char *name, const char *parent,
|
||||
const char *alt_parent, unsigned long offset,
|
||||
const struct exynos_cpuclk_cfg_data *cfg,
|
||||
unsigned int lookup_id, const char *name,
|
||||
const struct clk_hw *parent, const struct clk_hw *alt_parent,
|
||||
unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
|
||||
unsigned long num_cfgs, unsigned long flags)
|
||||
{
|
||||
struct exynos_cpuclk *cpuclk;
|
||||
struct clk_init_data init;
|
||||
struct clk *parent_clk;
|
||||
const char *parent_name;
|
||||
int ret = 0;
|
||||
|
||||
if (IS_ERR(parent) || IS_ERR(alt_parent)) {
|
||||
pr_err("%s: invalid parent clock(s)\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
|
||||
if (!cpuclk)
|
||||
return -ENOMEM;
|
||||
|
||||
parent_name = clk_hw_get_name(parent);
|
||||
|
||||
init.name = name;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = &parent;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.ops = &exynos_cpuclk_clk_ops;
|
||||
|
||||
cpuclk->alt_parent = alt_parent;
|
||||
cpuclk->hw.init = &init;
|
||||
cpuclk->ctrl_base = ctx->reg_base + offset;
|
||||
cpuclk->lock = &ctx->lock;
|
||||
@ -430,23 +438,8 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
||||
else
|
||||
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
|
||||
|
||||
cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent));
|
||||
if (!cpuclk->alt_parent) {
|
||||
pr_err("%s: could not lookup alternate parent %s\n",
|
||||
__func__, alt_parent);
|
||||
ret = -EINVAL;
|
||||
goto free_cpuclk;
|
||||
}
|
||||
|
||||
parent_clk = __clk_lookup(parent);
|
||||
if (!parent_clk) {
|
||||
pr_err("%s: could not lookup parent clock %s\n",
|
||||
__func__, parent);
|
||||
ret = -EINVAL;
|
||||
goto free_cpuclk;
|
||||
}
|
||||
|
||||
ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);
|
||||
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to register clock notifier for %s\n",
|
||||
__func__, name);
|
||||
@ -471,7 +464,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
||||
free_cpuclk_data:
|
||||
kfree(cpuclk->cfg);
|
||||
unregister_clk_nb:
|
||||
clk_notifier_unregister(parent_clk, &cpuclk->clk_nb);
|
||||
clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);
|
||||
free_cpuclk:
|
||||
kfree(cpuclk);
|
||||
return ret;
|
||||
|
@ -46,7 +46,7 @@ struct exynos_cpuclk_cfg_data {
|
||||
*/
|
||||
struct exynos_cpuclk {
|
||||
struct clk_hw hw;
|
||||
struct clk_hw *alt_parent;
|
||||
const struct clk_hw *alt_parent;
|
||||
void __iomem *ctrl_base;
|
||||
spinlock_t *lock;
|
||||
const struct exynos_cpuclk_cfg_data *cfg;
|
||||
@ -62,9 +62,9 @@ struct exynos_cpuclk {
|
||||
#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
|
||||
};
|
||||
|
||||
extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
||||
int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
||||
unsigned int lookup_id, const char *name,
|
||||
const char *parent, const char *alt_parent,
|
||||
const struct clk_hw *parent, const struct clk_hw *alt_parent,
|
||||
unsigned long offset,
|
||||
const struct exynos_cpuclk_cfg_data *cfg,
|
||||
unsigned long num_cfgs, unsigned long flags);
|
||||
|
@ -808,14 +808,16 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
|
||||
static void __init exynos3250_cmu_init(struct device_node *np)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
ctx = samsung_cmu_register_one(np, &cmu_info);
|
||||
if (!ctx)
|
||||
return;
|
||||
|
||||
hws = ctx->clk_data.hws;
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_core_p[0], mout_core_p[1], 0x14200,
|
||||
e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
|
||||
0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
|
||||
CLK_CPU_HAS_DIV1);
|
||||
|
||||
exynos3_core_down_clock(ctx->reg_base);
|
||||
|
@ -1233,6 +1233,8 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
enum exynos4_soc soc)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
exynos4_soc = soc;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -1240,6 +1242,7 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
|
||||
@ -1302,7 +1305,7 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
exynos4210_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4210_fixed_factor_clks));
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_core_p4210[0], mout_core_p4210[1], 0x14200,
|
||||
hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
|
||||
e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
|
||||
} else {
|
||||
@ -1317,7 +1320,7 @@ static void __init exynos4_clk_init(struct device_node *np,
|
||||
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
|
||||
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
|
||||
e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
|
||||
}
|
||||
|
@ -253,14 +253,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
|
||||
/*
|
||||
* CMU_CPU
|
||||
*/
|
||||
MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
|
||||
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
|
||||
|
||||
/*
|
||||
* CMU_CORE
|
||||
*/
|
||||
MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
|
||||
MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
|
||||
|
||||
/*
|
||||
* CMU_TOP
|
||||
@ -782,6 +782,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
unsigned int tmp;
|
||||
struct clk_hw **hws;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -792,6 +793,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
||||
}
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
|
||||
@ -821,7 +823,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
||||
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
|
||||
ARRAY_SIZE(exynos5250_gate_clks));
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_cpu_p[0], mout_cpu_p[1], 0x200,
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
|
||||
exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
|
||||
CLK_CPU_HAS_DIV1);
|
||||
|
||||
|
@ -596,13 +596,14 @@ static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
|
||||
static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
||||
MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
|
||||
SRC_TOP7, 4, 1),
|
||||
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
|
||||
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
|
||||
|
||||
MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
|
||||
MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p,
|
||||
SRC_TOP7, 8, 2),
|
||||
MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p,
|
||||
SRC_TOP7, 12, 2),
|
||||
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
|
||||
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
|
||||
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
|
||||
MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
|
||||
MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
|
||||
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
|
||||
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
|
||||
|
||||
@ -712,8 +713,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
||||
SRC_TOP12, 8, 1),
|
||||
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
|
||||
SRC_TOP12, 12, 1),
|
||||
MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
|
||||
SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
|
||||
SRC_TOP12, 20, 1),
|
||||
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
|
||||
@ -1560,6 +1561,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
enum exynos5x_soc soc)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
@ -1572,6 +1574,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
exynos5x_soc = soc;
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
|
||||
@ -1623,15 +1626,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
|
||||
if (soc == EXYNOS5420) {
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_cpu_p[0], mout_cpu_p[1], 0x200,
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
|
||||
exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
|
||||
} else {
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_cpu_p[0], mout_cpu_p[1], 0x200,
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
|
||||
exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
|
||||
}
|
||||
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
|
||||
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
|
||||
hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
|
||||
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
|
||||
|
||||
samsung_clk_extended_sleep_init(reg_base,
|
||||
@ -1654,7 +1657,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
* that the internal busses get their clock regardless of the
|
||||
* main G3D clock enablement status.
|
||||
*/
|
||||
clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
|
||||
clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
|
||||
/*
|
||||
* Keep top BPLL mux enabled permanently to ensure that DRAM operates
|
||||
* properly.
|
||||
*/
|
||||
clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
@ -3679,6 +3679,7 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
@ -3701,8 +3702,10 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np)
|
||||
samsung_clk_register_gate(ctx, apollo_gate_clks,
|
||||
ARRAY_SIZE(apollo_gate_clks));
|
||||
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
|
||||
mout_apollo_p[0], mout_apollo_p[1], 0x200,
|
||||
hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
|
||||
exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
|
||||
CLK_CPU_HAS_E5433_REGS_LAYOUT);
|
||||
|
||||
@ -3933,6 +3936,7 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
@ -3955,8 +3959,10 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np)
|
||||
samsung_clk_register_gate(ctx, atlas_gate_clks,
|
||||
ARRAY_SIZE(atlas_gate_clks));
|
||||
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
|
||||
mout_atlas_p[0], mout_atlas_p[1], 0x200,
|
||||
hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
|
||||
exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
|
||||
CLK_CPU_HAS_E5433_REGS_LAYOUT);
|
||||
|
||||
|
@ -21,19 +21,6 @@ static const struct clk_parent_data pll_mux[] = {
|
||||
.name = "f2s-free-clk", },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cntr_mux[] = {
|
||||
{ .fw_name = "main_pll",
|
||||
.name = "main_pll", },
|
||||
{ .fw_name = "periph_pll",
|
||||
.name = "periph_pll", },
|
||||
{ .fw_name = "osc1",
|
||||
.name = "osc1", },
|
||||
{ .fw_name = "cb-intosc-hs-div2-clk",
|
||||
.name = "cb-intosc-hs-div2-clk", },
|
||||
{ .fw_name = "f2s-free-clk",
|
||||
.name = "f2s-free-clk", },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data boot_mux[] = {
|
||||
{ .fw_name = "osc1",
|
||||
.name = "osc1", },
|
||||
|
@ -17,6 +17,16 @@ config SUN50I_A64_CCU
|
||||
default ARM64 && ARCH_SUNXI
|
||||
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
|
||||
|
||||
config SUN50I_A100_CCU
|
||||
bool "Support for the Allwinner A100 CCU"
|
||||
default ARM64 && ARCH_SUNXI
|
||||
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
|
||||
|
||||
config SUN50I_A100_R_CCU
|
||||
bool "Support for the Allwinner A100 PRCM CCU"
|
||||
default ARM64 && ARCH_SUNXI
|
||||
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
|
||||
|
||||
config SUN50I_H6_CCU
|
||||
bool "Support for the Allwinner H6 CCU"
|
||||
default ARM64 && ARCH_SUNXI
|
||||
|
@ -23,6 +23,8 @@ obj-y += ccu_mp.o
|
||||
# SoC support
|
||||
obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
|
||||
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
|
||||
obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
|
||||
obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
|
||||
obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
|
||||
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
|
||||
obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
|
||||
|
214
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
Normal file
214
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
Normal file
@ -0,0 +1,214 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "ccu_common.h"
|
||||
#include "ccu_reset.h"
|
||||
|
||||
#include "ccu_div.h"
|
||||
#include "ccu_gate.h"
|
||||
#include "ccu_mp.h"
|
||||
#include "ccu_nm.h"
|
||||
|
||||
#include "ccu-sun50i-a100-r.h"
|
||||
|
||||
static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
|
||||
"iosc", "pll-periph0" };
|
||||
static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
|
||||
{ .index = 3, .shift = 0, .width = 5 },
|
||||
};
|
||||
|
||||
static struct ccu_div r_cpus_clk = {
|
||||
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
|
||||
|
||||
.mux = {
|
||||
.shift = 24,
|
||||
.width = 2,
|
||||
|
||||
.var_predivs = cpus_r_apb2_predivs,
|
||||
.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
|
||||
},
|
||||
|
||||
.common = {
|
||||
.reg = 0x000,
|
||||
.features = CCU_FEATURE_VARIABLE_PREDIV,
|
||||
.hw.init = CLK_HW_INIT_PARENTS("cpus",
|
||||
cpus_r_apb2_parents,
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
},
|
||||
};
|
||||
|
||||
static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
|
||||
|
||||
static struct ccu_div r_apb1_clk = {
|
||||
.div = _SUNXI_CCU_DIV(0, 2),
|
||||
|
||||
.common = {
|
||||
.reg = 0x00c,
|
||||
.hw.init = CLK_HW_INIT("r-apb1",
|
||||
"r-ahb",
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
},
|
||||
};
|
||||
|
||||
static struct ccu_div r_apb2_clk = {
|
||||
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
|
||||
|
||||
.mux = {
|
||||
.shift = 24,
|
||||
.width = 2,
|
||||
|
||||
.var_predivs = cpus_r_apb2_predivs,
|
||||
.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
|
||||
},
|
||||
|
||||
.common = {
|
||||
.reg = 0x010,
|
||||
.features = CCU_FEATURE_VARIABLE_PREDIV,
|
||||
.hw.init = CLK_HW_INIT_PARENTS("r-apb2",
|
||||
cpus_r_apb2_parents,
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_parent_data clk_parent_r_apb1[] = {
|
||||
{ .hw = &r_apb1_clk.common.hw },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data clk_parent_r_apb2[] = {
|
||||
{ .hw = &r_apb2_clk.common.hw },
|
||||
};
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
|
||||
0x11c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
|
||||
0x12c, BIT(0), 0);
|
||||
|
||||
static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
|
||||
"iosc" };
|
||||
static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents,
|
||||
0x130, 24, 2, 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm",
|
||||
clk_parent_r_apb1, 0x13c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb1_ppu_clk, "r-apb1-ppu", clk_parent_r_apb1,
|
||||
0x17c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2,
|
||||
0x18c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2,
|
||||
0x19c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2,
|
||||
0x19c, BIT(1), 0);
|
||||
|
||||
static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };
|
||||
static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",
|
||||
r_apb1_ir_rx_parents, 0x1c0,
|
||||
0, 5, /* M */
|
||||
8, 2, /* P */
|
||||
24, 1, /* mux */
|
||||
BIT(31), /* gate */
|
||||
0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx",
|
||||
clk_parent_r_apb1, 0x1cc, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
|
||||
0x20c, BIT(0), 0);
|
||||
|
||||
static struct ccu_common *sun50i_a100_r_ccu_clks[] = {
|
||||
&r_cpus_clk.common,
|
||||
&r_apb1_clk.common,
|
||||
&r_apb2_clk.common,
|
||||
&r_apb1_timer_clk.common,
|
||||
&r_apb1_twd_clk.common,
|
||||
&r_apb1_pwm_clk.common,
|
||||
&r_apb1_bus_pwm_clk.common,
|
||||
&r_apb1_ppu_clk.common,
|
||||
&r_apb2_uart_clk.common,
|
||||
&r_apb2_i2c0_clk.common,
|
||||
&r_apb2_i2c1_clk.common,
|
||||
&r_apb1_ir_rx_clk.common,
|
||||
&r_apb1_bus_ir_rx_clk.common,
|
||||
&r_ahb_bus_rtc_clk.common,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_R_CPUS] = &r_cpus_clk.common.hw,
|
||||
[CLK_R_AHB] = &r_ahb_clk.hw,
|
||||
[CLK_R_APB1] = &r_apb1_clk.common.hw,
|
||||
[CLK_R_APB2] = &r_apb2_clk.common.hw,
|
||||
[CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
|
||||
[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
|
||||
[CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
|
||||
[CLK_R_APB1_BUS_PWM] = &r_apb1_bus_pwm_clk.common.hw,
|
||||
[CLK_R_APB1_PPU] = &r_apb1_ppu_clk.common.hw,
|
||||
[CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
|
||||
[CLK_R_APB2_I2C0] = &r_apb2_i2c0_clk.common.hw,
|
||||
[CLK_R_APB2_I2C1] = &r_apb2_i2c1_clk.common.hw,
|
||||
[CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw,
|
||||
[CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw,
|
||||
[CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER,
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
|
||||
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
|
||||
[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
|
||||
[RST_R_APB1_PPU] = { 0x17c, BIT(16) },
|
||||
[RST_R_APB2_UART] = { 0x18c, BIT(16) },
|
||||
[RST_R_APB2_I2C0] = { 0x19c, BIT(16) },
|
||||
[RST_R_APB2_I2C1] = { 0x19c, BIT(17) },
|
||||
[RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) },
|
||||
[RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun50i_a100_r_ccu_desc = {
|
||||
.ccu_clks = sun50i_a100_r_ccu_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun50i_a100_r_ccu_clks),
|
||||
|
||||
.hw_clks = &sun50i_a100_r_hw_clks,
|
||||
|
||||
.resets = sun50i_a100_r_ccu_resets,
|
||||
.num_resets = ARRAY_SIZE(sun50i_a100_r_ccu_resets),
|
||||
};
|
||||
|
||||
static int sun50i_a100_r_ccu_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *reg;
|
||||
|
||||
reg = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(reg))
|
||||
return PTR_ERR(reg);
|
||||
|
||||
return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a100_r_ccu_desc);
|
||||
}
|
||||
|
||||
static const struct of_device_id sun50i_a100_r_ccu_ids[] = {
|
||||
{ .compatible = "allwinner,sun50i-a100-r-ccu" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver sun50i_a100_r_ccu_driver = {
|
||||
.probe = sun50i_a100_r_ccu_probe,
|
||||
.driver = {
|
||||
.name = "sun50i-a100-r-ccu",
|
||||
.of_match_table = sun50i_a100_r_ccu_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun50i_a100_r_ccu_driver);
|
21
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
Normal file
21
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
Normal file
@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUN50I_A100_R_H
|
||||
#define _CCU_SUN50I_A100_R_H
|
||||
|
||||
#include <dt-bindings/clock/sun50i-a100-r-ccu.h>
|
||||
#include <dt-bindings/reset/sun50i-a100-r-ccu.h>
|
||||
|
||||
#define CLK_R_CPUS 0
|
||||
#define CLK_R_AHB 1
|
||||
|
||||
/* exported except APB1 for R_PIO */
|
||||
|
||||
#define CLK_R_APB2 3
|
||||
|
||||
#define CLK_NUMBER (CLK_R_AHB_BUS_RTC + 1)
|
||||
|
||||
#endif /* _CCU_SUN50I_A100_R_H */
|
1276
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
Normal file
1276
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
Normal file
File diff suppressed because it is too large
Load Diff
56
drivers/clk/sunxi-ng/ccu-sun50i-a100.h
Normal file
56
drivers/clk/sunxi-ng/ccu-sun50i-a100.h
Normal file
@ -0,0 +1,56 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUN50I_A100_H_
|
||||
#define _CCU_SUN50I_A100_H_
|
||||
|
||||
#include <dt-bindings/clock/sun50i-a100-ccu.h>
|
||||
#include <dt-bindings/reset/sun50i-a100-ccu.h>
|
||||
|
||||
#define CLK_OSC12M 0
|
||||
#define CLK_PLL_CPUX 1
|
||||
#define CLK_PLL_DDR0 2
|
||||
|
||||
/* PLL_PERIPH0 exported for PRCM */
|
||||
|
||||
#define CLK_PLL_PERIPH0_2X 4
|
||||
#define CLK_PLL_PERIPH1 5
|
||||
#define CLK_PLL_PERIPH1_2X 6
|
||||
#define CLK_PLL_GPU 7
|
||||
#define CLK_PLL_VIDEO0 8
|
||||
#define CLK_PLL_VIDEO0_2X 9
|
||||
#define CLK_PLL_VIDEO0_4X 10
|
||||
#define CLK_PLL_VIDEO1 11
|
||||
#define CLK_PLL_VIDEO1_2X 12
|
||||
#define CLK_PLL_VIDEO1_4X 13
|
||||
#define CLK_PLL_VIDEO2 14
|
||||
#define CLK_PLL_VIDEO2_2X 15
|
||||
#define CLK_PLL_VIDEO2_4X 16
|
||||
#define CLK_PLL_VIDEO3 17
|
||||
#define CLK_PLL_VIDEO3_2X 18
|
||||
#define CLK_PLL_VIDEO3_4X 19
|
||||
#define CLK_PLL_VE 20
|
||||
#define CLK_PLL_COM 21
|
||||
#define CLK_PLL_COM_AUDIO 22
|
||||
#define CLK_PLL_AUDIO 23
|
||||
|
||||
/* CPUX clock exported for DVFS */
|
||||
|
||||
#define CLK_AXI 25
|
||||
#define CLK_CPUX_APB 26
|
||||
#define CLK_PSI_AHB1_AHB2 27
|
||||
#define CLK_AHB3 28
|
||||
|
||||
/* APB1 clock exported for PIO */
|
||||
|
||||
#define CLK_APB2 30
|
||||
|
||||
/* All module clocks and bus gates are exported except DRAM */
|
||||
|
||||
#define CLK_BUS_DRAM 58
|
||||
|
||||
#define CLK_NUMBER (CLK_CSI_ISP + 1)
|
||||
|
||||
#endif /* _CCU_SUN50I_A100_H_ */
|
@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = {
|
||||
* the base (2x, 4x and 8x), and one variable divider (the one true
|
||||
* pll audio).
|
||||
*
|
||||
* We don't have any need for the variable divider for now, so we just
|
||||
* hardcode it to match with the clock names
|
||||
* With sigma-delta modulation for fractional-N on the audio PLL,
|
||||
* we have to use specific dividers. This means the variable divider
|
||||
* can no longer be used, as the audio codec requests the exact clock
|
||||
* rates we support through this mechanism. So we now hard code the
|
||||
* variable divider to 1. This means the clock rates will no longer
|
||||
* match the clock names.
|
||||
*/
|
||||
#define SUN8I_R40_PLL_AUDIO_REG 0x008
|
||||
|
||||
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
||||
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
|
||||
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
|
||||
};
|
||||
|
||||
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
pll_audio_sdm_table, BIT(24),
|
||||
0x284, BIT(31),
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
|
||||
"osc24M", 0x0010,
|
||||
@ -952,10 +963,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
|
||||
&pll_audio_base_clk.common.hw
|
||||
};
|
||||
|
||||
/* We hardcode the divider to 4 for now */
|
||||
/* We hardcode the divider to 1 for now */
|
||||
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
|
||||
clk_parent_pll_audio,
|
||||
4, 1, CLK_SET_RATE_PARENT);
|
||||
1, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
|
||||
clk_parent_pll_audio,
|
||||
2, 1, CLK_SET_RATE_PARENT);
|
||||
@ -1307,10 +1318,10 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(reg))
|
||||
return PTR_ERR(reg);
|
||||
|
||||
/* Force the PLL-Audio-1x divider to 4 */
|
||||
/* Force the PLL-Audio-1x divider to 1 */
|
||||
val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||
val &= ~GENMASK(19, 16);
|
||||
writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||
writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||
|
||||
/* Force PLL-MIPI to MIPI mode */
|
||||
val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
|
||||
|
@ -172,8 +172,10 @@
|
||||
#define CLK_MOUT_GPLL 1025
|
||||
#define CLK_MOUT_ACLK200_DISP1_SUB 1026
|
||||
#define CLK_MOUT_ACLK300_DISP1_SUB 1027
|
||||
#define CLK_MOUT_APLL 1028
|
||||
#define CLK_MOUT_MPLL 1029
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 1028
|
||||
#define CLK_NR_CLKS 1030
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
|
||||
|
@ -230,6 +230,12 @@
|
||||
#define CLK_MOUT_USER_MAU_EPLL 659
|
||||
#define CLK_MOUT_SCLK_SPLL 660
|
||||
#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
|
||||
#define CLK_MOUT_SW_ACLK_G3D 662
|
||||
#define CLK_MOUT_APLL 663
|
||||
#define CLK_MOUT_MSPLL_CPU 664
|
||||
#define CLK_MOUT_KPLL 665
|
||||
#define CLK_MOUT_MSPLL_KFC 666
|
||||
|
||||
|
||||
/* divider clocks */
|
||||
#define CLK_DOUT_PIXEL 768
|
||||
|
116
include/dt-bindings/clock/sun50i-a100-ccu.h
Normal file
116
include/dt-bindings/clock/sun50i-a100-ccu.h
Normal file
@ -0,0 +1,116 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_A100_H_
|
||||
|
||||
#define CLK_PLL_PERIPH0 3
|
||||
|
||||
#define CLK_CPUX 24
|
||||
|
||||
#define CLK_APB1 29
|
||||
|
||||
#define CLK_MBUS 31
|
||||
#define CLK_DE 32
|
||||
#define CLK_BUS_DE 33
|
||||
#define CLK_G2D 34
|
||||
#define CLK_BUS_G2D 35
|
||||
#define CLK_GPU 36
|
||||
#define CLK_BUS_GPU 37
|
||||
#define CLK_CE 38
|
||||
#define CLK_BUS_CE 39
|
||||
#define CLK_VE 40
|
||||
#define CLK_BUS_VE 41
|
||||
#define CLK_BUS_DMA 42
|
||||
#define CLK_BUS_MSGBOX 43
|
||||
#define CLK_BUS_SPINLOCK 44
|
||||
#define CLK_BUS_HSTIMER 45
|
||||
#define CLK_AVS 46
|
||||
#define CLK_BUS_DBG 47
|
||||
#define CLK_BUS_PSI 48
|
||||
#define CLK_BUS_PWM 49
|
||||
#define CLK_BUS_IOMMU 50
|
||||
#define CLK_MBUS_DMA 51
|
||||
#define CLK_MBUS_VE 52
|
||||
#define CLK_MBUS_CE 53
|
||||
#define CLK_MBUS_NAND 54
|
||||
#define CLK_MBUS_CSI 55
|
||||
#define CLK_MBUS_ISP 56
|
||||
#define CLK_MBUS_G2D 57
|
||||
|
||||
#define CLK_NAND0 59
|
||||
#define CLK_NAND1 60
|
||||
#define CLK_BUS_NAND 61
|
||||
#define CLK_MMC0 62
|
||||
#define CLK_MMC1 63
|
||||
#define CLK_MMC2 64
|
||||
#define CLK_MMC3 65
|
||||
#define CLK_BUS_MMC0 66
|
||||
#define CLK_BUS_MMC1 67
|
||||
#define CLK_BUS_MMC2 68
|
||||
#define CLK_BUS_UART0 69
|
||||
#define CLK_BUS_UART1 70
|
||||
#define CLK_BUS_UART2 71
|
||||
#define CLK_BUS_UART3 72
|
||||
#define CLK_BUS_UART4 73
|
||||
#define CLK_BUS_I2C0 74
|
||||
#define CLK_BUS_I2C1 75
|
||||
#define CLK_BUS_I2C2 76
|
||||
#define CLK_BUS_I2C3 77
|
||||
#define CLK_SPI0 78
|
||||
#define CLK_SPI1 79
|
||||
#define CLK_SPI2 80
|
||||
#define CLK_BUS_SPI0 81
|
||||
#define CLK_BUS_SPI1 82
|
||||
#define CLK_BUS_SPI2 83
|
||||
#define CLK_EMAC_25M 84
|
||||
#define CLK_BUS_EMAC 85
|
||||
#define CLK_IR_RX 86
|
||||
#define CLK_BUS_IR_RX 87
|
||||
#define CLK_IR_TX 88
|
||||
#define CLK_BUS_IR_TX 89
|
||||
#define CLK_BUS_GPADC 90
|
||||
#define CLK_BUS_THS 91
|
||||
#define CLK_I2S0 92
|
||||
#define CLK_I2S1 93
|
||||
#define CLK_I2S2 94
|
||||
#define CLK_I2S3 95
|
||||
#define CLK_BUS_I2S0 96
|
||||
#define CLK_BUS_I2S1 97
|
||||
#define CLK_BUS_I2S2 98
|
||||
#define CLK_BUS_I2S3 99
|
||||
#define CLK_SPDIF 100
|
||||
#define CLK_BUS_SPDIF 101
|
||||
#define CLK_DMIC 102
|
||||
#define CLK_BUS_DMIC 103
|
||||
#define CLK_AUDIO_DAC 104
|
||||
#define CLK_AUDIO_ADC 105
|
||||
#define CLK_AUDIO_4X 106
|
||||
#define CLK_BUS_AUDIO_CODEC 107
|
||||
#define CLK_USB_OHCI0 108
|
||||
#define CLK_USB_PHY0 109
|
||||
#define CLK_USB_OHCI1 110
|
||||
#define CLK_USB_PHY1 111
|
||||
#define CLK_BUS_OHCI0 112
|
||||
#define CLK_BUS_OHCI1 113
|
||||
#define CLK_BUS_EHCI0 114
|
||||
#define CLK_BUS_EHCI1 115
|
||||
#define CLK_BUS_OTG 116
|
||||
#define CLK_BUS_LRADC 117
|
||||
#define CLK_BUS_DPSS_TOP0 118
|
||||
#define CLK_BUS_DPSS_TOP1 119
|
||||
#define CLK_MIPI_DSI 120
|
||||
#define CLK_BUS_MIPI_DSI 121
|
||||
#define CLK_TCON_LCD 122
|
||||
#define CLK_BUS_TCON_LCD 123
|
||||
#define CLK_LEDC 124
|
||||
#define CLK_BUS_LEDC 125
|
||||
#define CLK_CSI_TOP 126
|
||||
#define CLK_CSI0_MCLK 127
|
||||
#define CLK_CSI1_MCLK 128
|
||||
#define CLK_BUS_CSI 129
|
||||
#define CLK_CSI_ISP 130
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */
|
23
include/dt-bindings/clock/sun50i-a100-r-ccu.h
Normal file
23
include/dt-bindings/clock/sun50i-a100-r-ccu.h
Normal file
@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
|
||||
|
||||
#define CLK_R_APB1 2
|
||||
|
||||
#define CLK_R_APB1_TIMER 4
|
||||
#define CLK_R_APB1_TWD 5
|
||||
#define CLK_R_APB1_PWM 6
|
||||
#define CLK_R_APB1_BUS_PWM 7
|
||||
#define CLK_R_APB1_PPU 8
|
||||
#define CLK_R_APB2_UART 9
|
||||
#define CLK_R_APB2_I2C0 10
|
||||
#define CLK_R_APB2_I2C1 11
|
||||
#define CLK_R_APB1_IR 12
|
||||
#define CLK_R_APB1_BUS_IR 13
|
||||
#define CLK_R_AHB_BUS_RTC 14
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */
|
68
include/dt-bindings/reset/sun50i-a100-ccu.h
Normal file
68
include/dt-bindings/reset/sun50i-a100-ccu.h
Normal file
@ -0,0 +1,68 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_
|
||||
#define _DT_BINDINGS_RESET_SUN50I_A100_H_
|
||||
|
||||
#define RST_MBUS 0
|
||||
#define RST_BUS_DE 1
|
||||
#define RST_BUS_G2D 2
|
||||
#define RST_BUS_GPU 3
|
||||
#define RST_BUS_CE 4
|
||||
#define RST_BUS_VE 5
|
||||
#define RST_BUS_DMA 6
|
||||
#define RST_BUS_MSGBOX 7
|
||||
#define RST_BUS_SPINLOCK 8
|
||||
#define RST_BUS_HSTIMER 9
|
||||
#define RST_BUS_DBG 10
|
||||
#define RST_BUS_PSI 11
|
||||
#define RST_BUS_PWM 12
|
||||
#define RST_BUS_DRAM 13
|
||||
#define RST_BUS_NAND 14
|
||||
#define RST_BUS_MMC0 15
|
||||
#define RST_BUS_MMC1 16
|
||||
#define RST_BUS_MMC2 17
|
||||
#define RST_BUS_UART0 18
|
||||
#define RST_BUS_UART1 19
|
||||
#define RST_BUS_UART2 20
|
||||
#define RST_BUS_UART3 21
|
||||
#define RST_BUS_UART4 22
|
||||
#define RST_BUS_I2C0 23
|
||||
#define RST_BUS_I2C1 24
|
||||
#define RST_BUS_I2C2 25
|
||||
#define RST_BUS_I2C3 26
|
||||
#define RST_BUS_SPI0 27
|
||||
#define RST_BUS_SPI1 28
|
||||
#define RST_BUS_SPI2 29
|
||||
#define RST_BUS_EMAC 30
|
||||
#define RST_BUS_IR_RX 31
|
||||
#define RST_BUS_IR_TX 32
|
||||
#define RST_BUS_GPADC 33
|
||||
#define RST_BUS_THS 34
|
||||
#define RST_BUS_I2S0 35
|
||||
#define RST_BUS_I2S1 36
|
||||
#define RST_BUS_I2S2 37
|
||||
#define RST_BUS_I2S3 38
|
||||
#define RST_BUS_SPDIF 39
|
||||
#define RST_BUS_DMIC 40
|
||||
#define RST_BUS_AUDIO_CODEC 41
|
||||
#define RST_USB_PHY0 42
|
||||
#define RST_USB_PHY1 43
|
||||
#define RST_BUS_OHCI0 44
|
||||
#define RST_BUS_OHCI1 45
|
||||
#define RST_BUS_EHCI0 46
|
||||
#define RST_BUS_EHCI1 47
|
||||
#define RST_BUS_OTG 48
|
||||
#define RST_BUS_LRADC 49
|
||||
#define RST_BUS_DPSS_TOP0 50
|
||||
#define RST_BUS_DPSS_TOP1 51
|
||||
#define RST_BUS_MIPI_DSI 52
|
||||
#define RST_BUS_TCON_LCD 53
|
||||
#define RST_BUS_LVDS 54
|
||||
#define RST_BUS_LEDC 55
|
||||
#define RST_BUS_CSI 56
|
||||
#define RST_BUS_CSI_ISP 57
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */
|
18
include/dt-bindings/reset/sun50i-a100-r-ccu.h
Normal file
18
include/dt-bindings/reset/sun50i-a100-r-ccu.h
Normal file
@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_
|
||||
#define _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_
|
||||
|
||||
#define RST_R_APB1_TIMER 0
|
||||
#define RST_R_APB1_BUS_PWM 1
|
||||
#define RST_R_APB1_PPU 2
|
||||
#define RST_R_APB2_UART 3
|
||||
#define RST_R_APB2_I2C0 4
|
||||
#define RST_R_APB2_I2C1 5
|
||||
#define RST_R_APB1_BUS_IR 6
|
||||
#define RST_R_AHB_BUS_RTC 7
|
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ */
|
Loading…
Reference in New Issue
Block a user