forked from Minki/linux
Merge branch 'devel-stable' into devel
This commit is contained in:
commit
9bafc74163
@ -727,9 +727,11 @@ config ARCH_S5PC100
|
||||
config ARCH_S5PV210
|
||||
bool "Samsung S5PV210/S5PC110"
|
||||
select CPU_V7
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select GENERIC_GPIO
|
||||
select HAVE_CLK
|
||||
select ARM_L1_CACHE_SHIFT_6
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select HAVE_S3C2410_I2C
|
||||
select HAVE_S3C_RTC
|
||||
@ -740,9 +742,13 @@ config ARCH_S5PV210
|
||||
config ARCH_S5PV310
|
||||
bool "Samsung S5PV310/S5PC210"
|
||||
select CPU_V7
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select GENERIC_GPIO
|
||||
select HAVE_CLK
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_S3C_RTC
|
||||
select HAVE_S3C2410_I2C
|
||||
select HAVE_S3C2410_WATCHDOG
|
||||
help
|
||||
Samsung S5PV310 series based systems
|
||||
|
||||
@ -1669,6 +1675,12 @@ if ARCH_HAS_CPUFREQ
|
||||
|
||||
source "drivers/cpufreq/Kconfig"
|
||||
|
||||
config CPU_FREQ_IMX
|
||||
tristate "CPUfreq driver for i.MX CPUs"
|
||||
depends on ARCH_MXC && CPU_FREQ
|
||||
help
|
||||
This enables the CPUfreq driver for i.MX CPUs.
|
||||
|
||||
config CPU_FREQ_SA1100
|
||||
bool
|
||||
|
||||
|
@ -82,6 +82,7 @@ CONFIG_FEC=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
CONFIG_MOUSE_PS2=m
|
||||
CONFIG_MOUSE_PS2_ELANTECH=y
|
||||
|
@ -21,9 +21,6 @@
|
||||
#define __ASM_ARM_HARDWARE_L2X0_H
|
||||
|
||||
#define L2X0_CACHE_ID 0x000
|
||||
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
|
||||
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
|
||||
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
|
||||
#define L2X0_CACHE_TYPE 0x004
|
||||
#define L2X0_CTRL 0x100
|
||||
#define L2X0_AUX_CTRL 0x104
|
||||
@ -53,6 +50,16 @@
|
||||
#define L2X0_LINE_DATA 0xF10
|
||||
#define L2X0_LINE_TAG 0xF30
|
||||
#define L2X0_DEBUG_CTRL 0xF40
|
||||
#define L2X0_PREFETCH_CTRL 0xF60
|
||||
#define L2X0_POWER_CTRL 0xF80
|
||||
#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
|
||||
#define L2X0_STNDBY_MODE_EN (1 << 0)
|
||||
|
||||
/* Registers shifts and masks */
|
||||
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
|
||||
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
|
||||
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
|
||||
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
|
||||
|
@ -25,6 +25,9 @@ struct outer_cache_fns {
|
||||
void (*inv_range)(unsigned long, unsigned long);
|
||||
void (*clean_range)(unsigned long, unsigned long);
|
||||
void (*flush_range)(unsigned long, unsigned long);
|
||||
void (*flush_all)(void);
|
||||
void (*inv_all)(void);
|
||||
void (*disable)(void);
|
||||
#ifdef CONFIG_OUTER_CACHE_SYNC
|
||||
void (*sync)(void);
|
||||
#endif
|
||||
@ -50,6 +53,24 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
|
||||
outer_cache.flush_range(start, end);
|
||||
}
|
||||
|
||||
static inline void outer_flush_all(void)
|
||||
{
|
||||
if (outer_cache.flush_all)
|
||||
outer_cache.flush_all();
|
||||
}
|
||||
|
||||
static inline void outer_inv_all(void)
|
||||
{
|
||||
if (outer_cache.inv_all)
|
||||
outer_cache.inv_all();
|
||||
}
|
||||
|
||||
static inline void outer_disable(void)
|
||||
{
|
||||
if (outer_cache.disable)
|
||||
outer_cache.disable();
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void outer_inv_range(unsigned long start, unsigned long end)
|
||||
@ -58,6 +79,9 @@ static inline void outer_clean_range(unsigned long start, unsigned long end)
|
||||
{ }
|
||||
static inline void outer_flush_range(unsigned long start, unsigned long end)
|
||||
{ }
|
||||
static inline void outer_flush_all(void) { }
|
||||
static inline void outer_inv_all(void) { }
|
||||
static inline void outer_disable(void) { }
|
||||
|
||||
#endif
|
||||
|
||||
|
@ -78,7 +78,10 @@ void machine_kexec(struct kimage *image)
|
||||
local_fiq_disable();
|
||||
setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
|
||||
flush_cache_all();
|
||||
outer_flush_all();
|
||||
outer_disable();
|
||||
cpu_proc_fin();
|
||||
outer_inv_all();
|
||||
flush_cache_all();
|
||||
cpu_reset(reboot_code_buffer_phys);
|
||||
}
|
||||
|
@ -23,16 +23,20 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/input/matrix_keypad.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux-mx27.h>
|
||||
#include <mach/mmc.h>
|
||||
|
||||
#include "devices-imx27.h"
|
||||
#include "devices.h"
|
||||
|
||||
#define SD1_EN_GPIO (GPIO_PORTB + 25)
|
||||
|
||||
static const int mx27pdk_pins[] __initconst = {
|
||||
/* UART1 */
|
||||
PE12_PF_UART1_TXD,
|
||||
@ -58,6 +62,14 @@ static const int mx27pdk_pins[] __initconst = {
|
||||
PD15_AOUT_FEC_COL,
|
||||
PD16_AIN_FEC_TX_ER,
|
||||
PF23_AIN_FEC_TX_EN,
|
||||
/* SDHC1 */
|
||||
PE18_PF_SD1_D0,
|
||||
PE19_PF_SD1_D1,
|
||||
PE20_PF_SD1_D2,
|
||||
PE21_PF_SD1_D3,
|
||||
PE22_PF_SD1_CMD,
|
||||
PE23_PF_SD1_CLK,
|
||||
SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
|
||||
};
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
@ -85,13 +97,39 @@ static struct matrix_keymap_data mx27_3ds_keymap_data = {
|
||||
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
|
||||
};
|
||||
|
||||
static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
|
||||
void *data)
|
||||
{
|
||||
return request_irq(IRQ_GPIOB(26), detect_irq, IRQF_TRIGGER_FALLING |
|
||||
IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
|
||||
}
|
||||
|
||||
static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
|
||||
{
|
||||
free_irq(IRQ_GPIOB(26), data);
|
||||
}
|
||||
|
||||
static struct imxmmc_platform_data sdhc1_pdata = {
|
||||
.init = mx27_3ds_sdhc1_init,
|
||||
.exit = mx27_3ds_sdhc1_exit,
|
||||
};
|
||||
|
||||
static void mx27_3ds_sdhc1_enable_level_translator(void)
|
||||
{
|
||||
/* Turn on TXB0108 OE pin */
|
||||
gpio_request(SD1_EN_GPIO, "sd1_enable");
|
||||
gpio_direction_output(SD1_EN_GPIO, 1);
|
||||
}
|
||||
|
||||
static void __init mx27pdk_init(void)
|
||||
{
|
||||
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
|
||||
"mx27pdk");
|
||||
mx27_3ds_sdhc1_enable_level_translator();
|
||||
imx27_add_imx_uart0(&uart_pdata);
|
||||
imx27_add_fec(NULL);
|
||||
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
|
||||
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
|
||||
}
|
||||
|
||||
static void __init mx27pdk_timer_init(void)
|
||||
|
@ -6,6 +6,7 @@ config MACH_MX25_3DS
|
||||
bool "Support MX25PDK (3DS) Platform"
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_MXC_NAND
|
||||
select IMX_HAVE_PLATFORM_ESDHC
|
||||
|
||||
config MACH_EUKREA_CPUIMX25
|
||||
bool "Support Eukrea CPUIMX25 Platform"
|
||||
|
@ -96,6 +96,14 @@ static struct pad_desc mx25pdk_pads[] = {
|
||||
MX25_PAD_KPP_COL1__KPP_COL1,
|
||||
MX25_PAD_KPP_COL2__KPP_COL2,
|
||||
MX25_PAD_KPP_COL3__KPP_COL3,
|
||||
|
||||
/* SD1 */
|
||||
MX25_PAD_SD1_CMD__SD1_CMD,
|
||||
MX25_PAD_SD1_CLK__SD1_CLK,
|
||||
MX25_PAD_SD1_DATA0__SD1_DATA0,
|
||||
MX25_PAD_SD1_DATA1__SD1_DATA1,
|
||||
MX25_PAD_SD1_DATA2__SD1_DATA2,
|
||||
MX25_PAD_SD1_DATA3__SD1_DATA3,
|
||||
};
|
||||
|
||||
static const struct fec_platform_data mx25_fec_pdata __initconst = {
|
||||
@ -193,6 +201,8 @@ static void __init mx25pdk_init(void)
|
||||
mx25pdk_fec_reset();
|
||||
imx25_add_fec(&mx25_fec_pdata);
|
||||
mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
|
||||
|
||||
imx25_add_esdhc(0, NULL);
|
||||
}
|
||||
|
||||
static void __init mx25pdk_timer_init(void)
|
||||
|
@ -143,8 +143,10 @@ config MACH_ARMADILLO5X0
|
||||
config MACH_MX35_3DS
|
||||
bool "Support MX35PDK platform"
|
||||
select ARCH_MX35
|
||||
select MXC_DEBUG_BOARD
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_MXC_NAND
|
||||
select IMX_HAVE_PLATFORM_ESDHC
|
||||
default n
|
||||
help
|
||||
Include support for MX35PDK platform. This includes specific
|
||||
|
@ -72,24 +72,24 @@ struct platform_device mxc_w1_master_device = {
|
||||
#ifdef CONFIG_ARCH_MX31
|
||||
static struct resource mxcsdhc0_resources[] = {
|
||||
{
|
||||
.start = MMC_SDHC1_BASE_ADDR,
|
||||
.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
|
||||
.start = MX31_MMC_SDHC1_BASE_ADDR,
|
||||
.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = MXC_INT_MMC_SDHC1,
|
||||
.end = MXC_INT_MMC_SDHC1,
|
||||
.start = MX31_INT_MMC_SDHC1,
|
||||
.end = MX31_INT_MMC_SDHC1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource mxcsdhc1_resources[] = {
|
||||
{
|
||||
.start = MMC_SDHC2_BASE_ADDR,
|
||||
.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
|
||||
.start = MX31_MMC_SDHC2_BASE_ADDR,
|
||||
.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = MXC_INT_MMC_SDHC2,
|
||||
.end = MXC_INT_MMC_SDHC2,
|
||||
.start = MX31_INT_MMC_SDHC2,
|
||||
.end = MX31_INT_MMC_SDHC2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
@ -38,39 +38,9 @@
|
||||
#include "devices-imx31.h"
|
||||
#include "devices.h"
|
||||
|
||||
/* Definitions for components on the Debug board */
|
||||
|
||||
/* Base address of CPLD controller on the Debug board */
|
||||
#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
|
||||
|
||||
/* LAN9217 ethernet base address */
|
||||
#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
|
||||
|
||||
/* CPLD config and interrupt base address */
|
||||
#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
|
||||
|
||||
/* status, interrupt */
|
||||
#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
|
||||
#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
|
||||
#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
|
||||
/* magic word for debug CPLD */
|
||||
#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
|
||||
#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
|
||||
/* CPLD code version */
|
||||
#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
|
||||
/* magic word for debug CPLD */
|
||||
#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
|
||||
|
||||
/* CPLD IRQ line for external uart, external ethernet etc */
|
||||
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
|
||||
|
||||
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
|
||||
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
|
||||
|
||||
#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
|
||||
|
||||
#define MXC_MAX_EXP_IO_LINES 16
|
||||
|
||||
/*
|
||||
* This file contains the board-specific initialization routines.
|
||||
*/
|
||||
@ -272,7 +242,7 @@ static void __init mxc_board_init(void)
|
||||
imx31_add_imx_uart0(&uart_pdata);
|
||||
imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
|
||||
|
||||
imx31_add_spi_imx0(&spi1_pdata);
|
||||
imx31_add_spi_imx1(&spi1_pdata);
|
||||
spi_register_board_info(mx31_3ds_spi_devs,
|
||||
ARRAY_SIZE(mx31_3ds_spi_devs));
|
||||
|
||||
@ -281,9 +251,9 @@ static void __init mxc_board_init(void)
|
||||
mx31_3ds_usbotg_init();
|
||||
mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
|
||||
|
||||
if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
|
||||
if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
|
||||
printk(KERN_WARNING "Init of the debug board failed, all "
|
||||
"devices on the board are unusable.\n");
|
||||
"devices on the debug board are unusable.\n");
|
||||
}
|
||||
|
||||
static void __init mx31_3ds_timer_init(void)
|
||||
|
@ -38,11 +38,15 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux-mx35.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/3ds_debugboard.h>
|
||||
#include <mach/mxc_ehci.h>
|
||||
|
||||
#include "devices-imx35.h"
|
||||
#include "devices.h"
|
||||
|
||||
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
@ -108,6 +112,13 @@ static struct pad_desc mx35pdk_pads[] = {
|
||||
/* USBH1 */
|
||||
MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
|
||||
MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
|
||||
/* SDCARD */
|
||||
MX35_PAD_SD1_CMD__ESDHC1_CMD,
|
||||
MX35_PAD_SD1_CLK__ESDHC1_CLK,
|
||||
MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
|
||||
MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
|
||||
MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
|
||||
MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
|
||||
};
|
||||
|
||||
/* OTG config */
|
||||
@ -140,6 +151,11 @@ static void __init mxc_board_init(void)
|
||||
mxc_register_device(&mxc_usbh1, &usb_host_pdata);
|
||||
|
||||
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
|
||||
imx35_add_esdhc(0, NULL);
|
||||
|
||||
if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
|
||||
pr_warn("Init of the debugboard failed, all "
|
||||
"devices on the debugboard are unusable.\n");
|
||||
}
|
||||
|
||||
static void __init mx35pdk_timer_init(void)
|
||||
|
@ -6,6 +6,7 @@ config ARCH_MX51
|
||||
select MXC_TZIC
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select ARCH_MXC_AUDMUX_V2
|
||||
select ARCH_HAS_CPUFREQ
|
||||
|
||||
comment "MX5 platforms:"
|
||||
|
||||
@ -13,6 +14,7 @@ config MACH_MX51_BABBAGE
|
||||
bool "Support MX51 BABBAGE platforms"
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_ESDHC
|
||||
help
|
||||
Include support for MX51 Babbage platform, also known as MX51EVK in
|
||||
u-boot. This includes specific configurations for the board and its
|
||||
|
@ -5,6 +5,7 @@
|
||||
# Object file lists.
|
||||
obj-y := cpu.o mm.o clock-mx51.o devices.o
|
||||
|
||||
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
|
||||
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
|
||||
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
|
||||
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
@ -18,6 +18,8 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/fsl_devices.h>
|
||||
#include <linux/fec.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
@ -32,11 +34,13 @@
|
||||
|
||||
#include "devices-imx51.h"
|
||||
#include "devices.h"
|
||||
#include "cpu_op-mx51.h"
|
||||
|
||||
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
|
||||
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
|
||||
#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
|
||||
#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
|
||||
#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
|
||||
|
||||
/* USB_CTRL_1 */
|
||||
#define MX51_USB_CTRL_1_OFFSET 0x10
|
||||
@ -46,6 +50,21 @@
|
||||
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
|
||||
#define MX51_USB_PLL_DIV_24_MHZ 0x02
|
||||
|
||||
static struct gpio_keys_button babbage_buttons[] = {
|
||||
{
|
||||
.gpio = BABBAGE_POWER_KEY,
|
||||
.code = BTN_0,
|
||||
.desc = "PWR",
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_keys_platform_data imx_button_data __initconst = {
|
||||
.buttons = babbage_buttons,
|
||||
.nbuttons = ARRAY_SIZE(babbage_buttons),
|
||||
};
|
||||
|
||||
static struct pad_desc mx51babbage_pads[] = {
|
||||
/* UART1 */
|
||||
MX51_PAD_UART1_RXD__UART1_RXD,
|
||||
@ -112,6 +131,22 @@ static struct pad_desc mx51babbage_pads[] = {
|
||||
|
||||
/* FEC PHY reset line */
|
||||
MX51_PAD_EIM_A20__GPIO_2_14,
|
||||
|
||||
/* SD 1 */
|
||||
MX51_PAD_SD1_CMD__SD1_CMD,
|
||||
MX51_PAD_SD1_CLK__SD1_CLK,
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0,
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1,
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2,
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3,
|
||||
|
||||
/* SD 2 */
|
||||
MX51_PAD_SD2_CMD__SD2_CMD,
|
||||
MX51_PAD_SD2_CLK__SD2_CLK,
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0,
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1,
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2,
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3,
|
||||
};
|
||||
|
||||
/* Serial ports */
|
||||
@ -281,13 +316,22 @@ __setup("otg_mode=", babbage_otg_mode);
|
||||
static void __init mxc_board_init(void)
|
||||
{
|
||||
struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
|
||||
struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ_IMX)
|
||||
get_cpu_op = mx51_get_cpu_op;
|
||||
#endif
|
||||
mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
|
||||
ARRAY_SIZE(mx51babbage_pads));
|
||||
mxc_init_imx_uart();
|
||||
babbage_fec_reset();
|
||||
imx51_add_fec(NULL);
|
||||
|
||||
/* Set the PAD settings for the pwr key. */
|
||||
power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
|
||||
mxc_iomux_v3_setup_pad(&power_key);
|
||||
imx51_add_gpio_keys(&imx_button_data);
|
||||
|
||||
imx51_add_imx_i2c(0, &babbage_i2c_data);
|
||||
imx51_add_imx_i2c(1, &babbage_i2c_data);
|
||||
mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
|
||||
@ -304,6 +348,9 @@ static void __init mxc_board_init(void)
|
||||
/* setback USBH1_STP to be function */
|
||||
mxc_iomux_v3_setup_pad(&usbh1stp);
|
||||
babbage_usbhub_reset();
|
||||
|
||||
imx51_add_esdhc(0, NULL);
|
||||
imx51_add_esdhc(1, NULL);
|
||||
}
|
||||
|
||||
static void __init mx51_babbage_timer_init(void)
|
||||
|
@ -362,7 +362,7 @@ static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long clk_arm_get_rate(struct clk *clk)
|
||||
static unsigned long clk_cpu_get_rate(struct clk *clk)
|
||||
{
|
||||
u32 cacrr, div;
|
||||
unsigned long parent_rate;
|
||||
@ -374,6 +374,22 @@ static unsigned long clk_arm_get_rate(struct clk *clk)
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 reg, cpu_podf;
|
||||
unsigned long parent_rate;
|
||||
|
||||
parent_rate = clk_get_rate(clk->parent);
|
||||
cpu_podf = parent_rate / rate - 1;
|
||||
/* use post divider to change freq */
|
||||
reg = __raw_readl(MXC_CCM_CACRR);
|
||||
reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
|
||||
reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
|
||||
__raw_writel(reg, MXC_CCM_CACRR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
u32 reg, mux;
|
||||
@ -736,7 +752,8 @@ static struct clk periph_apm_clk = {
|
||||
|
||||
static struct clk cpu_clk = {
|
||||
.parent = &pll1_sw_clk,
|
||||
.get_rate = clk_arm_get_rate,
|
||||
.get_rate = clk_cpu_get_rate,
|
||||
.set_rate = clk_cpu_set_rate,
|
||||
};
|
||||
|
||||
static struct clk ahb_clk = {
|
||||
@ -1064,6 +1081,7 @@ static struct clk_lookup lookups[] = {
|
||||
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
|
||||
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
|
||||
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
|
||||
_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
|
||||
};
|
||||
|
||||
static void clk_tree_init(void)
|
||||
|
29
arch/arm/mach-mx5/cpu_op-mx51.c
Normal file
29
arch/arm/mach-mx5/cpu_op-mx51.c
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
static struct cpu_op mx51_cpu_op[] = {
|
||||
{
|
||||
.cpu_rate = 160000000,},
|
||||
{
|
||||
.cpu_rate = 800000000,},
|
||||
};
|
||||
|
||||
struct cpu_op *mx51_get_cpu_op(int *op)
|
||||
{
|
||||
*op = ARRAY_SIZE(mx51_cpu_op);
|
||||
return mx51_cpu_op;
|
||||
}
|
14
arch/arm/mach-mx5/cpu_op-mx51.h
Normal file
14
arch/arm/mach-mx5/cpu_op-mx51.h
Normal file
@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
extern struct cpu_op *mx51_get_cpu_op(int *op);
|
@ -13,6 +13,8 @@ extern const struct imx_fec_data imx51_fec_data __initconst;
|
||||
#define imx51_add_fec(pdata) \
|
||||
imx_add_fec(&imx51_fec_data, pdata)
|
||||
|
||||
#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
|
||||
|
||||
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
|
||||
#define imx51_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
|
||||
|
@ -44,6 +44,13 @@ void __init gic_init_irq(void)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
|
||||
static void omap4_l2x0_disable(void)
|
||||
{
|
||||
/* Disable PL310 L2 Cache controller */
|
||||
omap_smc1(0x102, 0x0);
|
||||
}
|
||||
|
||||
static int __init omap_l2_cache_init(void)
|
||||
{
|
||||
/*
|
||||
@ -70,6 +77,12 @@ static int __init omap_l2_cache_init(void)
|
||||
else
|
||||
l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
|
||||
|
||||
/*
|
||||
* Override default outer_cache.disable with a OMAP4
|
||||
* specific one
|
||||
*/
|
||||
outer_cache.disable = omap4_l2x0_disable;
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_initcall(omap_l2_cache_init);
|
||||
|
@ -22,6 +22,8 @@
|
||||
|
||||
#ifdef CONFIG_CPU_S3C244X
|
||||
#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
|
||||
#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
|
||||
#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
|
||||
#else
|
||||
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
|
||||
#endif
|
||||
@ -30,8 +32,10 @@
|
||||
#include <mach/gpio-nrs.h>
|
||||
#include <mach/gpio-fns.h>
|
||||
|
||||
#ifdef CONFIG_CPU_S3C24XX
|
||||
#define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32)
|
||||
#ifdef CONFIG_CPU_S3C244X
|
||||
#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
|
||||
#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
|
||||
#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
|
||||
#else
|
||||
#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
|
||||
#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
|
||||
#endif
|
||||
|
@ -118,6 +118,8 @@
|
||||
#define S3C2443_SCLKCON_UARTCLK (1<<8)
|
||||
#define S3C2443_SCLKCON_USBHOST (1<<1)
|
||||
|
||||
#define S3C2443_PWRCFG_SLEEP (1<<15)
|
||||
|
||||
#include <asm/div64.h>
|
||||
|
||||
static inline unsigned int
|
||||
|
@ -15,6 +15,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H
|
||||
|
||||
#define VMALLOC_END 0xE0000000UL
|
||||
#define VMALLOC_END 0xF6000000UL
|
||||
|
||||
#endif /* __ASM_ARCH_VMALLOC_H */
|
||||
|
@ -51,6 +51,7 @@
|
||||
#include <plat/clock.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/nand-core.h>
|
||||
|
||||
#ifndef CONFIG_CPU_S3C2412_ONLY
|
||||
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
|
||||
@ -92,7 +93,7 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
/* rename devices that are s3c2412/s3c2413 specific */
|
||||
s3c_device_sdi.name = "s3c2412-sdi";
|
||||
s3c_device_lcd.name = "s3c2412-lcd";
|
||||
s3c_device_nand.name = "s3c2412-nand";
|
||||
s3c_nand_setname("s3c2412-nand");
|
||||
|
||||
/* alter IRQ of SDI controller */
|
||||
|
||||
|
@ -25,6 +25,11 @@ config S3C2416_DMA
|
||||
help
|
||||
Internal config node for S3C2416 DMA support
|
||||
|
||||
config S3C2416_PM
|
||||
bool
|
||||
help
|
||||
Internal config node to apply S3C2416 power management
|
||||
|
||||
menu "S3C2416 Machines"
|
||||
|
||||
config MACH_SMDK2416
|
||||
@ -33,6 +38,7 @@ config MACH_SMDK2416
|
||||
select S3C_DEV_FB
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C2416_PM if PM
|
||||
help
|
||||
Say Y here if you are using an SMDK2416
|
||||
|
||||
|
@ -11,7 +11,7 @@ obj- :=
|
||||
|
||||
obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock.o
|
||||
obj-$(CONFIG_CPU_S3C2416) += irq.o
|
||||
|
||||
obj-$(CONFIG_S3C2416_PM) += pm.o
|
||||
#obj-$(CONFIG_S3C2416_DMA) += dma.o
|
||||
|
||||
# Machine support
|
||||
|
@ -243,6 +243,8 @@ static int __init s3c2416_irq_add(struct sys_device *sysdev)
|
||||
|
||||
static struct sysdev_driver s3c2416_irq_driver = {
|
||||
.add = s3c2416_irq_add,
|
||||
.suspend = s3c24xx_irq_suspend,
|
||||
.resume = s3c24xx_irq_resume,
|
||||
};
|
||||
|
||||
static int __init s3c2416_irq_init(void)
|
||||
|
84
arch/arm/mach-s3c2416/pm.c
Normal file
84
arch/arm/mach-s3c2416/pm.c
Normal file
@ -0,0 +1,84 @@
|
||||
/* linux/arch/arm/mach-s3c2416/pm.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S3C2416 - PM support (Based on Ben Dooks' S3C2412 PM support)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include <mach/regs-power.h>
|
||||
#include <mach/regs-s3c2443-clock.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
extern void s3c2412_sleep_enter(void);
|
||||
|
||||
static void s3c2416_cpu_suspend(void)
|
||||
{
|
||||
flush_cache_all();
|
||||
|
||||
/* enable wakeup sources regardless of battery state */
|
||||
__raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG);
|
||||
|
||||
/* set the mode as sleep, 2BED represents "Go to BED" */
|
||||
__raw_writel(0x2BED, S3C2443_PWRMODE);
|
||||
|
||||
s3c2412_sleep_enter();
|
||||
}
|
||||
|
||||
static void s3c2416_pm_prepare(void)
|
||||
{
|
||||
/*
|
||||
* write the magic value u-boot uses to check for resume into
|
||||
* the INFORM0 register, and ensure INFORM1 is set to the
|
||||
* correct address to resume from.
|
||||
*/
|
||||
__raw_writel(0x2BED, S3C2412_INFORM0);
|
||||
__raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
|
||||
}
|
||||
|
||||
static int s3c2416_pm_add(struct sys_device *sysdev)
|
||||
{
|
||||
pm_cpu_prep = s3c2416_pm_prepare;
|
||||
pm_cpu_sleep = s3c2416_cpu_suspend;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c2416_pm_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c2416_pm_resume(struct sys_device *dev)
|
||||
{
|
||||
/* unset the return-from-sleep amd inform flags */
|
||||
__raw_writel(0x0, S3C2443_PWRMODE);
|
||||
__raw_writel(0x0, S3C2412_INFORM0);
|
||||
__raw_writel(0x0, S3C2412_INFORM1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_driver s3c2416_pm_driver = {
|
||||
.add = s3c2416_pm_add,
|
||||
.suspend = s3c2416_pm_suspend,
|
||||
.resume = s3c2416_pm_resume,
|
||||
};
|
||||
|
||||
static __init int s3c2416_pm_init(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2416_pm_init);
|
@ -56,6 +56,7 @@
|
||||
|
||||
#include <plat/iic-core.h>
|
||||
#include <plat/fb-core.h>
|
||||
#include <plat/nand-core.h>
|
||||
|
||||
static struct map_desc s3c2416_iodesc[] __initdata = {
|
||||
IODESC_ENT(WATCHDOG),
|
||||
@ -100,7 +101,7 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
{
|
||||
s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
|
||||
|
||||
s3c_device_nand.name = "s3c2416-nand";
|
||||
s3c_nand_setname("s3c2412-nand");
|
||||
}
|
||||
|
||||
/* s3c2416_map_io
|
||||
|
@ -44,6 +44,7 @@
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/nand-core.h>
|
||||
|
||||
static struct map_desc s3c244x_iodesc[] __initdata = {
|
||||
IODESC_ENT(CLKPWR),
|
||||
@ -68,7 +69,7 @@ void __init s3c244x_map_io(void)
|
||||
|
||||
s3c_device_sdi.name = "s3c2440-sdi";
|
||||
s3c_device_i2c0.name = "s3c2440-i2c";
|
||||
s3c_device_nand.name = "s3c2440-nand";
|
||||
s3c_nand_setname("s3c2440-nand");
|
||||
s3c_device_ts.name = "s3c2440-ts";
|
||||
s3c_device_usbgadget.name = "s3c2440-usbgadget";
|
||||
}
|
||||
|
@ -36,6 +36,7 @@
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/fb-core.h>
|
||||
#include <plat/nand-core.h>
|
||||
|
||||
static struct map_desc s3c2443_iodesc[] __initdata = {
|
||||
IODESC_ENT(WATCHDOG),
|
||||
@ -62,7 +63,7 @@ int __init s3c2443_init(void)
|
||||
|
||||
s3c24xx_reset_hook = s3c2443_hard_reset;
|
||||
|
||||
s3c_device_nand.name = "s3c2412-nand";
|
||||
s3c_nand_setname("s3c2412-nand");
|
||||
s3c_fb_setname("s3c2443-fb");
|
||||
|
||||
/* change WDT IRQ number */
|
||||
|
@ -12,6 +12,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H
|
||||
|
||||
#define VMALLOC_END (0xe0000000UL)
|
||||
#define VMALLOC_END 0xF6000000UL
|
||||
|
||||
#endif /* __ASM_ARCH_VMALLOC_H */
|
||||
|
@ -98,12 +98,33 @@ config MACH_ANW6410
|
||||
help
|
||||
Machine support for the A&W6410
|
||||
|
||||
config MACH_MINI6410
|
||||
bool "MINI6410"
|
||||
select CPU_S3C6410
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C64XX_SETUP_SDHCI
|
||||
select S3C_DEV_USB_HOST
|
||||
select S3C_DEV_NAND
|
||||
select S3C_DEV_FB
|
||||
select S3C64XX_SETUP_FB_24BPP
|
||||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_TS
|
||||
help
|
||||
Machine support for the FriendlyARM MINI6410
|
||||
|
||||
config MACH_REAL6410
|
||||
bool "REAL6410"
|
||||
select CPU_S3C6410
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C64XX_SETUP_SDHCI
|
||||
select S3C_DEV_FB
|
||||
select S3C64XX_SETUP_FB_24BPP
|
||||
select S3C_DEV_NAND
|
||||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_TS
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Machine support for the CoreWind REAL6410
|
||||
|
||||
|
@ -53,6 +53,7 @@ obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
|
||||
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
|
||||
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
|
||||
obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
|
||||
obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
|
||||
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
|
||||
obj-$(CONFIG_MACH_HMT) += mach-hmt.o
|
||||
obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
|
||||
|
@ -22,27 +22,16 @@
|
||||
#include <plat/audio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#include <mach/gpio-bank-c.h>
|
||||
#include <mach/gpio-bank-d.h>
|
||||
#include <mach/gpio-bank-e.h>
|
||||
#include <mach/gpio-bank-h.h>
|
||||
|
||||
static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
unsigned int base;
|
||||
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
|
||||
base = S3C64XX_GPD(0);
|
||||
break;
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
|
||||
base = S3C64XX_GPE(0);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
|
||||
@ -50,18 +39,17 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -170,20 +158,14 @@ EXPORT_SYMBOL(s3c64xx_device_iisv4);
|
||||
|
||||
static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
unsigned int base;
|
||||
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_PCM0_SCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_PCM0_EXTCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_PCM0_FSYNC);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_PCM0_SIN);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_PCM0_SOUT);
|
||||
base = S3C64XX_GPD(0);
|
||||
break;
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_PCM1_SCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_PCM1_EXTCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_PCM1_FSYNC);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_PCM1_SIN);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
|
||||
base = S3C64XX_GPE(0);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
|
||||
@ -191,6 +173,7 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -264,24 +247,12 @@ EXPORT_SYMBOL(s3c64xx_device_pcm1);
|
||||
|
||||
static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_AC97_BITCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_AC97_nRESET);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_AC97_SYNC);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_AC97_SDI);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_AC97_SDO);
|
||||
|
||||
return 0;
|
||||
return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
|
||||
}
|
||||
|
||||
static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_AC97_BITCLK);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_AC97_nRESET);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_AC97_SYNC);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_AC97_SDI);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_AC97_SDO);
|
||||
|
||||
return 0;
|
||||
return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
|
||||
}
|
||||
|
||||
static struct resource s3c64xx_ac97_resource[] = {
|
||||
|
@ -195,11 +195,6 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
return IRQ_EINT(0) + pin;
|
||||
}
|
||||
|
||||
static struct s3c_gpio_chip gpio_2bit[] = {
|
||||
{
|
||||
.base = S3C64XX_GPF_BASE,
|
||||
@ -227,12 +222,13 @@ static struct s3c_gpio_chip gpio_2bit[] = {
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPN_BASE,
|
||||
.irq_base = IRQ_EINT(0),
|
||||
.config = &gpio_2bit_cfg_eint10,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPN(0),
|
||||
.ngpio = S3C64XX_GPIO_N_NR,
|
||||
.label = "GPN",
|
||||
.to_irq = s3c64xx_gpio2int_gpn,
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPO_BASE,
|
||||
|
@ -15,6 +15,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H
|
||||
|
||||
#define VMALLOC_END 0xE0000000UL
|
||||
#define VMALLOC_END 0xF6000000UL
|
||||
|
||||
#endif /* __ASM_ARCH_VMALLOC_H */
|
||||
|
357
arch/arm/mach-s3c64xx/mach-mini6410.c
Normal file
357
arch/arm/mach-s3c64xx/mach-mini6410.c
Normal file
@ -0,0 +1,357 @@
|
||||
/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
|
||||
*
|
||||
* Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/dm9000.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-fb.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-modem.h>
|
||||
#include <mach/regs-srom.h>
|
||||
#include <mach/s3c6410.h>
|
||||
|
||||
#include <plat/adc.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/ts.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
|
||||
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
|
||||
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
|
||||
|
||||
static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = UCON,
|
||||
.ulcon = ULCON,
|
||||
.ufcon = UFCON,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = UCON,
|
||||
.ulcon = ULCON,
|
||||
.ufcon = UFCON,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.flags = 0,
|
||||
.ucon = UCON,
|
||||
.ulcon = ULCON,
|
||||
.ufcon = UFCON,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.flags = 0,
|
||||
.ucon = UCON,
|
||||
.ulcon = ULCON,
|
||||
.ufcon = UFCON,
|
||||
},
|
||||
};
|
||||
|
||||
/* DM9000AEP 10/100 ethernet controller */
|
||||
|
||||
static struct resource mini6410_dm9k_resource[] = {
|
||||
[0] = {
|
||||
.start = S3C64XX_PA_XM0CSN1,
|
||||
.end = S3C64XX_PA_XM0CSN1 + 1,
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
[1] = {
|
||||
.start = S3C64XX_PA_XM0CSN1 + 4,
|
||||
.end = S3C64XX_PA_XM0CSN1 + 5,
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
[2] = {
|
||||
.start = S3C_EINT(7),
|
||||
.end = S3C_EINT(7),
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
|
||||
}
|
||||
};
|
||||
|
||||
static struct dm9000_plat_data mini6410_dm9k_pdata = {
|
||||
.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
|
||||
};
|
||||
|
||||
static struct platform_device mini6410_device_eth = {
|
||||
.name = "dm9000",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
|
||||
.resource = mini6410_dm9k_resource,
|
||||
.dev = {
|
||||
.platform_data = &mini6410_dm9k_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mtd_partition mini6410_nand_part[] = {
|
||||
[0] = {
|
||||
.name = "uboot",
|
||||
.size = SZ_1M,
|
||||
.offset = 0,
|
||||
},
|
||||
[1] = {
|
||||
.name = "kernel",
|
||||
.size = SZ_2M,
|
||||
.offset = SZ_1M,
|
||||
},
|
||||
[2] = {
|
||||
.name = "rootfs",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = SZ_1M + SZ_2M,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c2410_nand_set mini6410_nand_sets[] = {
|
||||
[0] = {
|
||||
.name = "nand",
|
||||
.nr_chips = 1,
|
||||
.nr_partitions = ARRAY_SIZE(mini6410_nand_part),
|
||||
.partitions = mini6410_nand_part,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c2410_platform_nand mini6410_nand_info = {
|
||||
.tacls = 25,
|
||||
.twrph0 = 55,
|
||||
.twrph1 = 40,
|
||||
.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
|
||||
.sets = mini6410_nand_sets,
|
||||
};
|
||||
|
||||
static struct s3c_fb_pd_win mini6410_fb_win[] = {
|
||||
{
|
||||
.win_mode = { /* 4.3" 480x272 */
|
||||
.left_margin = 3,
|
||||
.right_margin = 2,
|
||||
.upper_margin = 1,
|
||||
.lower_margin = 1,
|
||||
.hsync_len = 40,
|
||||
.vsync_len = 1,
|
||||
.xres = 480,
|
||||
.yres = 272,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
}, {
|
||||
.win_mode = { /* 7.0" 800x480 */
|
||||
.left_margin = 8,
|
||||
.right_margin = 13,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 3,
|
||||
.vsync_len = 1,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
|
||||
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
|
||||
.win[0] = &mini6410_fb_win[0],
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
};
|
||||
|
||||
static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
|
||||
unsigned int power)
|
||||
{
|
||||
if (power)
|
||||
gpio_direction_output(S3C64XX_GPE(0), 1);
|
||||
else
|
||||
gpio_direction_output(S3C64XX_GPE(0), 0);
|
||||
}
|
||||
|
||||
static struct plat_lcd_data mini6410_lcd_power_data = {
|
||||
.set_power = mini6410_lcd_power_set,
|
||||
};
|
||||
|
||||
static struct platform_device mini6410_lcd_powerdev = {
|
||||
.name = "platform-lcd",
|
||||
.dev.parent = &s3c_device_fb.dev,
|
||||
.dev.platform_data = &mini6410_lcd_power_data,
|
||||
};
|
||||
|
||||
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
|
||||
.delay = 10000,
|
||||
.presc = 49,
|
||||
.oversampling_shift = 2,
|
||||
};
|
||||
|
||||
static struct platform_device *mini6410_devices[] __initdata = {
|
||||
&mini6410_device_eth,
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc1,
|
||||
&s3c_device_ohci,
|
||||
&s3c_device_nand,
|
||||
&s3c_device_fb,
|
||||
&mini6410_lcd_powerdev,
|
||||
&s3c_device_adc,
|
||||
&s3c_device_ts,
|
||||
};
|
||||
|
||||
static void __init mini6410_map_io(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
s3c64xx_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
|
||||
|
||||
/* set the LCD type */
|
||||
tmp = __raw_readl(S3C64XX_SPCON);
|
||||
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
|
||||
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
|
||||
__raw_writel(tmp, S3C64XX_SPCON);
|
||||
|
||||
/* remove the LCD bypass */
|
||||
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
|
||||
tmp &= ~MIFPCON_LCD_BYPASS;
|
||||
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
|
||||
}
|
||||
|
||||
/*
|
||||
* mini6410_features string
|
||||
*
|
||||
* 0-9 LCD configuration
|
||||
*
|
||||
*/
|
||||
static char mini6410_features_str[12] __initdata = "0";
|
||||
|
||||
static int __init mini6410_features_setup(char *str)
|
||||
{
|
||||
if (str)
|
||||
strlcpy(mini6410_features_str, str,
|
||||
sizeof(mini6410_features_str));
|
||||
return 1;
|
||||
}
|
||||
|
||||
__setup("mini6410=", mini6410_features_setup);
|
||||
|
||||
#define FEATURE_SCREEN (1 << 0)
|
||||
|
||||
struct mini6410_features_t {
|
||||
int done;
|
||||
int lcd_index;
|
||||
};
|
||||
|
||||
static void mini6410_parse_features(
|
||||
struct mini6410_features_t *features,
|
||||
const char *features_str)
|
||||
{
|
||||
const char *fp = features_str;
|
||||
|
||||
features->done = 0;
|
||||
features->lcd_index = 0;
|
||||
|
||||
while (*fp) {
|
||||
char f = *fp++;
|
||||
|
||||
switch (f) {
|
||||
case '0'...'9': /* tft screen */
|
||||
if (features->done & FEATURE_SCREEN) {
|
||||
printk(KERN_INFO "MINI6410: '%c' ignored, "
|
||||
"screen type already set\n", f);
|
||||
} else {
|
||||
int li = f - '0';
|
||||
if (li >= ARRAY_SIZE(mini6410_fb_win))
|
||||
printk(KERN_INFO "MINI6410: '%c' out "
|
||||
"of range LCD mode\n", f);
|
||||
else {
|
||||
features->lcd_index = li;
|
||||
}
|
||||
}
|
||||
features->done |= FEATURE_SCREEN;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init mini6410_machine_init(void)
|
||||
{
|
||||
u32 cs1;
|
||||
struct mini6410_features_t features = { 0 };
|
||||
|
||||
printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
|
||||
mini6410_features_str);
|
||||
|
||||
/* Parse the feature string */
|
||||
mini6410_parse_features(&features, mini6410_features_str);
|
||||
|
||||
mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
|
||||
|
||||
printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
|
||||
mini6410_lcd_pdata.win[0]->win_mode.xres,
|
||||
mini6410_lcd_pdata.win[0]->win_mode.yres);
|
||||
|
||||
s3c_nand_set_platdata(&mini6410_nand_info);
|
||||
s3c_fb_set_platdata(&mini6410_lcd_pdata);
|
||||
s3c24xx_ts_set_platdata(&s3c_ts_platform);
|
||||
|
||||
/* configure nCS1 width to 16 bits */
|
||||
|
||||
cs1 = __raw_readl(S3C64XX_SROM_BW) &
|
||||
~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
|
||||
cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
|
||||
(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
|
||||
(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
|
||||
S3C64XX_SROM_BW__NCS1__SHIFT;
|
||||
__raw_writel(cs1, S3C64XX_SROM_BW);
|
||||
|
||||
/* set timing for nCS1 suitable for ethernet chip */
|
||||
|
||||
__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
|
||||
(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
|
||||
(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
|
||||
(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
|
||||
(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
|
||||
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
|
||||
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
|
||||
|
||||
gpio_request(S3C64XX_GPF(15), "LCD power");
|
||||
gpio_request(S3C64XX_GPE(0), "LCD power");
|
||||
|
||||
platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(MINI6410, "MINI6410")
|
||||
/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
|
||||
.boot_params = S3C64XX_PA_SDRAM + 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.map_io = mini6410_map_io,
|
||||
.init_machine = mini6410_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
MACHINE_END
|
@ -12,23 +12,39 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/dm9000.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/s3c6410.h>
|
||||
#include <mach/regs-fb.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-modem.h>
|
||||
#include <mach/regs-srom.h>
|
||||
#include <mach/s3c6410.h>
|
||||
|
||||
#include <plat/adc.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/ts.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
|
||||
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
|
||||
@ -99,22 +115,192 @@ static struct platform_device real6410_device_eth = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_fb_pd_win real6410_fb_win[] = {
|
||||
{
|
||||
.win_mode = { /* 4.3" 480x272 */
|
||||
.left_margin = 3,
|
||||
.right_margin = 2,
|
||||
.upper_margin = 1,
|
||||
.lower_margin = 1,
|
||||
.hsync_len = 40,
|
||||
.vsync_len = 1,
|
||||
.xres = 480,
|
||||
.yres = 272,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
}, {
|
||||
.win_mode = { /* 7.0" 800x480 */
|
||||
.left_margin = 8,
|
||||
.right_margin = 13,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 3,
|
||||
.vsync_len = 1,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
|
||||
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
|
||||
.win[0] = &real6410_fb_win[0],
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
};
|
||||
|
||||
static struct mtd_partition real6410_nand_part[] = {
|
||||
[0] = {
|
||||
.name = "uboot",
|
||||
.size = SZ_1M,
|
||||
.offset = 0,
|
||||
},
|
||||
[1] = {
|
||||
.name = "kernel",
|
||||
.size = SZ_2M,
|
||||
.offset = SZ_1M,
|
||||
},
|
||||
[2] = {
|
||||
.name = "rootfs",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = SZ_1M + SZ_2M,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c2410_nand_set real6410_nand_sets[] = {
|
||||
[0] = {
|
||||
.name = "nand",
|
||||
.nr_chips = 1,
|
||||
.nr_partitions = ARRAY_SIZE(real6410_nand_part),
|
||||
.partitions = real6410_nand_part,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c2410_platform_nand real6410_nand_info = {
|
||||
.tacls = 25,
|
||||
.twrph0 = 55,
|
||||
.twrph1 = 40,
|
||||
.nr_sets = ARRAY_SIZE(real6410_nand_sets),
|
||||
.sets = real6410_nand_sets,
|
||||
};
|
||||
|
||||
static struct platform_device *real6410_devices[] __initdata = {
|
||||
&real6410_device_eth,
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc1,
|
||||
&s3c_device_fb,
|
||||
&s3c_device_nand,
|
||||
&s3c_device_adc,
|
||||
&s3c_device_ts,
|
||||
&s3c_device_ohci,
|
||||
};
|
||||
|
||||
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
|
||||
.delay = 10000,
|
||||
.presc = 49,
|
||||
.oversampling_shift = 2,
|
||||
};
|
||||
|
||||
static void __init real6410_map_io(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
s3c64xx_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
|
||||
|
||||
/* set the LCD type */
|
||||
tmp = __raw_readl(S3C64XX_SPCON);
|
||||
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
|
||||
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
|
||||
__raw_writel(tmp, S3C64XX_SPCON);
|
||||
|
||||
/* remove the LCD bypass */
|
||||
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
|
||||
tmp &= ~MIFPCON_LCD_BYPASS;
|
||||
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
|
||||
}
|
||||
|
||||
/*
|
||||
* real6410_features string
|
||||
*
|
||||
* 0-9 LCD configuration
|
||||
*
|
||||
*/
|
||||
static char real6410_features_str[12] __initdata = "0";
|
||||
|
||||
static int __init real6410_features_setup(char *str)
|
||||
{
|
||||
if (str)
|
||||
strlcpy(real6410_features_str, str,
|
||||
sizeof(real6410_features_str));
|
||||
return 1;
|
||||
}
|
||||
|
||||
__setup("real6410=", real6410_features_setup);
|
||||
|
||||
#define FEATURE_SCREEN (1 << 0)
|
||||
|
||||
struct real6410_features_t {
|
||||
int done;
|
||||
int lcd_index;
|
||||
};
|
||||
|
||||
static void real6410_parse_features(
|
||||
struct real6410_features_t *features,
|
||||
const char *features_str)
|
||||
{
|
||||
const char *fp = features_str;
|
||||
|
||||
features->done = 0;
|
||||
features->lcd_index = 0;
|
||||
|
||||
while (*fp) {
|
||||
char f = *fp++;
|
||||
|
||||
switch (f) {
|
||||
case '0'...'9': /* tft screen */
|
||||
if (features->done & FEATURE_SCREEN) {
|
||||
printk(KERN_INFO "REAL6410: '%c' ignored, "
|
||||
"screen type already set\n", f);
|
||||
} else {
|
||||
int li = f - '0';
|
||||
if (li >= ARRAY_SIZE(real6410_fb_win))
|
||||
printk(KERN_INFO "REAL6410: '%c' out "
|
||||
"of range LCD mode\n", f);
|
||||
else {
|
||||
features->lcd_index = li;
|
||||
}
|
||||
}
|
||||
features->done |= FEATURE_SCREEN;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init real6410_machine_init(void)
|
||||
{
|
||||
u32 cs1;
|
||||
struct real6410_features_t features = { 0 };
|
||||
|
||||
printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
|
||||
real6410_features_str);
|
||||
|
||||
/* Parse the feature string */
|
||||
real6410_parse_features(&features, real6410_features_str);
|
||||
|
||||
real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
|
||||
|
||||
printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
|
||||
real6410_lcd_pdata.win[0]->win_mode.xres,
|
||||
real6410_lcd_pdata.win[0]->win_mode.yres);
|
||||
|
||||
s3c_fb_set_platdata(&real6410_lcd_pdata);
|
||||
s3c_nand_set_platdata(&real6410_nand_info);
|
||||
s3c24xx_ts_set_platdata(&s3c_ts_platform);
|
||||
|
||||
/* configure nCS1 width to 16 bits */
|
||||
|
||||
@ -136,6 +322,8 @@ static void __init real6410_machine_init(void)
|
||||
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
|
||||
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
|
||||
|
||||
gpio_request(S3C64XX_GPF(15), "LCD power");
|
||||
|
||||
platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
|
||||
}
|
||||
|
||||
|
@ -23,15 +23,6 @@
|
||||
|
||||
extern void s3c64xx_fb_gpio_setup_24bpp(void)
|
||||
{
|
||||
unsigned int gpio;
|
||||
|
||||
for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2));
|
||||
}
|
||||
|
@ -17,11 +17,11 @@
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/ata.h>
|
||||
|
||||
void s3c64xx_ide_setup_gpio(void)
|
||||
{
|
||||
u32 reg;
|
||||
u32 gpio = 0;
|
||||
|
||||
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
|
||||
|
||||
@ -32,15 +32,12 @@ void s3c64xx_ide_setup_gpio(void)
|
||||
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
|
||||
|
||||
/* Set XhiDATA[15:0] pins as CF Data[15:0] */
|
||||
for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
|
||||
|
||||
/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
|
||||
for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
|
||||
s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
|
||||
|
||||
/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
|
||||
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
|
||||
for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
|
||||
s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
|
||||
}
|
||||
|
@ -12,23 +12,13 @@
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/keypad.h>
|
||||
|
||||
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
|
||||
{
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
/* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
|
||||
end = S3C64XX_GPK(8 + rows);
|
||||
for (gpio = S3C64XX_GPK(8); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
|
||||
|
||||
/* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
|
||||
end = S3C64XX_GPL(0 + cols);
|
||||
for (gpio = S3C64XX_GPL(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
|
||||
}
|
||||
|
@ -24,16 +24,9 @@
|
||||
void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
end = S3C64XX_GPG(2 + width);
|
||||
|
||||
/* Set all the necessary GPG pins to special-function 0 */
|
||||
for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
/* Set all the necessary GPG pins to special-function 2 */
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
|
||||
@ -44,16 +37,9 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
end = S3C64XX_GPH(2 + width);
|
||||
|
||||
/* Set all the necessary GPG pins to special-function 0 */
|
||||
for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
/* Set all the necessary GPH pins to special-function 2 */
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2));
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
|
||||
@ -63,20 +49,9 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
||||
|
||||
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
/* Set all the necessary GPH pins to special-function 3 */
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3));
|
||||
|
||||
end = S3C64XX_GPH(6 + width);
|
||||
|
||||
/* Set all the necessary GPH pins to special-function 1 */
|
||||
for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
/* Set all the necessary GPC pins to special-function 1 */
|
||||
for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
/* Set all the necessary GPC pins to special-function 3 */
|
||||
s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3));
|
||||
}
|
||||
|
@ -11,7 +11,6 @@ if ARCH_S5P6442
|
||||
|
||||
config CPU_S5P6442
|
||||
bool
|
||||
select PLAT_S5P
|
||||
select S3C_PL330_DMA
|
||||
help
|
||||
Enable S5P6442 CPU support
|
||||
|
@ -192,6 +192,11 @@ static struct clk clk_pclkd1 = {
|
||||
.parent = &clk_hclkd1,
|
||||
};
|
||||
|
||||
int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
|
||||
}
|
||||
|
||||
int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
|
||||
@ -335,6 +340,16 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
|
||||
clk_pclkd1.rate = pclkd1;
|
||||
}
|
||||
|
||||
static struct clk init_clocks_disable[] = {
|
||||
{
|
||||
.name = "pdma",
|
||||
.id = -1,
|
||||
.parent = &clk_pclkd1,
|
||||
.enable = s5p6442_clk_ip0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks[] = {
|
||||
{
|
||||
.name = "systimer",
|
||||
@ -393,10 +408,23 @@ static struct clk *clks[] __initdata = {
|
||||
|
||||
void __init s5p6442_register_clocks(void)
|
||||
{
|
||||
struct clk *clkptr;
|
||||
int i, ret;
|
||||
|
||||
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
||||
|
||||
clkptr = init_clocks_disable;
|
||||
for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {
|
||||
ret = s3c24xx_register_clock(clkptr);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "Fail to register clock %s (%d)\n",
|
||||
clkptr->name, ret);
|
||||
} else
|
||||
(clkptr->enable)(clkptr, 0);
|
||||
}
|
||||
|
||||
s3c_pwmclk_init();
|
||||
}
|
||||
|
@ -21,22 +21,16 @@
|
||||
|
||||
static int s5p6442_cfg_i2s(struct platform_device *pdev)
|
||||
{
|
||||
unsigned int base;
|
||||
|
||||
/* configure GPIO for i2s port */
|
||||
switch (pdev->id) {
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2));
|
||||
base = S5P6442_GPC1(0);
|
||||
break;
|
||||
|
||||
case -1:
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2));
|
||||
base = S5P6442_GPC0(0);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -44,6 +38,7 @@ static int s5p6442_cfg_i2s(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -111,21 +106,15 @@ struct platform_device s5p6442_device_iis1 = {
|
||||
|
||||
static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
unsigned int base;
|
||||
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3));
|
||||
base = S5P6442_GPC0(0);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3));
|
||||
base = S5P6442_GPC1(0);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -133,6 +122,7 @@ static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -38,11 +38,9 @@ static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -82,7 +82,7 @@ static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
|
||||
|
||||
static struct platform_device s5p6442_device_pdma = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 1,
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
|
||||
.resource = s5p6442_pdma_resource,
|
||||
.dev = {
|
||||
|
@ -46,6 +46,7 @@
|
||||
#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
|
||||
#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
|
||||
|
||||
#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
|
||||
#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
|
||||
|
||||
/* CLK_OUT */
|
||||
|
@ -12,6 +12,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H
|
||||
|
||||
#define VMALLOC_END 0xE0000000UL
|
||||
#define VMALLOC_END 0xF6000000UL
|
||||
|
||||
#endif /* __ASM_ARCH_VMALLOC_H */
|
||||
|
@ -9,14 +9,12 @@ if ARCH_S5P64X0
|
||||
|
||||
config CPU_S5P6440
|
||||
bool
|
||||
select PLAT_S5P
|
||||
select S3C_PL330_DMA
|
||||
help
|
||||
Enable S5P6440 CPU support
|
||||
|
||||
config CPU_S5P6450
|
||||
bool
|
||||
select PLAT_S5P
|
||||
select S3C_PL330_DMA
|
||||
help
|
||||
Enable S5P6450 CPU support
|
||||
|
@ -79,13 +79,16 @@ static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
|
||||
__raw_writel(epll_con, S5P64X0_EPLL_CON);
|
||||
__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
|
||||
|
||||
printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
|
||||
clk->rate, rate);
|
||||
|
||||
clk->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops s5p6440_epll_ops = {
|
||||
.get_rate = s5p64x0_epll_get_rate,
|
||||
.get_rate = s5p_epll_get_rate,
|
||||
.set_rate = s5p6440_epll_set_rate,
|
||||
};
|
||||
|
||||
@ -149,6 +152,12 @@ static struct clk init_clocks_disable[] = {
|
||||
.parent = &clk_hclk.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
}, {
|
||||
.name = "pdma",
|
||||
.id = -1,
|
||||
.parent = &clk_hclk_low.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.id = 0,
|
||||
@ -330,12 +339,6 @@ static struct clk init_clocks[] = {
|
||||
.parent = &clk_hclk.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 21),
|
||||
}, {
|
||||
.name = "dma",
|
||||
.id = -1,
|
||||
.parent = &clk_hclk_low.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 0,
|
||||
@ -548,7 +551,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
|
||||
|
||||
/* Set S5P6440 functions for clk_fout_epll */
|
||||
|
||||
clk_fout_epll.enable = s5p64x0_epll_enable;
|
||||
clk_fout_epll.enable = s5p_epll_enable;
|
||||
clk_fout_epll.ops = &s5p6440_epll_ops;
|
||||
|
||||
clk_48m.enable = s5p64x0_clk48m_ctrl;
|
||||
|
@ -80,13 +80,16 @@ static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
|
||||
__raw_writel(epll_con, S5P64X0_EPLL_CON);
|
||||
__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
|
||||
|
||||
printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
|
||||
clk->rate, rate);
|
||||
|
||||
clk->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops s5p6450_epll_ops = {
|
||||
.get_rate = s5p64x0_epll_get_rate,
|
||||
.get_rate = s5p_epll_get_rate,
|
||||
.set_rate = s5p6450_epll_set_rate,
|
||||
};
|
||||
|
||||
@ -185,6 +188,12 @@ static struct clk init_clocks_disable[] = {
|
||||
.parent = &clk_hclk_low.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "pdma",
|
||||
.id = -1,
|
||||
.parent = &clk_hclk_low.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.id = 0,
|
||||
@ -282,12 +291,6 @@ static struct clk init_clocks[] = {
|
||||
.parent = &clk_hclk.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 21),
|
||||
}, {
|
||||
.name = "dma",
|
||||
.id = -1,
|
||||
.parent = &clk_hclk_low.clk,
|
||||
.enable = s5p64x0_hclk0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 0,
|
||||
@ -581,7 +584,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
|
||||
|
||||
/* Set S5P6450 functions for clk_fout_epll */
|
||||
|
||||
clk_fout_epll.enable = s5p64x0_epll_enable;
|
||||
clk_fout_epll.enable = s5p_epll_enable;
|
||||
clk_fout_epll.ops = &s5p6450_epll_ops;
|
||||
|
||||
clk_48m.enable = s5p64x0_clk48m_ctrl;
|
||||
|
@ -73,24 +73,6 @@ static const u32 clock_table[][3] = {
|
||||
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
|
||||
};
|
||||
|
||||
int s5p64x0_epll_enable(struct clk *clk, int enable)
|
||||
{
|
||||
unsigned int ctrlbit = clk->ctrlbit;
|
||||
unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
|
||||
|
||||
if (enable)
|
||||
__raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
|
||||
else
|
||||
__raw_writel(epll_con, S5P64X0_EPLL_CON);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long s5p64x0_epll_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk->rate;
|
||||
}
|
||||
|
||||
unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
|
||||
{
|
||||
unsigned long rate = clk_get_rate(clk->parent);
|
||||
|
@ -24,13 +24,8 @@ static int s5p6440_cfg_i2s(struct platform_device *pdev)
|
||||
/* configure GPIO for i2s port */
|
||||
switch (pdev->id) {
|
||||
case -1:
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5));
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -47,13 +42,9 @@ static int s5p6450_cfg_i2s(struct platform_device *pdev)
|
||||
switch (pdev->id) {
|
||||
case -1:
|
||||
s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -116,11 +107,8 @@ static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -39,23 +39,15 @@ static char *s5p64x0_spi_src_clks[] = {
|
||||
*/
|
||||
static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
unsigned int base;
|
||||
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
|
||||
base = S5P6440_GPC(0);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
|
||||
base = S5P6440_GPC(4);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -63,28 +55,23 @@ static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s3c_gpio_cfgall_range(base, 3,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
unsigned int base;
|
||||
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
|
||||
base = S5P6450_GPC(0);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
|
||||
base = S5P6450_GPC(4);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -92,6 +79,9 @@ static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s3c_gpio_cfgall_range(base, 3,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -122,7 +122,7 @@ static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
|
||||
|
||||
static struct platform_device s5p64x0_device_pdma = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 0,
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p64x0_pdma_resource),
|
||||
.resource = s5p64x0_pdma_resource,
|
||||
.dev = {
|
||||
|
@ -60,4 +60,6 @@
|
||||
#define ARM_DIV_RATIO_SHIFT 0
|
||||
#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
|
||||
|
||||
#define S5P_EPLL_CON S5P64X0_EPLL_CON
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_CLOCK_H */
|
||||
|
@ -15,6 +15,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H
|
||||
|
||||
#define VMALLOC_END 0xE0000000UL
|
||||
#define VMALLOC_END 0xF6000000UL
|
||||
|
||||
#endif /* __ASM_ARCH_VMALLOC_H */
|
||||
|
@ -25,18 +25,14 @@ struct platform_device; /* don't need the contents */
|
||||
|
||||
void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5P6440_GPB(5), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5P6450_GPB(5), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
|
||||
|
@ -25,18 +25,14 @@ struct platform_device; /* don't need the contents */
|
||||
|
||||
void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
|
||||
s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
|
||||
s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5P6440_GPR(9), 2,
|
||||
S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
|
||||
s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
|
||||
s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5P6450_GPR(9), 2,
|
||||
S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
|
||||
|
@ -9,7 +9,6 @@ if ARCH_S5PC100
|
||||
|
||||
config CPU_S5PC100
|
||||
bool
|
||||
select PLAT_S5P
|
||||
select S5P_EXT_INT
|
||||
select S3C_PL330_DMA
|
||||
help
|
||||
|
@ -11,7 +11,7 @@ obj- :=
|
||||
|
||||
# Core support for S5PC100 system
|
||||
|
||||
obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o
|
||||
obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o
|
||||
obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
|
||||
obj-$(CONFIG_CPU_S5PC100) += dma.o
|
||||
|
||||
|
@ -273,24 +273,6 @@ static struct clksrc_clk clk_div_hdmi = {
|
||||
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
|
||||
};
|
||||
|
||||
static int s5pc100_epll_enable(struct clk *clk, int enable)
|
||||
{
|
||||
unsigned int ctrlbit = clk->ctrlbit;
|
||||
unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
|
||||
|
||||
if (enable)
|
||||
__raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
|
||||
else
|
||||
__raw_writel(epll_con, S5P_EPLL_CON);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long s5pc100_epll_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk->rate;
|
||||
}
|
||||
|
||||
static u32 epll_div[][4] = {
|
||||
{ 32750000, 131, 3, 4 },
|
||||
{ 32768000, 131, 3, 4 },
|
||||
@ -341,13 +323,16 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
|
||||
|
||||
__raw_writel(epll_con, S5P_EPLL_CON);
|
||||
|
||||
printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
|
||||
clk->rate, rate);
|
||||
|
||||
clk->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops s5pc100_epll_ops = {
|
||||
.get_rate = s5pc100_epll_get_rate,
|
||||
.get_rate = s5p_epll_get_rate,
|
||||
.set_rate = s5pc100_epll_set_rate,
|
||||
};
|
||||
|
||||
@ -691,55 +676,55 @@ static struct clk init_clocks_disable[] = {
|
||||
}, {
|
||||
.name = "iis",
|
||||
.id = 0,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "iis",
|
||||
.id = 1,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "iis",
|
||||
.id = 2,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 2),
|
||||
}, {
|
||||
.name = "ac97",
|
||||
.id = -1,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "pcm",
|
||||
.id = 0,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "pcm",
|
||||
.id = 1,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "spdif",
|
||||
.id = -1,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "adc",
|
||||
.id = -1,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "keypad",
|
||||
.id = -1,
|
||||
.parent = &clk_div_d1_bus.clk,
|
||||
.parent = &clk_div_pclkd1.clk,
|
||||
.enable = s5pc100_d1_5_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
}, {
|
||||
@ -848,6 +833,18 @@ struct clksrc_sources clk_src_group3 = {
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group3_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_audio0 = {
|
||||
.clk = {
|
||||
.name = "sclk_audio",
|
||||
.id = 0,
|
||||
.ctrlbit = (1 << 8),
|
||||
.enable = s5pc100_sclk1_ctrl,
|
||||
},
|
||||
.sources = &clk_src_group3,
|
||||
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
|
||||
};
|
||||
|
||||
static struct clk *clk_src_group4_list[] = {
|
||||
[0] = &clk_mout_epll.clk,
|
||||
[1] = &clk_div_mpll.clk,
|
||||
@ -862,6 +859,18 @@ struct clksrc_sources clk_src_group4 = {
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group4_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_audio1 = {
|
||||
.clk = {
|
||||
.name = "sclk_audio",
|
||||
.id = 1,
|
||||
.ctrlbit = (1 << 9),
|
||||
.enable = s5pc100_sclk1_ctrl,
|
||||
},
|
||||
.sources = &clk_src_group4,
|
||||
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
|
||||
};
|
||||
|
||||
static struct clk *clk_src_group5_list[] = {
|
||||
[0] = &clk_mout_epll.clk,
|
||||
[1] = &clk_div_mpll.clk,
|
||||
@ -875,6 +884,18 @@ struct clksrc_sources clk_src_group5 = {
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group5_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_audio2 = {
|
||||
.clk = {
|
||||
.name = "sclk_audio",
|
||||
.id = 2,
|
||||
.ctrlbit = (1 << 10),
|
||||
.enable = s5pc100_sclk1_ctrl,
|
||||
},
|
||||
.sources = &clk_src_group5,
|
||||
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
|
||||
};
|
||||
|
||||
static struct clk *clk_src_group6_list[] = {
|
||||
[0] = &s5p_clk_27m,
|
||||
[1] = &clk_vclk54m,
|
||||
@ -944,6 +965,64 @@ struct clksrc_sources clk_src_pwi = {
|
||||
.nr_sources = ARRAY_SIZE(clk_src_pwi_list),
|
||||
};
|
||||
|
||||
static struct clk *clk_sclk_spdif_list[] = {
|
||||
[0] = &clk_sclk_audio0.clk,
|
||||
[1] = &clk_sclk_audio1.clk,
|
||||
[2] = &clk_sclk_audio2.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_sclk_spdif = {
|
||||
.sources = clk_sclk_spdif_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
|
||||
};
|
||||
|
||||
static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct clk *pclk;
|
||||
int ret;
|
||||
|
||||
pclk = clk_get_parent(clk);
|
||||
if (IS_ERR(pclk))
|
||||
return -EINVAL;
|
||||
|
||||
ret = pclk->ops->set_rate(pclk, rate);
|
||||
clk_put(pclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long s5pc100_spdif_get_rate(struct clk *clk)
|
||||
{
|
||||
struct clk *pclk;
|
||||
int rate;
|
||||
|
||||
pclk = clk_get_parent(clk);
|
||||
if (IS_ERR(pclk))
|
||||
return -EINVAL;
|
||||
|
||||
rate = pclk->ops->get_rate(clk);
|
||||
clk_put(pclk);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static struct clk_ops s5pc100_sclk_spdif_ops = {
|
||||
.set_rate = s5pc100_spdif_set_rate,
|
||||
.get_rate = s5pc100_spdif_get_rate,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_spdif = {
|
||||
.clk = {
|
||||
.name = "sclk_spdif",
|
||||
.id = -1,
|
||||
.ctrlbit = (1 << 11),
|
||||
.enable = s5pc100_sclk1_ctrl,
|
||||
.ops = &s5pc100_sclk_spdif_ops,
|
||||
},
|
||||
.sources = &clk_src_sclk_spdif,
|
||||
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
@ -999,39 +1078,6 @@ static struct clksrc_clk clksrcs[] = {
|
||||
},
|
||||
.sources = &clk_src_group6,
|
||||
.reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_audio",
|
||||
.id = 0,
|
||||
.ctrlbit = (1 << 8),
|
||||
.enable = s5pc100_sclk1_ctrl,
|
||||
|
||||
},
|
||||
.sources = &clk_src_group3,
|
||||
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_audio",
|
||||
.id = 1,
|
||||
.ctrlbit = (1 << 9),
|
||||
.enable = s5pc100_sclk1_ctrl,
|
||||
|
||||
},
|
||||
.sources = &clk_src_group4,
|
||||
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_audio",
|
||||
.id = 2,
|
||||
.ctrlbit = (1 << 10),
|
||||
.enable = s5pc100_sclk1_ctrl,
|
||||
|
||||
},
|
||||
.sources = &clk_src_group5,
|
||||
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_lcd",
|
||||
@ -1179,6 +1225,10 @@ static struct clksrc_clk *sysclks[] = {
|
||||
&clk_div_pclkd1,
|
||||
&clk_div_cam,
|
||||
&clk_div_hdmi,
|
||||
&clk_sclk_audio0,
|
||||
&clk_sclk_audio1,
|
||||
&clk_sclk_audio2,
|
||||
&clk_sclk_spdif,
|
||||
};
|
||||
|
||||
void __init_or_cpufreq s5pc100_setup_clocks(void)
|
||||
@ -1196,7 +1246,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
|
||||
unsigned int ptr;
|
||||
|
||||
/* Set S5PC100 functions for clk_fout_epll */
|
||||
clk_fout_epll.enable = s5pc100_epll_enable;
|
||||
clk_fout_epll.enable = s5p_epll_enable;
|
||||
clk_fout_epll.ops = &s5pc100_epll_ops;
|
||||
|
||||
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
|
||||
|
@ -24,19 +24,11 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
|
||||
/* configure GPIO for i2s port */
|
||||
switch (pdev->id) {
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
|
||||
case 2:
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
|
||||
break;
|
||||
|
||||
case -1: /* Dedicated pins */
|
||||
@ -144,19 +136,11 @@ static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5));
|
||||
s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
|
||||
break;
|
||||
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -231,13 +215,7 @@ struct platform_device s5pc100_device_pcm1 = {
|
||||
|
||||
static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4));
|
||||
|
||||
return 0;
|
||||
return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
|
||||
}
|
||||
|
||||
static struct resource s5pc100_ac97_resource[] = {
|
||||
@ -285,3 +263,57 @@ struct platform_device s5pc100_device_ac97 = {
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
/* S/PDIF Controller platform_device */
|
||||
static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct resource s5pc100_spdif_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PC100_PA_SPDIF,
|
||||
.end = S5PC100_PA_SPDIF + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_SPDIF,
|
||||
.end = DMACH_SPDIF,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_audio_pdata s5p_spdif_pdata = {
|
||||
.cfg_gpio = s5pc100_spdif_cfg_gpd,
|
||||
};
|
||||
|
||||
static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device s5pc100_device_spdif = {
|
||||
.name = "samsung-spdif",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5pc100_spdif_resource),
|
||||
.resource = s5pc100_spdif_resource,
|
||||
.dev = {
|
||||
.platform_data = &s5p_spdif_pdata,
|
||||
.dma_mask = &s5pc100_spdif_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
void __init s5pc100_spdif_setup_gpio(int gpio)
|
||||
{
|
||||
if (gpio == S5PC100_SPDIF_GPD)
|
||||
s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd;
|
||||
else
|
||||
s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3;
|
||||
}
|
||||
|
@ -38,30 +38,20 @@ static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -81,7 +81,7 @@ static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
|
||||
|
||||
static struct platform_device s5pc100_device_pdma0 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 1,
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5pc100_pdma0_resource),
|
||||
.resource = s5pc100_pdma0_resource,
|
||||
.dev = {
|
||||
@ -143,7 +143,7 @@ static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
|
||||
|
||||
static struct platform_device s5pc100_device_pdma1 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 2,
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(s5pc100_pdma1_resource),
|
||||
.resource = s5pc100_pdma1_resource,
|
||||
.dev = {
|
||||
|
@ -1,5 +1,7 @@
|
||||
/*
|
||||
* arch/arm/plat-s5pc100/gpiolib.c
|
||||
/* linux/arch/arm/mach-s5pc100/gpiolib.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright 2009 Samsung Electronics Co
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
@ -61,30 +63,6 @@
|
||||
* L3 8 4Bit None
|
||||
*/
|
||||
|
||||
static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
return S3C_IRQ_GPIO(chip->base + offset);
|
||||
}
|
||||
|
||||
static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
int base;
|
||||
|
||||
base = chip->base - S5PC100_GPH0(0);
|
||||
if (base == 0)
|
||||
return IRQ_EINT(offset);
|
||||
base = chip->base - S5PC100_GPH1(0);
|
||||
if (base == 0)
|
||||
return IRQ_EINT(8 + offset);
|
||||
base = chip->base - S5PC100_GPH2(0);
|
||||
if (base == 0)
|
||||
return IRQ_EINT(16 + offset);
|
||||
base = chip->base - S5PC100_GPH3(0);
|
||||
if (base == 0)
|
||||
return IRQ_EINT(24 + offset);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct s3c_gpio_cfg gpio_cfg = {
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
@ -104,209 +82,150 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO bank's base address given the index of the bank in the
|
||||
* list of all gpio banks.
|
||||
*/
|
||||
#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
|
||||
|
||||
/*
|
||||
* Following are the gpio banks in S5PC100.
|
||||
*
|
||||
* The 'config' member when left to NULL, is initialized to the default
|
||||
* structure gpio_cfg in the init function below.
|
||||
*
|
||||
* The 'base' member is also initialized in the init function below.
|
||||
* Note: The initialization of 'base' member of s3c_gpio_chip structure
|
||||
* uses the above macro and depends on the banks being listed in order here.
|
||||
*/
|
||||
static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
{
|
||||
.base = S5PC100_GPA0_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPA0(0),
|
||||
.ngpio = S5PC100_GPIO_A0_NR,
|
||||
.label = "GPA0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPA1_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPA1(0),
|
||||
.ngpio = S5PC100_GPIO_A1_NR,
|
||||
.label = "GPA1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPB_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPB(0),
|
||||
.ngpio = S5PC100_GPIO_B_NR,
|
||||
.label = "GPB",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPC_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPC(0),
|
||||
.ngpio = S5PC100_GPIO_C_NR,
|
||||
.label = "GPC",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPD_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPD(0),
|
||||
.ngpio = S5PC100_GPIO_D_NR,
|
||||
.label = "GPD",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPE0_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPE0(0),
|
||||
.ngpio = S5PC100_GPIO_E0_NR,
|
||||
.label = "GPE0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPE1_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPE1(0),
|
||||
.ngpio = S5PC100_GPIO_E1_NR,
|
||||
.label = "GPE1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPF0_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPF0(0),
|
||||
.ngpio = S5PC100_GPIO_F0_NR,
|
||||
.label = "GPF0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPF1_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPF1(0),
|
||||
.ngpio = S5PC100_GPIO_F1_NR,
|
||||
.label = "GPF1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPF2_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPF2(0),
|
||||
.ngpio = S5PC100_GPIO_F2_NR,
|
||||
.label = "GPF2",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPF3_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPF3(0),
|
||||
.ngpio = S5PC100_GPIO_F3_NR,
|
||||
.label = "GPF3",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPG0_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPG0(0),
|
||||
.ngpio = S5PC100_GPIO_G0_NR,
|
||||
.label = "GPG0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPG1_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPG1(0),
|
||||
.ngpio = S5PC100_GPIO_G1_NR,
|
||||
.label = "GPG1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPG2_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPG2(0),
|
||||
.ngpio = S5PC100_GPIO_G2_NR,
|
||||
.label = "GPG2",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPG3_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPG3(0),
|
||||
.ngpio = S5PC100_GPIO_G3_NR,
|
||||
.label = "GPG3",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPH0_BASE,
|
||||
.config = &gpio_cfg_eint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPH0(0),
|
||||
.ngpio = S5PC100_GPIO_H0_NR,
|
||||
.label = "GPH0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPH1_BASE,
|
||||
.config = &gpio_cfg_eint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPH1(0),
|
||||
.ngpio = S5PC100_GPIO_H1_NR,
|
||||
.label = "GPH1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPH2_BASE,
|
||||
.config = &gpio_cfg_eint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPH2(0),
|
||||
.ngpio = S5PC100_GPIO_H2_NR,
|
||||
.label = "GPH2",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPH3_BASE,
|
||||
.config = &gpio_cfg_eint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPH3(0),
|
||||
.ngpio = S5PC100_GPIO_H3_NR,
|
||||
.label = "GPH3",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPI_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPI(0),
|
||||
.ngpio = S5PC100_GPIO_I_NR,
|
||||
.label = "GPI",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPJ0_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPJ0(0),
|
||||
.ngpio = S5PC100_GPIO_J0_NR,
|
||||
.label = "GPJ0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPJ1_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPJ1(0),
|
||||
.ngpio = S5PC100_GPIO_J1_NR,
|
||||
.label = "GPJ1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPJ2_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPJ2(0),
|
||||
.ngpio = S5PC100_GPIO_J2_NR,
|
||||
.label = "GPJ2",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPJ3_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPJ3(0),
|
||||
.ngpio = S5PC100_GPIO_J3_NR,
|
||||
.label = "GPJ3",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPJ4_BASE,
|
||||
.config = &gpio_cfg,
|
||||
.chip = {
|
||||
.base = S5PC100_GPJ4(0),
|
||||
.ngpio = S5PC100_GPIO_J4_NR,
|
||||
.label = "GPJ4",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPK0_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPK0(0),
|
||||
@ -314,7 +233,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPK0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPK1_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPK1(0),
|
||||
@ -322,7 +240,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPK1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPK2_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPK2(0),
|
||||
@ -330,7 +247,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPK2",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPK3_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPK3(0),
|
||||
@ -338,7 +254,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPK3",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPL0_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPL0(0),
|
||||
@ -346,7 +261,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPL0",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPL1_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPL1(0),
|
||||
@ -354,7 +268,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPL1",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPL2_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPL2(0),
|
||||
@ -362,7 +275,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPL2",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPL3_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPL3(0),
|
||||
@ -370,56 +282,72 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
|
||||
.label = "GPL3",
|
||||
},
|
||||
}, {
|
||||
.base = S5PC100_GPL4_BASE,
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PC100_GPL4(0),
|
||||
.ngpio = S5PC100_GPIO_L4_NR,
|
||||
.label = "GPL4",
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC00),
|
||||
.config = &gpio_cfg_eint,
|
||||
.irq_base = IRQ_EINT(0),
|
||||
.chip = {
|
||||
.base = S5PC100_GPH0(0),
|
||||
.ngpio = S5PC100_GPIO_H0_NR,
|
||||
.label = "GPH0",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC20),
|
||||
.config = &gpio_cfg_eint,
|
||||
.irq_base = IRQ_EINT(8),
|
||||
.chip = {
|
||||
.base = S5PC100_GPH1(0),
|
||||
.ngpio = S5PC100_GPIO_H1_NR,
|
||||
.label = "GPH1",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC40),
|
||||
.config = &gpio_cfg_eint,
|
||||
.irq_base = IRQ_EINT(16),
|
||||
.chip = {
|
||||
.base = S5PC100_GPH2(0),
|
||||
.ngpio = S5PC100_GPIO_H2_NR,
|
||||
.label = "GPH2",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC60),
|
||||
.config = &gpio_cfg_eint,
|
||||
.irq_base = IRQ_EINT(24),
|
||||
.chip = {
|
||||
.base = S5PC100_GPH3(0),
|
||||
.ngpio = S5PC100_GPIO_H3_NR,
|
||||
.label = "GPH3",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* FIXME move from irq-gpio.c */
|
||||
extern struct irq_chip s5pc100_gpioint;
|
||||
extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
|
||||
|
||||
static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
/* Interrupt */
|
||||
if (chip->config == &gpio_cfg) {
|
||||
int i, irq;
|
||||
|
||||
chip->chip.to_irq = s5pc100_gpiolib_to_irq;
|
||||
|
||||
for (i = 0; i < chip->chip.ngpio; i++) {
|
||||
irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
|
||||
set_irq_chip(irq, &s5pc100_gpioint);
|
||||
set_irq_data(irq, &chip->chip);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
} else if (chip->config == &gpio_cfg_eint) {
|
||||
chip->chip.to_irq = s5pc100_gpiolib_to_eint;
|
||||
}
|
||||
}
|
||||
|
||||
static __init int s5pc100_gpiolib_init(void)
|
||||
{
|
||||
struct s3c_gpio_chip *chip;
|
||||
int nr_chips;
|
||||
struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
|
||||
int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
|
||||
int gpioint_group = 0;
|
||||
int i;
|
||||
|
||||
chip = s5pc100_gpio_chips;
|
||||
nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL) {
|
||||
chip->config = &gpio_cfg;
|
||||
chip->group = gpioint_group++;
|
||||
}
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5PC100_BANK_BASE(i);
|
||||
}
|
||||
|
||||
for (; nr_chips > 0; nr_chips--, chip++)
|
||||
s5pc100_gpiolib_link(chip);
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
|
||||
ARRAY_SIZE(s5pc100_gpio_chips));
|
||||
|
||||
/* Interrupt */
|
||||
set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
|
||||
samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -146,13 +146,6 @@ enum s5p_gpio_number {
|
||||
/* define the number of gpios we need to the one after the MP04() range */
|
||||
#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
|
||||
|
||||
#define EINT_MODE S3C_GPIO_SFN(0x2)
|
||||
|
||||
#define EINT_GPIO_0(x) S5PC100_GPH0(x)
|
||||
#define EINT_GPIO_1(x) S5PC100_GPH1(x)
|
||||
#define EINT_GPIO_2(x) S5PC100_GPH2(x)
|
||||
#define EINT_GPIO_3(x) S5PC100_GPH3(x)
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_H */
|
||||
|
@ -48,8 +48,8 @@
|
||||
#define IRQ_SPI1 S5P_IRQ_VIC1(16)
|
||||
#define IRQ_SPI2 S5P_IRQ_VIC1(17)
|
||||
#define IRQ_IRDA S5P_IRQ_VIC1(18)
|
||||
#define IRQ_CAN0 S5P_IRQ_VIC1(19)
|
||||
#define IRQ_CAN1 S5P_IRQ_VIC1(20)
|
||||
#define IRQ_IIC2 S5P_IRQ_VIC1(19)
|
||||
#define IRQ_IIC3 S5P_IRQ_VIC1(20)
|
||||
#define IRQ_HSIRX S5P_IRQ_VIC1(21)
|
||||
#define IRQ_HSITX S5P_IRQ_VIC1(22)
|
||||
#define IRQ_UHOST S5P_IRQ_VIC1(23)
|
||||
@ -100,11 +100,12 @@
|
||||
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
|
||||
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
|
||||
|
||||
#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
|
||||
#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
|
||||
/* GPIO interrupt */
|
||||
#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
|
||||
#define S5P_GPIOINT_GROUP_MAXNR 21
|
||||
|
||||
/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
|
||||
#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
|
||||
/* Set the default NR_IRQS */
|
||||
#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
|
||||
|
||||
/* Compatibility */
|
||||
#define IRQ_LCD_FIFO IRQ_LCD0
|
||||
|
@ -110,6 +110,8 @@
|
||||
#define S5PC100_PA_PCM0 0xF2400000
|
||||
#define S5PC100_PA_PCM1 0xF2500000
|
||||
|
||||
#define S5PC100_PA_SPDIF 0xF2600000
|
||||
|
||||
#define S5PC100_PA_TSADC (0xF3000000)
|
||||
|
||||
/* KEYPAD */
|
||||
|
@ -11,43 +11,6 @@
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* S5PC100 */
|
||||
#define S5PC100_GPIO_BASE S5P_VA_GPIO
|
||||
#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
|
||||
#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
|
||||
#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
|
||||
#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
|
||||
#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
|
||||
#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
|
||||
#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
|
||||
#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
|
||||
#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
|
||||
#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
|
||||
#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
|
||||
#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
|
||||
#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
|
||||
#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
|
||||
#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
|
||||
#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
|
||||
#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
|
||||
#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
|
||||
#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
|
||||
#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
|
||||
#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
|
||||
#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
|
||||
#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
|
||||
#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
|
||||
#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
|
||||
#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
|
||||
#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
|
||||
#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
|
||||
#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
|
||||
#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
|
||||
#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
|
||||
#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
|
||||
#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
|
||||
#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
|
||||
|
||||
#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
|
||||
#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
|
||||
|
||||
@ -64,12 +27,12 @@
|
||||
|
||||
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
|
||||
|
||||
/* values for S5P_EXTINT0 */
|
||||
#define S5P_EXTINT_LOWLEV (0x00)
|
||||
#define S5P_EXTINT_HILEV (0x01)
|
||||
#define S5P_EXTINT_FALLEDGE (0x02)
|
||||
#define S5P_EXTINT_RISEEDGE (0x03)
|
||||
#define S5P_EXTINT_BOTHEDGE (0x04)
|
||||
#define EINT_MODE S3C_GPIO_SFN(0x2)
|
||||
|
||||
#define EINT_GPIO_0(x) S5PC100_GPH0(x)
|
||||
#define EINT_GPIO_1(x) S5PC100_GPH1(x)
|
||||
#define EINT_GPIO_2(x) S5PC100_GPH2(x)
|
||||
#define EINT_GPIO_3(x) S5PC100_GPH3(x)
|
||||
|
||||
#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
|
||||
|
||||
|
@ -12,6 +12,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H
|
||||
|
||||
#define VMALLOC_END (0xe0000000UL)
|
||||
#define VMALLOC_END 0xF6000000UL
|
||||
|
||||
#endif /* __ASM_ARCH_VMALLOC_H */
|
||||
|
@ -1,266 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-s5pc100/irq-gpio.c
|
||||
*
|
||||
* Copyright (C) 2009 Samsung Electronics
|
||||
*
|
||||
* S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
|
||||
|
||||
#define CON_OFFSET 0x700
|
||||
#define MASK_OFFSET 0x900
|
||||
#define PEND_OFFSET 0xA00
|
||||
#define CON_OFFSET_2 0xE00
|
||||
#define MASK_OFFSET_2 0xF00
|
||||
#define PEND_OFFSET_2 0xF40
|
||||
|
||||
#define GPIOINT_LEVEL_LOW 0x0
|
||||
#define GPIOINT_LEVEL_HIGH 0x1
|
||||
#define GPIOINT_EDGE_FALLING 0x2
|
||||
#define GPIOINT_EDGE_RISING 0x3
|
||||
#define GPIOINT_EDGE_BOTH 0x4
|
||||
|
||||
static int group_to_con_offset(int group)
|
||||
{
|
||||
return group << 2;
|
||||
}
|
||||
|
||||
static int group_to_mask_offset(int group)
|
||||
{
|
||||
return group << 2;
|
||||
}
|
||||
|
||||
static int group_to_pend_offset(int group)
|
||||
{
|
||||
return group << 2;
|
||||
}
|
||||
|
||||
static int s5pc100_get_start(unsigned int group)
|
||||
{
|
||||
switch (group) {
|
||||
case 0: return S5PC100_GPIO_A0_START;
|
||||
case 1: return S5PC100_GPIO_A1_START;
|
||||
case 2: return S5PC100_GPIO_B_START;
|
||||
case 3: return S5PC100_GPIO_C_START;
|
||||
case 4: return S5PC100_GPIO_D_START;
|
||||
case 5: return S5PC100_GPIO_E0_START;
|
||||
case 6: return S5PC100_GPIO_E1_START;
|
||||
case 7: return S5PC100_GPIO_F0_START;
|
||||
case 8: return S5PC100_GPIO_F1_START;
|
||||
case 9: return S5PC100_GPIO_F2_START;
|
||||
case 10: return S5PC100_GPIO_F3_START;
|
||||
case 11: return S5PC100_GPIO_G0_START;
|
||||
case 12: return S5PC100_GPIO_G1_START;
|
||||
case 13: return S5PC100_GPIO_G2_START;
|
||||
case 14: return S5PC100_GPIO_G3_START;
|
||||
case 15: return S5PC100_GPIO_I_START;
|
||||
case 16: return S5PC100_GPIO_J0_START;
|
||||
case 17: return S5PC100_GPIO_J1_START;
|
||||
case 18: return S5PC100_GPIO_J2_START;
|
||||
case 19: return S5PC100_GPIO_J3_START;
|
||||
case 20: return S5PC100_GPIO_J4_START;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int s5pc100_get_group(unsigned int irq)
|
||||
{
|
||||
irq -= S3C_IRQ_GPIO(0);
|
||||
|
||||
switch (irq) {
|
||||
case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
|
||||
return 0;
|
||||
case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
|
||||
return 1;
|
||||
case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
|
||||
return 2;
|
||||
case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
|
||||
return 3;
|
||||
case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
|
||||
return 4;
|
||||
case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
|
||||
return 5;
|
||||
case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
|
||||
return 6;
|
||||
case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
|
||||
return 7;
|
||||
case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
|
||||
return 8;
|
||||
case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
|
||||
return 9;
|
||||
case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
|
||||
return 10;
|
||||
case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
|
||||
return 11;
|
||||
case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
|
||||
return 12;
|
||||
case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
|
||||
return 13;
|
||||
case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
|
||||
return 14;
|
||||
case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
|
||||
return 15;
|
||||
case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
|
||||
return 16;
|
||||
case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
|
||||
return 17;
|
||||
case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
|
||||
return 18;
|
||||
case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
|
||||
return 19;
|
||||
case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
|
||||
return 20;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int s5pc100_get_offset(unsigned int irq)
|
||||
{
|
||||
struct gpio_chip *chip = get_irq_data(irq);
|
||||
return irq - S3C_IRQ_GPIO(chip->base);
|
||||
}
|
||||
|
||||
static void s5pc100_gpioint_ack(unsigned int irq)
|
||||
{
|
||||
int group, offset, pend_offset;
|
||||
unsigned int value;
|
||||
|
||||
group = s5pc100_get_group(irq);
|
||||
offset = s5pc100_get_offset(irq);
|
||||
pend_offset = group_to_pend_offset(group);
|
||||
|
||||
value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
|
||||
value |= 1 << offset;
|
||||
__raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
|
||||
}
|
||||
|
||||
static void s5pc100_gpioint_mask(unsigned int irq)
|
||||
{
|
||||
int group, offset, mask_offset;
|
||||
unsigned int value;
|
||||
|
||||
group = s5pc100_get_group(irq);
|
||||
offset = s5pc100_get_offset(irq);
|
||||
mask_offset = group_to_mask_offset(group);
|
||||
|
||||
value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
|
||||
value |= 1 << offset;
|
||||
__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
|
||||
}
|
||||
|
||||
static void s5pc100_gpioint_unmask(unsigned int irq)
|
||||
{
|
||||
int group, offset, mask_offset;
|
||||
unsigned int value;
|
||||
|
||||
group = s5pc100_get_group(irq);
|
||||
offset = s5pc100_get_offset(irq);
|
||||
mask_offset = group_to_mask_offset(group);
|
||||
|
||||
value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
|
||||
value &= ~(1 << offset);
|
||||
__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
|
||||
}
|
||||
|
||||
static void s5pc100_gpioint_mask_ack(unsigned int irq)
|
||||
{
|
||||
s5pc100_gpioint_mask(irq);
|
||||
s5pc100_gpioint_ack(irq);
|
||||
}
|
||||
|
||||
static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
|
||||
{
|
||||
int group, offset, con_offset;
|
||||
unsigned int value;
|
||||
|
||||
group = s5pc100_get_group(irq);
|
||||
offset = s5pc100_get_offset(irq);
|
||||
con_offset = group_to_con_offset(group);
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_NONE:
|
||||
printk(KERN_WARNING "No irq type\n");
|
||||
return -EINVAL;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
type = GPIOINT_EDGE_RISING;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
type = GPIOINT_EDGE_FALLING;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
type = GPIOINT_EDGE_BOTH;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
type = GPIOINT_LEVEL_HIGH;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
type = GPIOINT_LEVEL_LOW;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
|
||||
value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
|
||||
value &= ~(0xf << (offset * 0x4));
|
||||
value |= (type << (offset * 0x4));
|
||||
__raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct irq_chip s5pc100_gpioint = {
|
||||
.name = "GPIO",
|
||||
.ack = s5pc100_gpioint_ack,
|
||||
.mask = s5pc100_gpioint_mask,
|
||||
.mask_ack = s5pc100_gpioint_mask_ack,
|
||||
.unmask = s5pc100_gpioint_unmask,
|
||||
.set_type = s5pc100_gpioint_set_type,
|
||||
};
|
||||
|
||||
void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
int group, offset, pend_offset, mask_offset;
|
||||
int real_irq, group_end;
|
||||
unsigned int pend, mask;
|
||||
|
||||
group_end = 21;
|
||||
|
||||
for (group = 0; group < group_end; group++) {
|
||||
pend_offset = group_to_pend_offset(group);
|
||||
pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
|
||||
if (!pend)
|
||||
continue;
|
||||
|
||||
mask_offset = group_to_mask_offset(group);
|
||||
mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
|
||||
pend &= ~mask;
|
||||
|
||||
for (offset = 0; offset < 8; offset++) {
|
||||
if (pend & (1 << offset)) {
|
||||
real_irq = s5pc100_get_start(group) + offset;
|
||||
generic_handle_irq(S3C_IRQ_GPIO(real_irq));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
@ -47,6 +47,7 @@
|
||||
#include <plat/adc.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/ts.h>
|
||||
#include <plat/audio.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
@ -196,6 +197,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
|
||||
&s5p_device_fimc0,
|
||||
&s5p_device_fimc1,
|
||||
&s5p_device_fimc2,
|
||||
&s5pc100_device_spdif,
|
||||
};
|
||||
|
||||
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
|
||||
@ -226,6 +228,8 @@ static void __init smdkc100_machine_init(void)
|
||||
|
||||
samsung_keypad_set_platdata(&smdkc100_keypad_data);
|
||||
|
||||
s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
|
||||
|
||||
/* LCD init */
|
||||
gpio_request(S5PC100_GPD(0), "GPD");
|
||||
gpio_request(S5PC100_GPH0(6), "GPH0");
|
||||
|
@ -22,27 +22,15 @@
|
||||
|
||||
#define DISR_OFFSET 0x7008
|
||||
|
||||
static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
|
||||
{
|
||||
s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
|
||||
}
|
||||
|
||||
void s5pc100_fb_gpio_setup_24bpp(void)
|
||||
{
|
||||
unsigned int gpio = 0;
|
||||
|
||||
for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s5pc100_fb_setgpios(S5PC100_GPF0(0), 8);
|
||||
s5pc100_fb_setgpios(S5PC100_GPF1(0), 8);
|
||||
s5pc100_fb_setgpios(S5PC100_GPF2(0), 8);
|
||||
s5pc100_fb_setgpios(S5PC100_GPF3(0), 4);
|
||||
}
|
||||
|
@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
|
||||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5PC100_GPD(3), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
|
||||
|
||||
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgall_range(S5PC100_GPD(5), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
@ -17,52 +17,39 @@
|
||||
#include <mach/regs-clock.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
|
||||
{
|
||||
s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
|
||||
|
||||
for (; nr > 0; nr--, base++)
|
||||
s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
|
||||
void s5pc100_ide_setup_gpio(void)
|
||||
{
|
||||
u32 reg;
|
||||
u32 gpio = 0;
|
||||
|
||||
/* Independent CF interface, CF chip select configuration */
|
||||
reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
|
||||
writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
|
||||
|
||||
/* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
|
||||
for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
|
||||
|
||||
/*CF_Data[0 - 7] */
|
||||
for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
|
||||
|
||||
/* CF_Data[8 - 15] */
|
||||
for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
|
||||
|
||||
/* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
|
||||
for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
|
||||
|
||||
/* EBI_OE, EBI_WE */
|
||||
for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++)
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0));
|
||||
s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
|
||||
|
||||
/* CF_OE, CF_WE */
|
||||
for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
|
||||
|
||||
/* CF_CD */
|
||||
s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
|
||||
|
@ -15,20 +15,9 @@
|
||||
|
||||
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
|
||||
{
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
|
||||
end = S5PC100_GPH3(rows);
|
||||
for (gpio = S5PC100_GPH3(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
|
||||
|
||||
/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
|
||||
end = S5PC100_GPH2(cols);
|
||||
for (gpio = S5PC100_GPH2(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
|
||||
}
|
||||
|
@ -25,8 +25,6 @@
|
||||
void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
unsigned int num;
|
||||
|
||||
num = width;
|
||||
@ -34,20 +32,11 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
if (width == 8)
|
||||
num = width - 2;
|
||||
|
||||
end = S5PC100_GPG0(2 + num);
|
||||
|
||||
/* Set all the necessary GPG0/GPG1 pins to special-function 0 */
|
||||
for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2));
|
||||
|
||||
if (width == 8) {
|
||||
for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
}
|
||||
if (width == 8)
|
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2));
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
|
||||
@ -58,16 +47,9 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
end = S5PC100_GPG2(2 + width);
|
||||
|
||||
/* Set all the necessary GPG2 pins to special-function 2 */
|
||||
for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2));
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
|
||||
@ -78,16 +60,9 @@ void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
||||
void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
end = S5PC100_GPG3(2 + width);
|
||||
|
||||
/* Set all the necessary GPG3 pins to special-function 2 */
|
||||
for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2));
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
|
||||
|
@ -11,9 +11,9 @@ if ARCH_S5PV210
|
||||
|
||||
config CPU_S5PV210
|
||||
bool
|
||||
select PLAT_S5P
|
||||
select S3C_PL330_DMA
|
||||
select S5P_EXT_INT
|
||||
select S5PV210_PM if PM
|
||||
help
|
||||
Enable S5PV210 CPU support
|
||||
|
||||
@ -58,7 +58,6 @@ menu "S5PC110 Machines"
|
||||
config MACH_AQUILA
|
||||
bool "Aquila"
|
||||
select CPU_S5PV210
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select S3C_DEV_FB
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
@ -75,7 +74,7 @@ config MACH_AQUILA
|
||||
config MACH_GONI
|
||||
bool "GONI"
|
||||
select CPU_S5PV210
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select S5P_GPIO_INT
|
||||
select S3C_DEV_FB
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
@ -83,8 +82,15 @@ config MACH_GONI
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C2
|
||||
select S3C_DEV_USB_HSOTG
|
||||
select S5P_DEV_ONENAND
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select S5PV210_SETUP_FB_24BPP
|
||||
select S5PV210_SETUP_I2C1
|
||||
select S5PV210_SETUP_I2C2
|
||||
select S5PV210_SETUP_KEYPAD
|
||||
select S5PV210_SETUP_SDHCI
|
||||
help
|
||||
Machine support for Samsung GONI board
|
||||
@ -93,7 +99,6 @@ config MACH_GONI
|
||||
config MACH_SMDKC110
|
||||
bool "SMDKC110"
|
||||
select CPU_S5PV210
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C2
|
||||
select S3C_DEV_RTC
|
||||
@ -113,7 +118,6 @@ menu "S5PV210 Machines"
|
||||
config MACH_SMDKV210
|
||||
bool "SMDKV210"
|
||||
select CPU_S5PV210
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
@ -134,6 +138,29 @@ config MACH_SMDKV210
|
||||
help
|
||||
Machine support for Samsung SMDKV210
|
||||
|
||||
config MACH_TORBRECK
|
||||
bool "Torbreck"
|
||||
select CPU_S5PV210
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C2
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S5PV210_SETUP_I2C1
|
||||
select S5PV210_SETUP_I2C2
|
||||
select S5PV210_SETUP_SDHCI
|
||||
help
|
||||
Machine support for aESOP Torbreck
|
||||
|
||||
endmenu
|
||||
|
||||
config S5PV210_PM
|
||||
bool
|
||||
help
|
||||
Power Management code common to S5PV210
|
||||
|
||||
endif
|
||||
|
@ -14,6 +14,8 @@ obj- :=
|
||||
|
||||
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o
|
||||
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
|
||||
obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
|
||||
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
|
||||
|
||||
# machine support
|
||||
|
||||
@ -21,6 +23,7 @@ obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o
|
||||
obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o
|
||||
obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o
|
||||
obj-$(CONFIG_MACH_GONI) += mach-goni.o
|
||||
obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
|
||||
|
||||
# device support
|
||||
|
||||
|
@ -31,6 +31,8 @@
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/s5pv210.h>
|
||||
|
||||
static unsigned long xtal;
|
||||
|
||||
static struct clksrc_clk clk_mout_apll = {
|
||||
.clk = {
|
||||
.name = "mout_apll",
|
||||
@ -259,6 +261,36 @@ static struct clksrc_clk clk_sclk_vpll = {
|
||||
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *clkset_moutdmc0src_list[] = {
|
||||
[0] = &clk_sclk_a2m.clk,
|
||||
[1] = &clk_mout_mpll.clk,
|
||||
[2] = NULL,
|
||||
[3] = NULL,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clkset_moutdmc0src = {
|
||||
.sources = clkset_moutdmc0src_list,
|
||||
.nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_dmc0 = {
|
||||
.clk = {
|
||||
.name = "mout_dmc0",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_moutdmc0src,
|
||||
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_dmc0 = {
|
||||
.clk = {
|
||||
.name = "sclk_dmc0",
|
||||
.id = -1,
|
||||
.parent = &clk_mout_dmc0.clk,
|
||||
},
|
||||
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
|
||||
};
|
||||
|
||||
static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk_get_rate(clk->parent) / 2;
|
||||
@ -268,8 +300,29 @@ static struct clk_ops clk_hclk_imem_ops = {
|
||||
.get_rate = s5pv210_clk_imem_get_rate,
|
||||
};
|
||||
|
||||
static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
|
||||
{
|
||||
return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
|
||||
}
|
||||
|
||||
static struct clk_ops clk_fout_apll_ops = {
|
||||
.get_rate = s5pv210_clk_fout_apll_get_rate,
|
||||
};
|
||||
|
||||
static struct clk init_clocks_disable[] = {
|
||||
{
|
||||
.name = "pdma",
|
||||
.id = 0,
|
||||
.parent = &clk_hclk_psys.clk,
|
||||
.enable = s5pv210_clk_ip0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "pdma",
|
||||
.id = 1,
|
||||
.parent = &clk_hclk_psys.clk,
|
||||
.enable = s5pv210_clk_ip0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "rot",
|
||||
.id = -1,
|
||||
.parent = &clk_hclk_dsys.clk,
|
||||
@ -431,6 +484,12 @@ static struct clk init_clocks_disable[] = {
|
||||
.parent = &clk_p,
|
||||
.enable = s5pv210_clk_ip3_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "spdif",
|
||||
.id = -1,
|
||||
.parent = &clk_p,
|
||||
.enable = s5pv210_clk_ip3_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
};
|
||||
|
||||
@ -660,6 +719,53 @@ static struct clksrc_sources clkset_sclk_spdif = {
|
||||
.nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
|
||||
};
|
||||
|
||||
static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct clk *pclk;
|
||||
int ret;
|
||||
|
||||
pclk = clk_get_parent(clk);
|
||||
if (IS_ERR(pclk))
|
||||
return -EINVAL;
|
||||
|
||||
ret = pclk->ops->set_rate(pclk, rate);
|
||||
clk_put(pclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
|
||||
{
|
||||
struct clk *pclk;
|
||||
int rate;
|
||||
|
||||
pclk = clk_get_parent(clk);
|
||||
if (IS_ERR(pclk))
|
||||
return -EINVAL;
|
||||
|
||||
rate = pclk->ops->get_rate(clk);
|
||||
clk_put(pclk);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static struct clk_ops s5pv210_sclk_spdif_ops = {
|
||||
.set_rate = s5pv210_spdif_set_rate,
|
||||
.get_rate = s5pv210_spdif_get_rate,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_spdif = {
|
||||
.clk = {
|
||||
.name = "sclk_spdif",
|
||||
.id = -1,
|
||||
.enable = s5pv210_clk_mask0_ctrl,
|
||||
.ctrlbit = (1 << 27),
|
||||
.ops = &s5pv210_sclk_spdif_ops,
|
||||
},
|
||||
.sources = &clkset_sclk_spdif,
|
||||
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
|
||||
};
|
||||
|
||||
static struct clk *clkset_group2_list[] = {
|
||||
[0] = &clk_ext_xtal_mux,
|
||||
[1] = &clk_xusbxti,
|
||||
@ -743,15 +849,6 @@ static struct clksrc_clk clksrcs[] = {
|
||||
},
|
||||
.sources = &clkset_sclk_mixer,
|
||||
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_spdif",
|
||||
.id = -1,
|
||||
.enable = s5pv210_clk_mask0_ctrl,
|
||||
.ctrlbit = (1 << 27),
|
||||
},
|
||||
.sources = &clkset_sclk_spdif,
|
||||
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
@ -953,12 +1050,93 @@ static struct clksrc_clk *sysclks[] = {
|
||||
&clk_sclk_dac,
|
||||
&clk_sclk_pixel,
|
||||
&clk_sclk_hdmi,
|
||||
&clk_mout_dmc0,
|
||||
&clk_sclk_dmc0,
|
||||
&clk_sclk_audio0,
|
||||
&clk_sclk_audio1,
|
||||
&clk_sclk_audio2,
|
||||
&clk_sclk_spdif,
|
||||
};
|
||||
|
||||
static u32 epll_div[][6] = {
|
||||
{ 48000000, 0, 48, 3, 3, 0 },
|
||||
{ 96000000, 0, 48, 3, 2, 0 },
|
||||
{ 144000000, 1, 72, 3, 2, 0 },
|
||||
{ 192000000, 0, 48, 3, 1, 0 },
|
||||
{ 288000000, 1, 72, 3, 1, 0 },
|
||||
{ 32750000, 1, 65, 3, 4, 35127 },
|
||||
{ 32768000, 1, 65, 3, 4, 35127 },
|
||||
{ 45158400, 0, 45, 3, 3, 10355 },
|
||||
{ 45000000, 0, 45, 3, 3, 10355 },
|
||||
{ 45158000, 0, 45, 3, 3, 10355 },
|
||||
{ 49125000, 0, 49, 3, 3, 9961 },
|
||||
{ 49152000, 0, 49, 3, 3, 9961 },
|
||||
{ 67737600, 1, 67, 3, 3, 48366 },
|
||||
{ 67738000, 1, 67, 3, 3, 48366 },
|
||||
{ 73800000, 1, 73, 3, 3, 47710 },
|
||||
{ 73728000, 1, 73, 3, 3, 47710 },
|
||||
{ 36000000, 1, 32, 3, 4, 0 },
|
||||
{ 60000000, 1, 60, 3, 3, 0 },
|
||||
{ 72000000, 1, 72, 3, 3, 0 },
|
||||
{ 80000000, 1, 80, 3, 3, 0 },
|
||||
{ 84000000, 0, 42, 3, 2, 0 },
|
||||
{ 50000000, 0, 50, 3, 3, 0 },
|
||||
};
|
||||
|
||||
static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned int epll_con, epll_con_k;
|
||||
unsigned int i;
|
||||
|
||||
/* Return if nothing changed */
|
||||
if (clk->rate == rate)
|
||||
return 0;
|
||||
|
||||
epll_con = __raw_readl(S5P_EPLL_CON);
|
||||
epll_con_k = __raw_readl(S5P_EPLL_CON1);
|
||||
|
||||
epll_con_k &= ~PLL46XX_KDIV_MASK;
|
||||
epll_con &= ~(1 << 27 |
|
||||
PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
|
||||
PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
|
||||
PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
|
||||
if (epll_div[i][0] == rate) {
|
||||
epll_con_k |= epll_div[i][5] << 0;
|
||||
epll_con |= (epll_div[i][1] << 27 |
|
||||
epll_div[i][2] << PLL46XX_MDIV_SHIFT |
|
||||
epll_div[i][3] << PLL46XX_PDIV_SHIFT |
|
||||
epll_div[i][4] << PLL46XX_SDIV_SHIFT);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == ARRAY_SIZE(epll_div)) {
|
||||
printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
__raw_writel(epll_con, S5P_EPLL_CON);
|
||||
__raw_writel(epll_con_k, S5P_EPLL_CON1);
|
||||
|
||||
printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
|
||||
clk->rate, rate);
|
||||
|
||||
clk->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops s5pv210_epll_ops = {
|
||||
.set_rate = s5pv210_epll_set_rate,
|
||||
.get_rate = s5p_epll_get_rate,
|
||||
};
|
||||
|
||||
void __init_or_cpufreq s5pv210_setup_clocks(void)
|
||||
{
|
||||
struct clk *xtal_clk;
|
||||
unsigned long xtal;
|
||||
unsigned long vpllsrc;
|
||||
unsigned long armclk;
|
||||
unsigned long hclk_msys;
|
||||
@ -974,6 +1152,10 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
|
||||
unsigned int ptr;
|
||||
u32 clkdiv0, clkdiv1;
|
||||
|
||||
/* Set functions for clk_fout_epll */
|
||||
clk_fout_epll.enable = s5p_epll_enable;
|
||||
clk_fout_epll.ops = &s5pv210_epll_ops;
|
||||
|
||||
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
|
||||
|
||||
clkdiv0 = __raw_readl(S5P_CLK_DIV0);
|
||||
@ -992,11 +1174,12 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
|
||||
|
||||
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
|
||||
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
|
||||
epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
|
||||
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
|
||||
__raw_readl(S5P_EPLL_CON1), pll_4600);
|
||||
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
|
||||
vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
|
||||
|
||||
clk_fout_apll.rate = apll;
|
||||
clk_fout_apll.ops = &clk_fout_apll_ops;
|
||||
clk_fout_mpll.rate = mpll;
|
||||
clk_fout_epll.rate = epll;
|
||||
clk_fout_vpll.rate = vpll;
|
||||
|
@ -85,6 +85,21 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
|
||||
.pfn = __phys_to_pfn(S5PV210_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_DMC0,
|
||||
.pfn = __phys_to_pfn(S5PV210_PA_DMC0),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_DMC1,
|
||||
.pfn = __phys_to_pfn(S5PV210_PA_DMC1),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
|
||||
.pfn =__phys_to_pfn(S5PV210_PA_HSPHY),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}
|
||||
};
|
||||
|
||||
|
484
arch/arm/mach-s5pv210/cpufreq.c
Normal file
484
arch/arm/mach-s5pv210/cpufreq.c
Normal file
@ -0,0 +1,484 @@
|
||||
/* linux/arch/arm/mach-s5pv210/cpufreq.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* CPU frequency scaling for S5PC110/S5PV210
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/cpufreq.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
static struct clk *dmc0_clk;
|
||||
static struct clk *dmc1_clk;
|
||||
static struct cpufreq_freqs freqs;
|
||||
|
||||
/* APLL M,P,S values for 1G/800Mhz */
|
||||
#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
|
||||
#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
|
||||
|
||||
/*
|
||||
* DRAM configurations to calculate refresh counter for changing
|
||||
* frequency of memory.
|
||||
*/
|
||||
struct dram_conf {
|
||||
unsigned long freq; /* HZ */
|
||||
unsigned long refresh; /* DRAM refresh counter * 1000 */
|
||||
};
|
||||
|
||||
/* DRAM configuration (DMC0 and DMC1) */
|
||||
static struct dram_conf s5pv210_dram_conf[2];
|
||||
|
||||
enum perf_level {
|
||||
L0, L1, L2, L3, L4,
|
||||
};
|
||||
|
||||
enum s5pv210_mem_type {
|
||||
LPDDR = 0x1,
|
||||
LPDDR2 = 0x2,
|
||||
DDR2 = 0x4,
|
||||
};
|
||||
|
||||
enum s5pv210_dmc_port {
|
||||
DMC0 = 0,
|
||||
DMC1,
|
||||
};
|
||||
|
||||
static struct cpufreq_frequency_table s5pv210_freq_table[] = {
|
||||
{L0, 1000*1000},
|
||||
{L1, 800*1000},
|
||||
{L2, 400*1000},
|
||||
{L3, 200*1000},
|
||||
{L4, 100*1000},
|
||||
{0, CPUFREQ_TABLE_END},
|
||||
};
|
||||
|
||||
static u32 clkdiv_val[5][11] = {
|
||||
/*
|
||||
* Clock divider value for following
|
||||
* { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
|
||||
* HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
|
||||
* ONEDRAM, MFC, G3D }
|
||||
*/
|
||||
|
||||
/* L0 : [1000/200/100][166/83][133/66][200/200] */
|
||||
{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L1 : [800/200/100][166/83][133/66][200/200] */
|
||||
{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L2 : [400/200/100][166/83][133/66][200/200] */
|
||||
{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L3 : [200/200/100][166/83][133/66][200/200] */
|
||||
{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L4 : [100/100/100][83/83][66/66][100/100] */
|
||||
{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
|
||||
};
|
||||
|
||||
/*
|
||||
* This function set DRAM refresh counter
|
||||
* accoriding to operating frequency of DRAM
|
||||
* ch: DMC port number 0 or 1
|
||||
* freq: Operating frequency of DRAM(KHz)
|
||||
*/
|
||||
static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
|
||||
{
|
||||
unsigned long tmp, tmp1;
|
||||
void __iomem *reg = NULL;
|
||||
|
||||
if (ch == DMC0)
|
||||
reg = (S5P_VA_DMC0 + 0x30);
|
||||
else if (ch == DMC1)
|
||||
reg = (S5P_VA_DMC1 + 0x30);
|
||||
else
|
||||
printk(KERN_ERR "Cannot find DMC port\n");
|
||||
|
||||
/* Find current DRAM frequency */
|
||||
tmp = s5pv210_dram_conf[ch].freq;
|
||||
|
||||
do_div(tmp, freq);
|
||||
|
||||
tmp1 = s5pv210_dram_conf[ch].refresh;
|
||||
|
||||
do_div(tmp1, tmp);
|
||||
|
||||
__raw_writel(tmp1, reg);
|
||||
}
|
||||
|
||||
int s5pv210_verify_speed(struct cpufreq_policy *policy)
|
||||
{
|
||||
if (policy->cpu)
|
||||
return -EINVAL;
|
||||
|
||||
return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
|
||||
}
|
||||
|
||||
unsigned int s5pv210_getspeed(unsigned int cpu)
|
||||
{
|
||||
if (cpu)
|
||||
return 0;
|
||||
|
||||
return clk_get_rate(cpu_clk) / 1000;
|
||||
}
|
||||
|
||||
static int s5pv210_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq,
|
||||
unsigned int relation)
|
||||
{
|
||||
unsigned long reg;
|
||||
unsigned int index, priv_index;
|
||||
unsigned int pll_changing = 0;
|
||||
unsigned int bus_speed_changing = 0;
|
||||
|
||||
freqs.old = s5pv210_getspeed(0);
|
||||
|
||||
if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
|
||||
target_freq, relation, &index))
|
||||
return -EINVAL;
|
||||
|
||||
freqs.new = s5pv210_freq_table[index].frequency;
|
||||
freqs.cpu = 0;
|
||||
|
||||
if (freqs.new == freqs.old)
|
||||
return 0;
|
||||
|
||||
/* Finding current running level index */
|
||||
if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
|
||||
freqs.old, relation, &priv_index))
|
||||
return -EINVAL;
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
|
||||
if (freqs.new > freqs.old) {
|
||||
/* Voltage up: will be implemented */
|
||||
}
|
||||
|
||||
/* Check if there need to change PLL */
|
||||
if ((index == L0) || (priv_index == L0))
|
||||
pll_changing = 1;
|
||||
|
||||
/* Check if there need to change System bus clock */
|
||||
if ((index == L4) || (priv_index == L4))
|
||||
bus_speed_changing = 1;
|
||||
|
||||
if (bus_speed_changing) {
|
||||
/*
|
||||
* Reconfigure DRAM refresh counter value for minimum
|
||||
* temporary clock while changing divider.
|
||||
* expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
|
||||
*/
|
||||
if (pll_changing)
|
||||
s5pv210_set_refresh(DMC1, 83000);
|
||||
else
|
||||
s5pv210_set_refresh(DMC1, 100000);
|
||||
|
||||
s5pv210_set_refresh(DMC0, 83000);
|
||||
}
|
||||
|
||||
/*
|
||||
* APLL should be changed in this level
|
||||
* APLL -> MPLL(for stable transition) -> APLL
|
||||
* Some clock source's clock API are not prepared.
|
||||
* Do not use clock API in below code.
|
||||
*/
|
||||
if (pll_changing) {
|
||||
/*
|
||||
* 1. Temporary Change divider for MFC and G3D
|
||||
* SCLKA2M(200/1=200)->(200/4=50)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_DIV2);
|
||||
reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
|
||||
reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
|
||||
(3 << S5P_CLKDIV2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_DIV2);
|
||||
|
||||
/* For MFC, G3D dividing */
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT0);
|
||||
} while (reg & ((1 << 16) | (1 << 17)));
|
||||
|
||||
/*
|
||||
* 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
|
||||
* (200/4=50)->(667/4=166)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_SRC2);
|
||||
reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
|
||||
reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
|
||||
(1 << S5P_CLKSRC2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC2);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT1);
|
||||
} while (reg & ((1 << 7) | (1 << 3)));
|
||||
|
||||
/*
|
||||
* 3. DMC1 refresh count for 133Mhz if (index == L4) is
|
||||
* true refresh counter is already programed in upper
|
||||
* code. 0x287@83Mhz
|
||||
*/
|
||||
if (!bus_speed_changing)
|
||||
s5pv210_set_refresh(DMC1, 133000);
|
||||
|
||||
/* 4. SCLKAPLL -> SCLKMPLL */
|
||||
reg = __raw_readl(S5P_CLK_SRC0);
|
||||
reg &= ~(S5P_CLKSRC0_MUX200_MASK);
|
||||
reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC0);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT0);
|
||||
} while (reg & (0x1 << 18));
|
||||
|
||||
}
|
||||
|
||||
/* Change divider */
|
||||
reg = __raw_readl(S5P_CLK_DIV0);
|
||||
|
||||
reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
|
||||
S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
|
||||
S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
|
||||
S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
|
||||
|
||||
reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
|
||||
(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
|
||||
(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
|
||||
(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
|
||||
(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
|
||||
(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
|
||||
(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
|
||||
(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
|
||||
|
||||
__raw_writel(reg, S5P_CLK_DIV0);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT0);
|
||||
} while (reg & 0xff);
|
||||
|
||||
/* ARM MCS value changed */
|
||||
reg = __raw_readl(S5P_ARM_MCS_CON);
|
||||
reg &= ~0x3;
|
||||
if (index >= L3)
|
||||
reg |= 0x3;
|
||||
else
|
||||
reg |= 0x1;
|
||||
|
||||
__raw_writel(reg, S5P_ARM_MCS_CON);
|
||||
|
||||
if (pll_changing) {
|
||||
/* 5. Set Lock time = 30us*24Mhz = 0x2cf */
|
||||
__raw_writel(0x2cf, S5P_APLL_LOCK);
|
||||
|
||||
/*
|
||||
* 6. Turn on APLL
|
||||
* 6-1. Set PMS values
|
||||
* 6-2. Wait untile the PLL is locked
|
||||
*/
|
||||
if (index == L0)
|
||||
__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
|
||||
else
|
||||
__raw_writel(APLL_VAL_800, S5P_APLL_CON);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_APLL_CON);
|
||||
} while (!(reg & (0x1 << 29)));
|
||||
|
||||
/*
|
||||
* 7. Change souce clock from SCLKMPLL(667Mhz)
|
||||
* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
|
||||
* (667/4=166)->(200/4=50)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_SRC2);
|
||||
reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
|
||||
reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
|
||||
(0 << S5P_CLKSRC2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC2);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT1);
|
||||
} while (reg & ((1 << 7) | (1 << 3)));
|
||||
|
||||
/*
|
||||
* 8. Change divider for MFC and G3D
|
||||
* (200/4=50)->(200/1=200)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_DIV2);
|
||||
reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
|
||||
reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
|
||||
(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_DIV2);
|
||||
|
||||
/* For MFC, G3D dividing */
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT0);
|
||||
} while (reg & ((1 << 16) | (1 << 17)));
|
||||
|
||||
/* 9. Change MPLL to APLL in MSYS_MUX */
|
||||
reg = __raw_readl(S5P_CLK_SRC0);
|
||||
reg &= ~(S5P_CLKSRC0_MUX200_MASK);
|
||||
reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC0);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT0);
|
||||
} while (reg & (0x1 << 18));
|
||||
|
||||
/*
|
||||
* 10. DMC1 refresh counter
|
||||
* L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
|
||||
* Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
|
||||
*/
|
||||
if (!bus_speed_changing)
|
||||
s5pv210_set_refresh(DMC1, 200000);
|
||||
}
|
||||
|
||||
/*
|
||||
* L4 level need to change memory bus speed, hence onedram clock divier
|
||||
* and memory refresh parameter should be changed
|
||||
*/
|
||||
if (bus_speed_changing) {
|
||||
reg = __raw_readl(S5P_CLK_DIV6);
|
||||
reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
|
||||
reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_DIV6);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT1);
|
||||
} while (reg & (1 << 15));
|
||||
|
||||
/* Reconfigure DRAM refresh counter value */
|
||||
if (index != L4) {
|
||||
/*
|
||||
* DMC0 : 166Mhz
|
||||
* DMC1 : 200Mhz
|
||||
*/
|
||||
s5pv210_set_refresh(DMC0, 166000);
|
||||
s5pv210_set_refresh(DMC1, 200000);
|
||||
} else {
|
||||
/*
|
||||
* DMC0 : 83Mhz
|
||||
* DMC1 : 100Mhz
|
||||
*/
|
||||
s5pv210_set_refresh(DMC0, 83000);
|
||||
s5pv210_set_refresh(DMC1, 100000);
|
||||
}
|
||||
}
|
||||
|
||||
if (freqs.new < freqs.old) {
|
||||
/* Voltage down: will be implemented */
|
||||
}
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
printk(KERN_DEBUG "Perf changed[L%d]\n", index);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy,
|
||||
pm_message_t pmsg)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int check_mem_type(void __iomem *dmc_reg)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = __raw_readl(dmc_reg + 0x4);
|
||||
val = (val & (0xf << 8));
|
||||
|
||||
return val >> 8;
|
||||
}
|
||||
|
||||
static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
unsigned long mem_type;
|
||||
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
return PTR_ERR(cpu_clk);
|
||||
|
||||
dmc0_clk = clk_get(NULL, "sclk_dmc0");
|
||||
if (IS_ERR(dmc0_clk)) {
|
||||
clk_put(cpu_clk);
|
||||
return PTR_ERR(dmc0_clk);
|
||||
}
|
||||
|
||||
dmc1_clk = clk_get(NULL, "hclk_msys");
|
||||
if (IS_ERR(dmc1_clk)) {
|
||||
clk_put(dmc0_clk);
|
||||
clk_put(cpu_clk);
|
||||
return PTR_ERR(dmc1_clk);
|
||||
}
|
||||
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* check_mem_type : This driver only support LPDDR & LPDDR2.
|
||||
* other memory type is not supported.
|
||||
*/
|
||||
mem_type = check_mem_type(S5P_VA_DMC0);
|
||||
|
||||
if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
|
||||
printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Find current refresh counter and frequency each DMC */
|
||||
s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
|
||||
s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
|
||||
|
||||
s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
|
||||
s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
|
||||
|
||||
policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
|
||||
|
||||
cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
|
||||
|
||||
policy->cpuinfo.transition_latency = 40000;
|
||||
|
||||
return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
|
||||
}
|
||||
|
||||
static struct cpufreq_driver s5pv210_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = s5pv210_verify_speed,
|
||||
.target = s5pv210_target,
|
||||
.get = s5pv210_getspeed,
|
||||
.init = s5pv210_cpu_init,
|
||||
.name = "s5pv210",
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = s5pv210_cpufreq_suspend,
|
||||
.resume = s5pv210_cpufreq_resume,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init s5pv210_cpufreq_init(void)
|
||||
{
|
||||
return cpufreq_register_driver(&s5pv210_driver);
|
||||
}
|
||||
|
||||
late_initcall(s5pv210_cpufreq_init);
|
@ -24,29 +24,15 @@ static int s5pv210_cfg_i2s(struct platform_device *pdev)
|
||||
/* configure GPIO for i2s port */
|
||||
switch (pdev->id) {
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
|
||||
case 2:
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
|
||||
break;
|
||||
|
||||
case -1:
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -151,25 +137,13 @@ static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
case 2:
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
default:
|
||||
printk(KERN_DEBUG "Invalid PCM Controller number!");
|
||||
@ -271,13 +245,7 @@ struct platform_device s5pv210_device_pcm2 = {
|
||||
|
||||
static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4));
|
||||
|
||||
return 0;
|
||||
return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4));
|
||||
}
|
||||
|
||||
static struct resource s5pv210_ac97_resource[] = {
|
||||
@ -325,3 +293,43 @@ struct platform_device s5pv210_device_ac97 = {
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
/* S/PDIF Controller platform_device */
|
||||
|
||||
static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct resource s5pv210_spdif_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV210_PA_SPDIF,
|
||||
.end = S5PV210_PA_SPDIF + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_SPDIF,
|
||||
.end = DMACH_SPDIF,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_audio_pdata samsung_spdif_pdata = {
|
||||
.cfg_gpio = s5pv210_spdif_cfg_gpio,
|
||||
};
|
||||
|
||||
static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device s5pv210_device_spdif = {
|
||||
.name = "samsung-spdif",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5pv210_spdif_resource),
|
||||
.resource = s5pv210_spdif_resource,
|
||||
.dev = {
|
||||
.platform_data = &samsung_spdif_pdata,
|
||||
.dma_mask = &s5pv210_spdif_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
@ -35,23 +35,15 @@ static char *spi_src_clks[] = {
|
||||
*/
|
||||
static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
unsigned int base;
|
||||
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP);
|
||||
base = S5PV210_GPB(0);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP);
|
||||
base = S5PV210_GPB(4);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -59,6 +51,9 @@ static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s3c_gpio_cfgall_range(base, 3,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -82,7 +82,7 @@ static struct s3c_pl330_platdata s5pv210_pdma0_pdata = {
|
||||
|
||||
static struct platform_device s5pv210_device_pdma0 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 1,
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5pv210_pdma0_resource),
|
||||
.resource = s5pv210_pdma0_resource,
|
||||
.dev = {
|
||||
@ -144,7 +144,7 @@ static struct s3c_pl330_platdata s5pv210_pdma1_pdata = {
|
||||
|
||||
static struct platform_device s5pv210_device_pdma1 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 2,
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(s5pv210_pdma1_resource),
|
||||
.resource = s5pv210_pdma1_resource,
|
||||
.dev = {
|
||||
|
@ -150,6 +150,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
|
||||
.label = "GPG3",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = S5PV210_GPI(0),
|
||||
.ngpio = S5PV210_GPIO_I_NR,
|
||||
@ -223,34 +224,42 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC00),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(0),
|
||||
.chip = {
|
||||
.base = S5PV210_GPH0(0),
|
||||
.ngpio = S5PV210_GPIO_H0_NR,
|
||||
.label = "GPH0",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC20),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(8),
|
||||
.chip = {
|
||||
.base = S5PV210_GPH1(0),
|
||||
.ngpio = S5PV210_GPIO_H1_NR,
|
||||
.label = "GPH1",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC40),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(16),
|
||||
.chip = {
|
||||
.base = S5PV210_GPH2(0),
|
||||
.ngpio = S5PV210_GPIO_H2_NR,
|
||||
.label = "GPH2",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO + 0xC60),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(24),
|
||||
.chip = {
|
||||
.base = S5PV210_GPH3(0),
|
||||
.ngpio = S5PV210_GPIO_H3_NR,
|
||||
.label = "GPH3",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
},
|
||||
};
|
||||
@ -259,11 +268,14 @@ static __init int s5pv210_gpiolib_init(void)
|
||||
{
|
||||
struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
|
||||
int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
|
||||
int gpioint_group = 0;
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL)
|
||||
if (chip->config == NULL) {
|
||||
chip->config = &gpio_cfg;
|
||||
chip->group = gpioint_group++;
|
||||
}
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5PV210_BANK_BASE(i);
|
||||
}
|
||||
|
@ -55,8 +55,8 @@
|
||||
#define IRQ_SPI1 S5P_IRQ_VIC1(16)
|
||||
#define IRQ_SPI2 S5P_IRQ_VIC1(17)
|
||||
#define IRQ_IRDA S5P_IRQ_VIC1(18)
|
||||
#define IRQ_CAN0 S5P_IRQ_VIC1(19)
|
||||
#define IRQ_CAN1 S5P_IRQ_VIC1(20)
|
||||
#define IRQ_IIC2 S5P_IRQ_VIC1(19)
|
||||
#define IRQ_IIC3 S5P_IRQ_VIC1(20)
|
||||
#define IRQ_HSIRX S5P_IRQ_VIC1(21)
|
||||
#define IRQ_HSITX S5P_IRQ_VIC1(22)
|
||||
#define IRQ_UHOST S5P_IRQ_VIC1(23)
|
||||
@ -109,7 +109,7 @@
|
||||
|
||||
#define IRQ_IPC S5P_IRQ_VIC3(0)
|
||||
#define IRQ_HOSTIF S5P_IRQ_VIC3(1)
|
||||
#define IRQ_MMC3 S5P_IRQ_VIC3(2)
|
||||
#define IRQ_HSMMC3 S5P_IRQ_VIC3(2)
|
||||
#define IRQ_CEC S5P_IRQ_VIC3(3)
|
||||
#define IRQ_TSI S5P_IRQ_VIC3(4)
|
||||
#define IRQ_MDNIE0 S5P_IRQ_VIC3(5)
|
||||
@ -121,8 +121,12 @@
|
||||
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
|
||||
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
|
||||
|
||||
/* GPIO interrupt */
|
||||
#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
|
||||
#define S5P_GPIOINT_GROUP_MAXNR 22
|
||||
|
||||
/* Set the default NR_IRQS */
|
||||
#define NR_IRQS (IRQ_EINT(31) + 1)
|
||||
#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
|
||||
|
||||
/* Compatibility */
|
||||
#define IRQ_LCD_FIFO IRQ_LCD0
|
||||
|
@ -57,6 +57,8 @@
|
||||
|
||||
#define S5P_SZ_UART SZ_256
|
||||
|
||||
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
|
||||
|
||||
#define S5PV210_PA_SROMC (0xE8000000)
|
||||
|
||||
#define S5PV210_PA_CFCON (0xE8200000)
|
||||
@ -73,6 +75,9 @@
|
||||
|
||||
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
|
||||
|
||||
#define S5PV210_PA_HSOTG (0xEC000000)
|
||||
#define S5PV210_PA_HSPHY (0xEC100000)
|
||||
|
||||
#define S5PV210_PA_VIC0 (0xF2000000)
|
||||
#define S5PV210_PA_VIC1 (0xF2100000)
|
||||
#define S5PV210_PA_VIC2 (0xF2200000)
|
||||
@ -81,6 +86,9 @@
|
||||
#define S5PV210_PA_SDRAM (0x20000000)
|
||||
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
|
||||
|
||||
/* S/PDIF */
|
||||
#define S5PV210_PA_SPDIF 0xE1100000
|
||||
|
||||
/* I2S */
|
||||
#define S5PV210_PA_IIS0 0xEEE30000
|
||||
#define S5PV210_PA_IIS1 0xE2100000
|
||||
@ -96,6 +104,9 @@
|
||||
|
||||
#define S5PV210_PA_ADC (0xE1700000)
|
||||
|
||||
#define S5PV210_PA_DMC0 (0xF0000000)
|
||||
#define S5PV210_PA_DMC1 (0xF1400000)
|
||||
|
||||
/* compatibiltiy defines. */
|
||||
#define S3C_PA_UART S5PV210_PA_UART
|
||||
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
|
||||
@ -108,6 +119,7 @@
|
||||
#define S3C_PA_FB S5PV210_PA_FB
|
||||
#define S3C_PA_RTC S5PV210_PA_RTC
|
||||
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
|
||||
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
|
||||
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
|
||||
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
|
||||
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
|
||||
|
43
arch/arm/mach-s5pv210/include/mach/pm-core.h
Normal file
43
arch/arm/mach-s5pv210/include/mach/pm-core.h
Normal file
@ -0,0 +1,43 @@
|
||||
/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
static inline void s3c_pm_debug_init_uart(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_prepare_irqs(void)
|
||||
{
|
||||
__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
|
||||
__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_stop_clocks(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_show_resume_irqs(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
|
||||
struct pm_uart_save *save)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
@ -25,6 +25,7 @@
|
||||
#define S5P_APLL_CON S5P_CLKREG(0x100)
|
||||
#define S5P_MPLL_CON S5P_CLKREG(0x108)
|
||||
#define S5P_EPLL_CON S5P_CLKREG(0x110)
|
||||
#define S5P_EPLL_CON1 S5P_CLKREG(0x114)
|
||||
#define S5P_VPLL_CON S5P_CLKREG(0x120)
|
||||
|
||||
#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
|
||||
@ -67,11 +68,28 @@
|
||||
#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488)
|
||||
#define S5P_CLK_OUT S5P_CLKREG(0x500)
|
||||
|
||||
/* DIV/MUX STATUS */
|
||||
#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
|
||||
#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
|
||||
#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
|
||||
#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
|
||||
|
||||
/* CLKSRC0 */
|
||||
#define S5P_CLKSRC0_MUX200_MASK (0x1<<16)
|
||||
#define S5P_CLKSRC0_MUX200_SHIFT (16)
|
||||
#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
|
||||
#define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
|
||||
#define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
|
||||
|
||||
/* CLKSRC2 */
|
||||
#define S5P_CLKSRC2_G3D_SHIFT (0)
|
||||
#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
|
||||
#define S5P_CLKSRC2_MFC_SHIFT (4)
|
||||
#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
|
||||
|
||||
/* CLKSRC6*/
|
||||
#define S5P_CLKSRC6_ONEDRAM_SHIFT (24)
|
||||
#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
|
||||
|
||||
/* CLKDIV0 */
|
||||
#define S5P_CLKDIV0_APLL_SHIFT (0)
|
||||
#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
|
||||
@ -90,8 +108,20 @@
|
||||
#define S5P_CLKDIV0_PCLK66_SHIFT (28)
|
||||
#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
|
||||
|
||||
/* CLKDIV2 */
|
||||
#define S5P_CLKDIV2_G3D_SHIFT (0)
|
||||
#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
|
||||
#define S5P_CLKDIV2_MFC_SHIFT (4)
|
||||
#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
|
||||
|
||||
/* CLKDIV6 */
|
||||
#define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
|
||||
#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
|
||||
|
||||
#define S5P_SWRESET S5P_CLKREG(0x2000)
|
||||
|
||||
#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
|
||||
|
||||
/* Registers related to power management */
|
||||
#define S5P_PWR_CFG S5P_CLKREG(0xC000)
|
||||
#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004)
|
||||
@ -159,8 +189,11 @@
|
||||
#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1)
|
||||
|
||||
/* OTHERS Resgister */
|
||||
#define S5P_OTHERS_RET_IO (1 << 31)
|
||||
#define S5P_OTHERS_RET_CF (1 << 30)
|
||||
#define S5P_OTHERS_RET_MMC (1 << 29)
|
||||
#define S5P_OTHERS_RET_UART (1 << 28)
|
||||
#define S5P_OTHERS_USB_SIG_MASK (1 << 16)
|
||||
#define S5P_OTHERS_MIPI_DPHY_EN (1 << 28)
|
||||
|
||||
/* MIPI */
|
||||
#define S5P_MIPI_DPHY_EN (3)
|
||||
|
@ -31,13 +31,6 @@
|
||||
|
||||
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
|
||||
|
||||
/* values for S5P_EXTINT0 */
|
||||
#define S5P_EXTINT_LOWLEV (0x00)
|
||||
#define S5P_EXTINT_HILEV (0x01)
|
||||
#define S5P_EXTINT_FALLEDGE (0x02)
|
||||
#define S5P_EXTINT_RISEEDGE (0x03)
|
||||
#define S5P_EXTINT_BOTHEDGE (0x04)
|
||||
|
||||
#define EINT_MODE S3C_GPIO_SFN(0xf)
|
||||
|
||||
#define EINT_GPIO_0(x) S5PV210_GPH0(x)
|
||||
|
19
arch/arm/mach-s5pv210/include/mach/regs-sys.h
Normal file
19
arch/arm/mach-s5pv210/include/mach/regs-sys.h
Normal file
@ -0,0 +1,19 @@
|
||||
/* arch/arm/mach-s5pv210/include/mach/regs-sys.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV210 - System registers definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
|
||||
#define S5PV210_USB_PHY0_EN (1 << 0)
|
||||
#define S5PV210_USB_PHY1_EN (1 << 1)
|
||||
|
||||
/* compatibility defines for s3c-hsotg driver */
|
||||
#define S3C64XX_OTHERS S5PV210_USB_PHY_CON
|
||||
#define S3C64XX_OTHERS_USBMASK S5PV210_USB_PHY0_EN
|
@ -17,6 +17,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H __FILE__
|
||||
|
||||
#define VMALLOC_END (0xE0000000UL)
|
||||
#define VMALLOC_END 0xF6000000UL
|
||||
|
||||
#endif /* __ASM_ARCH_VMALLOC_H */
|
||||
|
@ -16,6 +16,8 @@
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-gpio.h>
|
||||
#include <linux/mfd/max8998.h>
|
||||
#include <linux/mfd/wm8994/pdata.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio.h>
|
||||
@ -379,6 +381,119 @@ static struct max8998_platform_data aquila_max8998_pdata = {
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DBVDD",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD2",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "CPVDD",
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD1",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD2",
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
|
||||
.constraints = {
|
||||
.always_on = 1,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
|
||||
.consumer_supplies = wm8994_fixed_voltage0_supplies,
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
|
||||
.constraints = {
|
||||
.always_on = 1,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
|
||||
.consumer_supplies = wm8994_fixed_voltage1_supplies,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
|
||||
.supply_name = "VCC_1.8V_PDA",
|
||||
.microvolts = 1800000,
|
||||
.gpio = -EINVAL,
|
||||
.init_data = &wm8994_fixed_voltage0_init_data,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
|
||||
.supply_name = "V_BAT",
|
||||
.microvolts = 3700000,
|
||||
.gpio = -EINVAL,
|
||||
.init_data = &wm8994_fixed_voltage1_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device wm8994_fixed_voltage0 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &wm8994_fixed_voltage0_config,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device wm8994_fixed_voltage1 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &wm8994_fixed_voltage1_config,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_avdd1_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD1",
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_dcvdd_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DCVDD",
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_ldo1_data = {
|
||||
.constraints = {
|
||||
.name = "AVDD1_3.0V",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &wm8994_avdd1_supply,
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "DCVDD_1.0V",
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &wm8994_dcvdd_supply,
|
||||
};
|
||||
|
||||
static struct wm8994_pdata wm8994_platform_data = {
|
||||
/* configure gpio1 function: 0x0001(Logic level input/output) */
|
||||
.gpio_defaults[0] = 0x0001,
|
||||
/* configure gpio3/4/5/7 function for AIF2 voice */
|
||||
.gpio_defaults[2] = 0x8100,
|
||||
.gpio_defaults[3] = 0x8100,
|
||||
.gpio_defaults[4] = 0x8100,
|
||||
.gpio_defaults[6] = 0x0100,
|
||||
/* configure gpio8/9/10/11 function for AIF3 BT */
|
||||
.gpio_defaults[7] = 0x8100,
|
||||
.gpio_defaults[8] = 0x0100,
|
||||
.gpio_defaults[9] = 0x0100,
|
||||
.gpio_defaults[10] = 0x0100,
|
||||
.ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
|
||||
.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
|
||||
};
|
||||
|
||||
/* GPIO I2C PMIC */
|
||||
#define AP_I2C_GPIO_PMIC_BUS_4 4
|
||||
static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = {
|
||||
@ -404,6 +519,29 @@ static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
|
||||
#endif
|
||||
};
|
||||
|
||||
/* GPIO I2C AP 1.8V */
|
||||
#define AP_I2C_GPIO_BUS_5 5
|
||||
static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = {
|
||||
.sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
|
||||
.scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
|
||||
};
|
||||
|
||||
static struct platform_device aquila_i2c_gpio5 = {
|
||||
.name = "i2c-gpio",
|
||||
.id = AP_I2C_GPIO_BUS_5,
|
||||
.dev = {
|
||||
.platform_data = &aquila_i2c_gpio5_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
|
||||
{
|
||||
/* CS/ADDR = low 0x34 (FYI: high = 0x36) */
|
||||
I2C_BOARD_INFO("wm8994", 0x1a),
|
||||
.platform_data = &wm8994_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* PMIC Power button */
|
||||
static struct gpio_keys_button aquila_gpio_keys_table[] = {
|
||||
{
|
||||
@ -475,6 +613,7 @@ static void aquila_setup_sdhci(void)
|
||||
|
||||
static struct platform_device *aquila_devices[] __initdata = {
|
||||
&aquila_i2c_gpio_pmic,
|
||||
&aquila_i2c_gpio5,
|
||||
&aquila_device_gpiokeys,
|
||||
&s3c_device_fb,
|
||||
&s5p_device_onenand,
|
||||
@ -484,8 +623,33 @@ static struct platform_device *aquila_devices[] __initdata = {
|
||||
&s5p_device_fimc0,
|
||||
&s5p_device_fimc1,
|
||||
&s5p_device_fimc2,
|
||||
&s5pv210_device_iis0,
|
||||
&wm8994_fixed_voltage0,
|
||||
&wm8994_fixed_voltage1,
|
||||
};
|
||||
|
||||
static void __init aquila_sound_init(void)
|
||||
{
|
||||
unsigned int gpio;
|
||||
|
||||
/* CODEC_XTAL_EN
|
||||
*
|
||||
* The Aquila board have a oscillator which provide main clock
|
||||
* to WM8994 codec. The oscillator provide 24MHz clock to WM8994
|
||||
* clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator.
|
||||
* */
|
||||
gpio = S5PV210_GPH3(2); /* XEINT_26 */
|
||||
gpio_request(gpio, "CODEC_XTAL_EN");
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
|
||||
/* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
|
||||
* The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
|
||||
* because it needs 24MHz clock to operate WM8994 codec.
|
||||
*/
|
||||
__raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
|
||||
}
|
||||
|
||||
static void __init aquila_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
@ -506,6 +670,11 @@ static void __init aquila_machine_init(void)
|
||||
s3c_fimc_setname(1, "s5p-fimc");
|
||||
s3c_fimc_setname(2, "s5p-fimc");
|
||||
|
||||
/* SOUND */
|
||||
aquila_sound_init();
|
||||
i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
|
||||
ARRAY_SIZE(i2c_gpio5_devs));
|
||||
|
||||
/* FB */
|
||||
s3c_fb_set_platdata(&aquila_lcd_pdata);
|
||||
|
||||
|
@ -15,7 +15,13 @@
|
||||
#include <linux/fb.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-gpio.h>
|
||||
#include <linux/i2c/qt602240_ts.h>
|
||||
#include <linux/mfd/max8998.h>
|
||||
#include <linux/mfd/wm8994/pdata.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi_gpio.h>
|
||||
#include <linux/lcd.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio.h>
|
||||
@ -35,7 +41,10 @@
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/clock.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
@ -87,13 +96,12 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
|
||||
/* Frame Buffer */
|
||||
static struct s3c_fb_pd_win goni_fb_win0 = {
|
||||
.win_mode = {
|
||||
.pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*55),
|
||||
.left_margin = 16,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 3,
|
||||
.upper_margin = 2,
|
||||
.lower_margin = 28,
|
||||
.hsync_len = 2,
|
||||
.vsync_len = 2,
|
||||
.vsync_len = 1,
|
||||
.xres = 480,
|
||||
.yres = 800,
|
||||
.refresh = 55,
|
||||
@ -111,9 +119,160 @@ static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
|
||||
.setup_gpio = s5pv210_fb_gpio_setup_24bpp,
|
||||
};
|
||||
|
||||
static int lcd_power_on(struct lcd_device *ld, int enable)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int reset_lcd(struct lcd_device *ld)
|
||||
{
|
||||
static unsigned int first = 1;
|
||||
int reset_gpio = -1;
|
||||
|
||||
reset_gpio = S5PV210_MP05(5);
|
||||
|
||||
if (first) {
|
||||
gpio_request(reset_gpio, "MLCD_RST");
|
||||
first = 0;
|
||||
}
|
||||
|
||||
gpio_direction_output(reset_gpio, 1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static struct lcd_platform_data goni_lcd_platform_data = {
|
||||
.reset = reset_lcd,
|
||||
.power_on = lcd_power_on,
|
||||
.lcd_enabled = 0,
|
||||
.reset_delay = 120, /* 120ms */
|
||||
.power_on_delay = 25, /* 25ms */
|
||||
.power_off_delay = 200, /* 200ms */
|
||||
};
|
||||
|
||||
#define LCD_BUS_NUM 3
|
||||
static struct spi_board_info spi_board_info[] __initdata = {
|
||||
{
|
||||
.modalias = "s6e63m0",
|
||||
.platform_data = &goni_lcd_platform_data,
|
||||
.max_speed_hz = 1200000,
|
||||
.bus_num = LCD_BUS_NUM,
|
||||
.chip_select = 0,
|
||||
.mode = SPI_MODE_3,
|
||||
.controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */
|
||||
},
|
||||
};
|
||||
|
||||
static struct spi_gpio_platform_data lcd_spi_gpio_data = {
|
||||
.sck = S5PV210_MP04(1), /* DISPLAY_CLK */
|
||||
.mosi = S5PV210_MP04(3), /* DISPLAY_SI */
|
||||
.miso = SPI_GPIO_NO_MISO,
|
||||
.num_chipselect = 1,
|
||||
};
|
||||
|
||||
static struct platform_device goni_spi_gpio = {
|
||||
.name = "spi_gpio",
|
||||
.id = LCD_BUS_NUM,
|
||||
.dev = {
|
||||
.parent = &s3c_device_fb.dev,
|
||||
.platform_data = &lcd_spi_gpio_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* KEYPAD */
|
||||
static uint32_t keymap[] __initdata = {
|
||||
/* KEY(row, col, keycode) */
|
||||
KEY(0, 1, KEY_MENU), /* Send */
|
||||
KEY(0, 2, KEY_BACK), /* End */
|
||||
KEY(1, 1, KEY_CONFIG), /* Half shot */
|
||||
KEY(1, 2, KEY_VOLUMEUP),
|
||||
KEY(2, 1, KEY_CAMERA), /* Full shot */
|
||||
KEY(2, 2, KEY_VOLUMEDOWN),
|
||||
};
|
||||
|
||||
static struct matrix_keymap_data keymap_data __initdata = {
|
||||
.keymap = keymap,
|
||||
.keymap_size = ARRAY_SIZE(keymap),
|
||||
};
|
||||
|
||||
static struct samsung_keypad_platdata keypad_data __initdata = {
|
||||
.keymap_data = &keymap_data,
|
||||
.rows = 3,
|
||||
.cols = 3,
|
||||
};
|
||||
|
||||
/* Radio */
|
||||
static struct i2c_board_info i2c1_devs[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("si470x", 0x10),
|
||||
},
|
||||
};
|
||||
|
||||
static void __init goni_radio_init(void)
|
||||
{
|
||||
int gpio;
|
||||
|
||||
gpio = S5PV210_GPJ2(4); /* XMSMDATA_4 */
|
||||
gpio_request(gpio, "FM_INT");
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
|
||||
i2c1_devs[0].irq = gpio_to_irq(gpio);
|
||||
|
||||
gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */
|
||||
gpio_request(gpio, "FM_RST");
|
||||
gpio_direction_output(gpio, 1);
|
||||
}
|
||||
|
||||
/* TSP */
|
||||
static struct qt602240_platform_data qt602240_platform_data = {
|
||||
.x_line = 17,
|
||||
.y_line = 11,
|
||||
.x_size = 800,
|
||||
.y_size = 480,
|
||||
.blen = 0x21,
|
||||
.threshold = 0x28,
|
||||
.voltage = 2800000, /* 2.8V */
|
||||
.orient = QT602240_DIAGONAL,
|
||||
};
|
||||
|
||||
static struct s3c2410_platform_i2c i2c2_data __initdata = {
|
||||
.flags = 0,
|
||||
.bus_num = 2,
|
||||
.slave_addr = 0x10,
|
||||
.frequency = 400 * 1000,
|
||||
.sda_delay = 100,
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c2_devs[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("qt602240_ts", 0x4a),
|
||||
.platform_data = &qt602240_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init goni_tsp_init(void)
|
||||
{
|
||||
int gpio;
|
||||
|
||||
gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */
|
||||
gpio_request(gpio, "TSP_LDO_ON");
|
||||
gpio_direction_output(gpio, 1);
|
||||
gpio_export(gpio, 0);
|
||||
|
||||
gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */
|
||||
gpio_request(gpio, "TSP_INT");
|
||||
|
||||
s5p_register_gpio_interrupt(gpio);
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
|
||||
i2c2_devs[0].irq = gpio_to_irq(gpio);
|
||||
}
|
||||
|
||||
/* MAX8998 regulators */
|
||||
#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
|
||||
|
||||
static struct regulator_consumer_supply goni_ldo5_consumers[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "VALIVE_1.1V",
|
||||
@ -153,6 +312,8 @@ static struct regulator_init_data goni_ldo5_data = {
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
|
||||
.consumer_supplies = goni_ldo5_consumers,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo6_data = {
|
||||
@ -360,6 +521,119 @@ static struct max8998_platform_data goni_max8998_pdata = {
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DBVDD",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD2",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "CPVDD",
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD1",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD2",
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
|
||||
.constraints = {
|
||||
.always_on = 1,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
|
||||
.consumer_supplies = wm8994_fixed_voltage0_supplies,
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
|
||||
.constraints = {
|
||||
.always_on = 1,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
|
||||
.consumer_supplies = wm8994_fixed_voltage1_supplies,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
|
||||
.supply_name = "VCC_1.8V_PDA",
|
||||
.microvolts = 1800000,
|
||||
.gpio = -EINVAL,
|
||||
.init_data = &wm8994_fixed_voltage0_init_data,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
|
||||
.supply_name = "V_BAT",
|
||||
.microvolts = 3700000,
|
||||
.gpio = -EINVAL,
|
||||
.init_data = &wm8994_fixed_voltage1_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device wm8994_fixed_voltage0 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &wm8994_fixed_voltage0_config,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device wm8994_fixed_voltage1 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &wm8994_fixed_voltage1_config,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_avdd1_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD1",
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_dcvdd_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DCVDD",
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_ldo1_data = {
|
||||
.constraints = {
|
||||
.name = "AVDD1_3.0V",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &wm8994_avdd1_supply,
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "DCVDD_1.0V",
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &wm8994_dcvdd_supply,
|
||||
};
|
||||
|
||||
static struct wm8994_pdata wm8994_platform_data = {
|
||||
/* configure gpio1 function: 0x0001(Logic level input/output) */
|
||||
.gpio_defaults[0] = 0x0001,
|
||||
/* configure gpio3/4/5/7 function for AIF2 voice */
|
||||
.gpio_defaults[2] = 0x8100,
|
||||
.gpio_defaults[3] = 0x8100,
|
||||
.gpio_defaults[4] = 0x8100,
|
||||
.gpio_defaults[6] = 0x0100,
|
||||
/* configure gpio8/9/10/11 function for AIF3 BT */
|
||||
.gpio_defaults[7] = 0x8100,
|
||||
.gpio_defaults[8] = 0x0100,
|
||||
.gpio_defaults[9] = 0x0100,
|
||||
.gpio_defaults[10] = 0x0100,
|
||||
.ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
|
||||
.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
|
||||
};
|
||||
|
||||
/* GPIO I2C PMIC */
|
||||
#define AP_I2C_GPIO_PMIC_BUS_4 4
|
||||
static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = {
|
||||
@ -385,6 +659,29 @@ static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
|
||||
#endif
|
||||
};
|
||||
|
||||
/* GPIO I2C AP 1.8V */
|
||||
#define AP_I2C_GPIO_BUS_5 5
|
||||
static struct i2c_gpio_platform_data goni_i2c_gpio5_data = {
|
||||
.sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
|
||||
.scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
|
||||
};
|
||||
|
||||
static struct platform_device goni_i2c_gpio5 = {
|
||||
.name = "i2c-gpio",
|
||||
.id = AP_I2C_GPIO_BUS_5,
|
||||
.dev = {
|
||||
.platform_data = &goni_i2c_gpio5_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
|
||||
{
|
||||
/* CS/ADDR = low 0x34 (FYI: high = 0x36) */
|
||||
I2C_BOARD_INFO("wm8994", 0x1a),
|
||||
.platform_data = &wm8994_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* PMIC Power button */
|
||||
static struct gpio_keys_button goni_gpio_keys_table[] = {
|
||||
{
|
||||
@ -444,11 +741,37 @@ static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = {
|
||||
.ext_cd_gpio_invert = 1,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply mmc2_supplies[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data mmc2_fixed_voltage_init_data = {
|
||||
.constraints = {
|
||||
.name = "V_TF_2.8V",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(mmc2_supplies),
|
||||
.consumer_supplies = mmc2_supplies,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config mmc2_fixed_voltage_config = {
|
||||
.supply_name = "EXT_FLASH_EN",
|
||||
.microvolts = 2800000,
|
||||
.gpio = GONI_EXT_FLASH_EN,
|
||||
.enable_high = true,
|
||||
.init_data = &mmc2_fixed_voltage_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device mmc2_fixed_voltage = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &mmc2_fixed_voltage_config,
|
||||
},
|
||||
};
|
||||
|
||||
static void goni_setup_sdhci(void)
|
||||
{
|
||||
gpio_request(GONI_EXT_FLASH_EN, "FLASH_EN");
|
||||
gpio_direction_output(GONI_EXT_FLASH_EN, 1);
|
||||
|
||||
s3c_sdhci0_set_platdata(&goni_hsmmc0_data);
|
||||
s3c_sdhci1_set_platdata(&goni_hsmmc1_data);
|
||||
s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
|
||||
@ -457,7 +780,10 @@ static void goni_setup_sdhci(void)
|
||||
static struct platform_device *goni_devices[] __initdata = {
|
||||
&s3c_device_fb,
|
||||
&s5p_device_onenand,
|
||||
&goni_spi_gpio,
|
||||
&goni_i2c_gpio_pmic,
|
||||
&goni_i2c_gpio5,
|
||||
&mmc2_fixed_voltage,
|
||||
&goni_device_gpiokeys,
|
||||
&s5p_device_fimc0,
|
||||
&s5p_device_fimc1,
|
||||
@ -465,8 +791,24 @@ static struct platform_device *goni_devices[] __initdata = {
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc1,
|
||||
&s3c_device_hsmmc2,
|
||||
&s5pv210_device_iis0,
|
||||
&s3c_device_usb_hsotg,
|
||||
&samsung_device_keypad,
|
||||
&s3c_device_i2c1,
|
||||
&s3c_device_i2c2,
|
||||
&wm8994_fixed_voltage0,
|
||||
&wm8994_fixed_voltage1,
|
||||
};
|
||||
|
||||
static void __init goni_sound_init(void)
|
||||
{
|
||||
/* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
|
||||
* The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
|
||||
* because it needs 24MHz clock to operate WM8994 codec.
|
||||
*/
|
||||
__raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
|
||||
}
|
||||
|
||||
static void __init goni_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
@ -476,6 +818,20 @@ static void __init goni_map_io(void)
|
||||
|
||||
static void __init goni_machine_init(void)
|
||||
{
|
||||
/* Radio: call before I2C 1 registeration */
|
||||
goni_radio_init();
|
||||
|
||||
/* I2C1 */
|
||||
s3c_i2c1_set_platdata(NULL);
|
||||
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
|
||||
|
||||
/* TSP: call before I2C 2 registeration */
|
||||
goni_tsp_init();
|
||||
|
||||
/* I2C2 */
|
||||
s3c_i2c2_set_platdata(&i2c2_data);
|
||||
i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
|
||||
|
||||
/* PMIC */
|
||||
goni_pmic_init();
|
||||
i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
|
||||
@ -483,9 +839,22 @@ static void __init goni_machine_init(void)
|
||||
/* SDHCI */
|
||||
goni_setup_sdhci();
|
||||
|
||||
/* SOUND */
|
||||
goni_sound_init();
|
||||
i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
|
||||
ARRAY_SIZE(i2c_gpio5_devs));
|
||||
|
||||
/* FB */
|
||||
s3c_fb_set_platdata(&goni_lcd_pdata);
|
||||
|
||||
/* SPI */
|
||||
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
|
||||
|
||||
/* KEYPAD */
|
||||
samsung_keypad_set_platdata(&keypad_data);
|
||||
|
||||
clk_xusbxti.rate = 24000000;
|
||||
|
||||
platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
|
||||
}
|
||||
|
||||
|
@ -28,6 +28,7 @@
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/ata.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
@ -81,6 +82,7 @@ static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = {
|
||||
static struct platform_device *smdkc110_devices[] __initdata = {
|
||||
&s5pv210_device_iis0,
|
||||
&s5pv210_device_ac97,
|
||||
&s5pv210_device_spdif,
|
||||
&s3c_device_cfcon,
|
||||
&s3c_device_i2c0,
|
||||
&s3c_device_i2c1,
|
||||
@ -110,6 +112,8 @@ static void __init smdkc110_map_io(void)
|
||||
|
||||
static void __init smdkc110_machine_init(void)
|
||||
{
|
||||
s3c_pm_init();
|
||||
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
s3c_i2c1_set_platdata(NULL);
|
||||
s3c_i2c2_set_platdata(NULL);
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user