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drm/msm: Set different display size limitation on each target

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The maximum output width of one pipeline depends on the LayerMixer's
capability. It may be different on each target. Also, MDP5 doesn't
have vertical limitation in one frame, as long as the pixel clock
can be supported.

This change obtains the maximum LM resolution from configuration
table and treat it as the whole pipe's limitation for MDP5. The size
limit on MDP4 is not changed.

Signed-off-by: Hai Li <hali@codeaurora.org>
This commit is contained in:
Hai Li
2015-06-24 19:13:40 -04:00
committed by Rob Clark
parent 5cf3a4553f
commit 9b7a9fc29a
5 changed files with 20 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
View File

@@ -527,6 +527,11 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
goto fail; goto fail;
} }
dev->mode_config.min_width = 0;
dev->mode_config.min_height = 0;
dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048;
return kms; return kms;
fail: fail:

8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
View File

@@ -58,6 +58,8 @@ const struct mdp5_cfg_hw msm8x74_config = {
.count = 5, .count = 5,
.base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 }, .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
.nb_stages = 5, .nb_stages = 5,
.max_width = 2048,
.max_height = 0xFFFF,
}, },
.dspp = { .dspp = {
.count = 3, .count = 3,
@@ -126,6 +128,8 @@ const struct mdp5_cfg_hw apq8084_config = {
.count = 6, .count = 6,
.base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 }, .base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
.nb_stages = 5, .nb_stages = 5,
.max_width = 2048,
.max_height = 0xFFFF,
}, },
.dspp = { .dspp = {
.count = 4, .count = 4,
@@ -187,6 +191,8 @@ const struct mdp5_cfg_hw msm8x16_config = {
.count = 2, /* LM0 and LM3 */ .count = 2, /* LM0 and LM3 */
.base = { 0x45000, 0x48000 }, .base = { 0x45000, 0x48000 },
.nb_stages = 5, .nb_stages = 5,
.max_width = 2048,
.max_height = 0xFFFF,
}, },
.dspp = { .dspp = {
.count = 1, .count = 1,
@@ -248,6 +254,8 @@ const struct mdp5_cfg_hw msm8x94_config = {
.count = 6, .count = 6,
.base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 }, .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 },
.nb_stages = 8, .nb_stages = 8,
.max_width = 2048,
.max_height = 0xFFFF,
}, },
.dspp = { .dspp = {
.count = 4, .count = 4,

2
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
View File

@@ -42,6 +42,8 @@ struct mdp5_sub_block {
struct mdp5_lm_block { struct mdp5_lm_block {
MDP5_SUB_BLOCK_DEFINITION; MDP5_SUB_BLOCK_DEFINITION;
uint32_t nb_stages; /* number of stages per blender */ uint32_t nb_stages; /* number of stages per blender */
uint32_t max_width; /* Maximum output resolution */
uint32_t max_height;
}; };
struct mdp5_ctl_block { struct mdp5_ctl_block {

5
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
View File

@@ -579,6 +579,11 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
goto fail; goto fail;
} }
dev->mode_config.min_width = 0;
dev->mode_config.min_height = 0;
dev->mode_config.max_width = config->hw->lm.max_width;
dev->mode_config.max_height = config->hw->lm.max_height;
return kms; return kms;
fail: fail:

4
drivers/gpu/drm/msm/msm_drv.c
View File

@@ -331,10 +331,6 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
} }
} }
dev->mode_config.min_width = 0;
dev->mode_config.min_height = 0;
dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048;
dev->mode_config.funcs = &mode_config_funcs; dev->mode_config.funcs = &mode_config_funcs;
ret = drm_vblank_init(dev, priv->num_crtcs); ret = drm_vblank_init(dev, priv->num_crtcs);