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Merge tag 'arc-v3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

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Pull ARC updates from Vineet Gupta:
 "Nothing too exciting here, just minor fixes/cleanup.  Only noteworthy
  ones are:

   - Moving cache disabling to early boot
   - ARC UART enabled only if earlyprintk setup in cmdline"

* tag 'arc-v3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: Disable caches in early boot if so configured
  ARC: [arcfpga] Early ARC UART to be only activated by cmdline
  ARC: [arcfpga] Get rid of legacy BVCI latency unit support
  ARC: remove duplicate header exports
  ARC: arc_local_timer_setup() need not pass own cpu id
  ARC: Fixed spelling errors within comments
  ARC: make start_thread() out-of-line
  ARC: fix mmuv2 warning
  ARC: [SMP] ISS SMP extension bitrot
This commit is contained in:
Linus Torvalds
2014-06-09 18:05:11 -07:00
parent 214b931320 ef680cdc24
commit 9b651cc227
16 changed files with 158 additions and 249 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arc/include/asm/cache.h
View File

@@ -55,4 +55,31 @@ extern void read_decode_cache_bcr(void);
#endif /* !__ASSEMBLY__ */
/* Instruction cache related Auxiliary registers */
#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
#define ARC_REG_IC_IVIC 0x10
#define ARC_REG_IC_CTRL 0x11
#define ARC_REG_IC_IVIL 0x19
#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
#define ARC_REG_IC_PTAG 0x1E
#endif
/* Bit val in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE 0x1
/* Data cache related Auxiliary registers */
#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
#define ARC_REG_DC_IVDC 0x47
#define ARC_REG_DC_CTRL 0x48
#define ARC_REG_DC_IVDL 0x4A
#define ARC_REG_DC_FLSH 0x4B
#define ARC_REG_DC_FLDL 0x4C
#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
#define ARC_REG_DC_PTAG 0x5C
#endif
/* Bit val in DC_CTRL */
#define DC_CTRL_INV_MODE_FLUSH 0x40
#define DC_CTRL_FLUSH_STATUS 0x100
#endif /* _ASM_CACHE_H */

4
arch/arc/include/asm/irq.h
View File

@@ -19,8 +19,6 @@
#include <asm-generic/irq.h>
extern void arc_init_IRQ(void);
extern int get_hw_config_num_irq(void);
void arc_local_timer_setup(unsigned int cpu);
void arc_local_timer_setup(void);
#endif

29
arch/arc/include/asm/processor.h
View File

@@ -18,7 +18,6 @@
#ifndef __ASSEMBLY__
#include <asm/arcregs.h> /* for STATUS_E1_MASK et all */
#include <asm/ptrace.h>
/* Arch specific stuff which needs to be saved per task.
@@ -41,15 +40,13 @@ struct thread_struct {
/* Forward declaration, a strange C thing */
struct task_struct;
/*
* Return saved PC of a blocked thread.
*/
/* Return saved PC of a blocked thread */
unsigned long thread_saved_pc(struct task_struct *t);
#define task_pt_regs(p) \
((struct pt_regs *)(THREAD_SIZE + (void *)task_stack_page(p)) - 1)
/* Free all resources held by a thread. */
/* Free all resources held by a thread */
#define release_thread(thread) do { } while (0)
/* Prepare to copy thread state - unlazy all lazy status */
@@ -82,26 +79,8 @@ unsigned long thread_saved_pc(struct task_struct *t);
#define KSTK_BLINK(tsk) KSTK_REG(tsk, 4)
#define KSTK_FP(tsk) KSTK_REG(tsk, 0)
/*
* Do necessary setup to start up a newly executed thread.
*
* E1,E2 so that Interrupts are enabled in user mode
* L set, so Loop inhibited to begin with
* lp_start and lp_end seeded with bogus non-zero values so to easily catch
* the ARC700 sr to lp_start hardware bug
*/
#define start_thread(_regs, _pc, _usp) \
do { \
set_fs(USER_DS); /* reads from user space */ \
(_regs)->ret = (_pc); \
/* Interrupts enabled in User Mode */ \
(_regs)->status32 = STATUS_U_MASK | STATUS_L_MASK \
| STATUS_E1_MASK | STATUS_E2_MASK; \
(_regs)->sp = (_usp); \
/* bogus seed values for debugging */ \
(_regs)->lp_start = 0x10; \
(_regs)->lp_end = 0x80; \
} while (0)
extern void start_thread(struct pt_regs * regs, unsigned long pc,
unsigned long usp);
extern unsigned int get_wchan(struct task_struct *p);