clk: renesas: Updates for v5.1 (take two)
- Add RPC (QSPI/HyperFLASH) clocks on R-Car V3H, - Add TMU (timer) clocks on RZ/G2E, - Small fixes and cleanups. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXGKaWgAKCRCKwlD9ZEnx cNZbAQCbPRjoiH9U53jwoDrgqhVdcFazsO+OXLfudIj/aewIEAD9HS0fNY2G0p7x /LDYlg7dXTlgA/p8oNvZg2OLq/H2XQg= =WYY8 -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v5.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull second round of Renesas clk driver updates from Geert Uytterhoeven: - Add RPC (QSPI/HyperFLASH) clocks on R-Car V3H - Add TMU (timer) clocks on RZ/G2E - Small fixes and cleanups * tag 'clk-renesas-for-v5.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a774c0: Add TMU clock clk: renesas: r8a77980: Add RPC clocks clk: renesas: rcar-gen3: Add RPC clocks clk: renesas: rcar-gen3: Add spinlock clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
This commit is contained in:
Stephen Boyd
commit
9b57e0ee89
@ -122,6 +122,11 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
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};
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static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
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DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C),
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DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C),
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DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C),
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DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C),
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DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
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DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
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DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
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DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
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@ -41,6 +41,7 @@ enum clk_ids {
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_OCO,
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/* Module Clocks */
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@ -65,8 +66,14 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_RATE(".oco", CLK_OCO, 32768),
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DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A77980_CLK_RPC),
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/* Core Clock Outputs */
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DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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@ -164,6 +171,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
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DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
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DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
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DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
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DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC),
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DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
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DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
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DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
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@ -30,6 +30,21 @@
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#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
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static spinlock_t cpg_lock;
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static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&cpg_lock, flags);
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val = readl(reg);
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val &= ~clear;
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val |= set;
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writel(val, reg);
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spin_unlock_irqrestore(&cpg_lock, flags);
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};
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struct cpg_simple_notifier {
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struct notifier_block nb;
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void __iomem *reg;
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@ -118,7 +133,6 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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unsigned int i;
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u32 val, kick;
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/* Factor of 2 is for fixed divider */
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mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
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@ -127,17 +141,14 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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val = readl(zclk->reg) & ~zclk->mask;
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val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
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writel(val, zclk->reg);
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cpg_reg_modify(zclk->reg, zclk->mask,
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((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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kick = readl(zclk->kick_reg);
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kick |= CPG_FRQCRB_KICK;
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writel(kick, zclk->kick_reg);
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cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
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/*
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* Note: There is no HW information about the worst case latency.
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@ -266,12 +277,10 @@ static const struct sd_div_table cpg_sd_div_table[] = {
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static int cpg_sd_clock_enable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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u32 val = readl(clock->csn.reg);
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val &= ~(CPG_SD_STP_MASK);
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val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
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writel(val, clock->csn.reg);
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cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
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clock->div_table[clock->cur_div_idx].val &
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CPG_SD_STP_MASK);
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return 0;
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}
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@ -280,7 +289,7 @@ static void cpg_sd_clock_disable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
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cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
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}
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static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
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@ -327,7 +336,6 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
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u32 val;
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unsigned int i;
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for (i = 0; i < clock->div_num; i++)
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@ -339,10 +347,9 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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clock->cur_div_idx = i;
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val = readl(clock->csn.reg);
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val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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writel(val, clock->csn.reg);
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cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
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clock->div_table[i].val &
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(CPG_SD_STP_MASK | CPG_SD_FC_MASK));
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return 0;
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}
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@ -415,6 +422,92 @@ free_clock:
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return clk;
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}
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struct rpc_clock {
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struct clk_divider div;
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struct clk_gate gate;
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/*
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* One notifier covers both RPC and RPCD2 clocks as they are both
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* controlled by the same RPCCKCR register...
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*/
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struct cpg_simple_notifier csn;
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};
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static const struct clk_div_table cpg_rpcsrc_div_table[] = {
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{ 2, 5 }, { 3, 6 }, { 0, 0 },
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};
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static const struct clk_div_table cpg_rpc_div_table[] = {
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{ 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
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};
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static struct clk * __init cpg_rpc_clk_register(const char *name,
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void __iomem *base, const char *parent_name,
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struct raw_notifier_head *notifiers)
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{
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struct rpc_clock *rpc;
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struct clk *clk;
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rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
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if (!rpc)
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return ERR_PTR(-ENOMEM);
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rpc->div.reg = base + CPG_RPCCKCR;
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rpc->div.width = 3;
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rpc->div.table = cpg_rpc_div_table;
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rpc->div.lock = &cpg_lock;
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rpc->gate.reg = base + CPG_RPCCKCR;
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rpc->gate.bit_idx = 8;
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rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
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rpc->gate.lock = &cpg_lock;
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rpc->csn.reg = base + CPG_RPCCKCR;
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
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&rpc->div.hw, &clk_divider_ops,
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&rpc->gate.hw, &clk_gate_ops, 0);
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if (IS_ERR(clk)) {
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kfree(rpc);
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return clk;
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}
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cpg_simple_notifier_register(notifiers, &rpc->csn);
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return clk;
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}
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struct rpcd2_clock {
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struct clk_fixed_factor fixed;
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struct clk_gate gate;
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};
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static struct clk * __init cpg_rpcd2_clk_register(const char *name,
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void __iomem *base,
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const char *parent_name)
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{
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struct rpcd2_clock *rpcd2;
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struct clk *clk;
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rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
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if (!rpcd2)
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return ERR_PTR(-ENOMEM);
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rpcd2->fixed.mult = 1;
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rpcd2->fixed.div = 2;
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rpcd2->gate.reg = base + CPG_RPCCKCR;
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rpcd2->gate.bit_idx = 9;
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rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
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rpcd2->gate.lock = &cpg_lock;
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
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&rpcd2->fixed.hw, &clk_fixed_factor_ops,
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&rpcd2->gate.hw, &clk_gate_ops, 0);
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if (IS_ERR(clk))
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kfree(rpcd2);
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return clk;
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}
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static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
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static unsigned int cpg_clk_extalr __initdata;
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@ -593,6 +686,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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}
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break;
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case CLK_TYPE_GEN3_RPCSRC:
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return clk_register_divider_table(NULL, core->name,
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__clk_get_name(parent), 0,
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base + CPG_RPCCKCR, 3, 2, 0,
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cpg_rpcsrc_div_table,
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&cpg_lock);
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case CLK_TYPE_GEN3_RPC:
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return cpg_rpc_clk_register(core->name, base,
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__clk_get_name(parent), notifiers);
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case CLK_TYPE_GEN3_RPCD2:
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return cpg_rpcd2_clk_register(core->name, base,
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__clk_get_name(parent));
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default:
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return ERR_PTR(-EINVAL);
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}
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@ -613,5 +721,8 @@ int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
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if (attr)
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cpg_quirks = (uintptr_t)attr->data;
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pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
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spin_lock_init(&cpg_lock);
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return 0;
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}
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@ -23,6 +23,9 @@ enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_Z2,
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CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
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CLK_TYPE_GEN3_RPCSRC,
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CLK_TYPE_GEN3_RPC,
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CLK_TYPE_GEN3_RPCD2,
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/* SoC specific definitions start here */
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CLK_TYPE_GEN3_SOC_BASE,
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@ -57,6 +60,7 @@ struct rcar_gen3_cpg_pll_config {
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u8 osc_prediv;
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};
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#define CPG_RPCCKCR 0x238
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#define CPG_RCKCR 0x240
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struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
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