drm/amd/powerplay: expose supported clock domains only through sysfs
Do not expose those unsupported clock domains through sysfs on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2828,10 +2828,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
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DRM_ERROR("failed to create device file pp_dpm_socclk\n");
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return ret;
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}
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ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
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if (ret) {
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DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
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return ret;
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if (adev->asic_type != CHIP_ARCTURUS) {
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ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
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if (ret) {
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DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
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return ret;
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}
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}
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}
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if (adev->asic_type >= CHIP_VEGA20) {
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@ -2841,10 +2843,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
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return ret;
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}
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}
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ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
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if (ret) {
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DRM_ERROR("failed to create device file pp_dpm_pcie\n");
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return ret;
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if (adev->asic_type != CHIP_ARCTURUS) {
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ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
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if (ret) {
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DRM_ERROR("failed to create device file pp_dpm_pcie\n");
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return ret;
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}
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}
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ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
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if (ret) {
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@ -2948,9 +2952,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
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device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
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if (adev->asic_type >= CHIP_VEGA10) {
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device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
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device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
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if (adev->asic_type != CHIP_ARCTURUS)
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device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
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}
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device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
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if (adev->asic_type != CHIP_ARCTURUS)
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device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
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if (adev->asic_type >= CHIP_VEGA20)
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device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
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device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
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