forked from Minki/linux
iwlegacy: use FH49_ prefix in 4965 code
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
This commit is contained in:
Stanislaw Gruszka
parent
53143a1809
commit
9a95b37015
@ -138,22 +138,22 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
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u32 rb_timeout = 0;
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if (il->cfg->mod_params->amsdu_size_8K)
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
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rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
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else
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
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rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
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/* Stop Rx DMA */
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il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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/* Reset driver's Rx queue write idx */
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il_wr(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
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il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
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/* Tell device where to find RBD circular buffer in DRAM */
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il_wr(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
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(u32)(rxq->bd_dma >> 8));
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/* Tell device where in DRAM to update its Rx status */
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il_wr(il, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG,
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rxq->rb_stts_dma >> 4);
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/* Enable Rx DMA
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@ -162,13 +162,13 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
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* RB timeout 0x10
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* 256 RBDs
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*/
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il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG,
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FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
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il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
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FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
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rb_size|
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(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
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(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
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(rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
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(rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
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/* Set interrupt coalescing timer to default (2048 usecs) */
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il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
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@ -443,9 +443,9 @@ int il4965_rxq_stop(struct il_priv *il)
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{
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/* stop Rx DMA */
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il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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il_poll_bit(il, FH_MEM_RSSR_RX_STATUS_REG,
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FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
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il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
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FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
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return 0;
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}
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@ -1180,15 +1180,15 @@ u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant, u8 valid)
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static const char *il4965_get_fh_string(int cmd)
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{
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switch (cmd) {
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IL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
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IL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
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IL_CMD(FH_RSCSR_CHNL0_WPTR);
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IL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
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IL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
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IL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
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IL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
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IL_CMD(FH_TSSR_TX_STATUS_REG);
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IL_CMD(FH_TSSR_TX_ERROR_REG);
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IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
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IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
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IL_CMD(FH49_RSCSR_CHNL0_WPTR);
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IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
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IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
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IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
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IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
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IL_CMD(FH49_TSSR_TX_STATUS_REG);
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IL_CMD(FH49_TSSR_TX_ERROR_REG);
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default:
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return "UNKNOWN";
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}
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@ -1202,15 +1202,15 @@ int il4965_dump_fh(struct il_priv *il, char **buf, bool display)
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size_t bufsz = 0;
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#endif
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static const u32 fh_tbl[] = {
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FH_RSCSR_CHNL0_STTS_WPTR_REG,
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FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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FH_RSCSR_CHNL0_WPTR,
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FH_MEM_RCSR_CHNL0_CONFIG_REG,
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FH_MEM_RSSR_SHARED_CTRL_REG,
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FH_MEM_RSSR_RX_STATUS_REG,
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FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
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FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_ERROR_REG
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FH49_RSCSR_CHNL0_STTS_WPTR_REG,
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FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
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FH49_RSCSR_CHNL0_WPTR,
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FH49_MEM_RCSR_CHNL0_CONFIG_REG,
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FH49_MEM_RSSR_SHARED_CTRL_REG,
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FH49_MEM_RSSR_RX_STATUS_REG,
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FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
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FH49_TSSR_TX_STATUS_REG,
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FH49_TSSR_TX_ERROR_REG
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};
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#ifdef CONFIG_IWLEGACY_DEBUG
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if (display) {
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@ -2010,7 +2010,7 @@ int il4965_txq_ctx_alloc(struct il_priv *il)
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il4965_txq_set_sched(il, 0);
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/* Tell NIC where to find the "keep warm" buffer */
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il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);
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il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
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spin_unlock_irqrestore(&il->lock, flags);
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@ -2049,7 +2049,7 @@ void il4965_txq_ctx_reset(struct il_priv *il)
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il4965_txq_set_sched(il, 0);
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/* Tell NIC where to find the "keep warm" buffer */
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il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);
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il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
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spin_unlock_irqrestore(&il->lock, flags);
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@ -2078,14 +2078,14 @@ void il4965_txq_ctx_stop(struct il_priv *il)
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/* Stop each Tx DMA channel, and wait for it to be idle */
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for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
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il_wr(il,
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FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
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if (il_poll_bit(il, FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
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FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
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if (il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
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FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
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1000))
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IL_ERR("Failing on timeout while stopping"
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" DMA channel %d [0x%08x]", ch,
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il_rd(il,
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FH_TSSR_TX_STATUS_REG));
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FH49_TSSR_TX_STATUS_REG));
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}
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spin_unlock_irqrestore(&il->lock, flags);
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@ -3743,7 +3743,7 @@ int il4965_hw_tx_queue_init(struct il_priv *il,
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int txq_id = txq->q.id;
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/* Circular buffer (TFD queue in DRAM) physical base address */
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il_wr(il, FH_MEM_CBBC_QUEUE(txq_id),
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il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id),
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txq->q.dma_addr >> 8);
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return 0;
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@ -4262,7 +4262,7 @@ static void il4965_irq_tasklet(struct il_priv *il)
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if (inta & ~(il->inta_mask)) {
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IL_WARN("Disabled INTA bits 0x%08x were pending\n",
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inta & ~il->inta_mask);
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IL_WARN(" with FH_INT = 0x%08x\n", inta_fh);
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IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
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}
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/* Re-enable all interrupts */
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@ -4798,7 +4798,7 @@ static const char * const desc_lookup_text[] = {
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"HW_ERROR_TEMPERATURE",
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"ILLEGAL_CHAN_FREQ",
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"VCC_NOT_STBL",
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"FH_ERROR",
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"FH49_ERROR",
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"NMI_INTERRUPT_HOST",
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"NMI_INTERRUPT_ACTION_PT",
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"NMI_INTERRUPT_UNKNOWN",
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@ -4969,14 +4969,14 @@ static int il4965_alive_notify(struct il_priv *il)
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/* Enable DMA channel */
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for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
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il_wr(il,
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FH_TCSR_CHNL_TX_CONFIG_REG(chan),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
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FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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/* Update FH chicken bits */
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reg_val = il_rd(il, FH_TX_CHICKEN_BITS_REG);
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il_wr(il, FH_TX_CHICKEN_BITS_REG,
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reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
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il_wr(il, FH49_TX_CHICKEN_BITS_REG,
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reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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/* Disable chain mode for all queues */
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il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
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@ -630,7 +630,7 @@ static int il4965_hw_set_hw_params(struct il_priv *il)
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il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
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il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
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il->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
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il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
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il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
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il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
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@ -2835,7 +2835,7 @@ struct il_tfd_tb {
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* contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
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*
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* Driver must indicate the physical address of the base of each
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* circular buffer via the FH_MEM_CBBC_QUEUE registers.
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* circular buffer via the FH49_MEM_CBBC_QUEUE registers.
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*
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* Each TFD contains pointer/size information for up to 20 data buffers
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* in host DRAM. These buffers collectively contain the (one) frame described
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@ -71,8 +71,8 @@
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* This I/O area is directly read/writable by driver (e.g. Linux uses writel())
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* Addresses are offsets from device's PCI hardware base address.
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*/
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#define FH_MEM_LOWER_BOUND (0x1000)
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#define FH_MEM_UPPER_BOUND (0x2000)
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#define FH49_MEM_LOWER_BOUND (0x1000)
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#define FH49_MEM_UPPER_BOUND (0x2000)
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/**
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* Keep-Warm (KW) buffer base address.
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@ -83,7 +83,7 @@
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* from going into a power-savings mode that would cause higher DRAM latency,
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* and possible data over/under-runs, before all Tx/Rx is complete.
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*
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* Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
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* Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
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* of the buffer, which must be 4K aligned. Once this is set up, the 4965
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* automatically invokes keep-warm accesses when normal accesses might not
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* be sufficient to maintain fast DRAM response.
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@ -91,7 +91,7 @@
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* Bit fields:
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* 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
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*/
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#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
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#define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
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/**
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@ -106,11 +106,11 @@
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* Bit fields in each pointer register:
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* 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
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*/
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#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
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#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
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#define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
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#define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
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/* Find TFD CB base pointer for given queue (range 0-15). */
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#define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
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#define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
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/**
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@ -132,18 +132,18 @@
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* Each entry (1 dword) points to a receive buffer (RB) of consistent size
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* (typically 4K, although 8K or 16K are also selectable by driver).
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* Driver sets up RB size and number of RBDs in the CB via Rx config
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* register FH_MEM_RCSR_CHNL0_CONFIG_REG.
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* register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
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*
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* Bit fields within one RBD:
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* 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
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*
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* Driver sets physical address [35:8] of base of RBD circular buffer
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* into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
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* into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
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*
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* 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
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* (RBs) have been filled, via a "write pointer", actually the idx of
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* the RB's corresponding RBD within the circular buffer. Driver sets
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* physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
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* physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
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*
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* Bit fields in lower dword of Rx status buffer (upper dword not used
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* by driver; see struct il4965_shared, val0):
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@ -154,7 +154,7 @@
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* As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
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* enter pointers to these RBs into contiguous RBD circular buffer entries,
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* and update the 4965's "write" idx register,
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* FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
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* FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
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*
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* This "write" idx corresponds to the *next* RBD that the driver will make
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* available, i.e. one RBD past the tail of the ready-to-fill RBDs within
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@ -182,23 +182,23 @@
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* and "read" idxes; that is, make sure that there are no more than 254
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* buffers waiting to be filled.
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*/
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#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
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#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
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#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
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#define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
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#define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
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#define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
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/**
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* Physical base address of 8-byte Rx Status buffer.
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* Bit fields:
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* 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
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*/
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#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
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#define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
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/**
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* Physical base address of Rx Buffer Descriptor Circular Buffer.
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* Bit fields:
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* 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
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*/
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#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
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#define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
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/**
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* Rx write pointer (idx, really!).
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@ -206,20 +206,20 @@
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* 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
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* NOTE: For 256-entry circular buffer, use only bits [7:0].
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*/
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#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
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#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
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#define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
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#define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
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/**
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* Rx Config/Status Registers (RCSR)
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* Rx Config Reg for channel 0 (only channel used)
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*
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* Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
|
||||
* Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
|
||||
* normal operation (see bit fields).
|
||||
*
|
||||
* Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
|
||||
* Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
|
||||
* FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
|
||||
* Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
|
||||
* Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
|
||||
* FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
|
||||
*
|
||||
* Bit fields:
|
||||
* 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
|
||||
@ -236,67 +236,67 @@
|
||||
* typical value 0x10 (about 1/2 msec)
|
||||
* 3- 0: reserved
|
||||
*/
|
||||
#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
|
||||
#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
|
||||
#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
|
||||
#define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
|
||||
#define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
|
||||
#define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
|
||||
|
||||
#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
|
||||
#define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
|
||||
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
|
||||
|
||||
#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
|
||||
#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
|
||||
#define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
|
||||
#define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
|
||||
#define RX_RB_TIMEOUT (0x10)
|
||||
|
||||
#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
|
||||
#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
|
||||
#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
|
||||
#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
|
||||
#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
|
||||
#define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
|
||||
|
||||
#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
|
||||
#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
|
||||
#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
|
||||
#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
|
||||
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
|
||||
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
|
||||
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
|
||||
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
|
||||
|
||||
#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
|
||||
#define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
|
||||
#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
|
||||
|
||||
/**
|
||||
* Rx Shared Status Registers (RSSR)
|
||||
*
|
||||
* After stopping Rx DMA channel (writing 0 to
|
||||
* FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
|
||||
* FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
|
||||
* FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
|
||||
* FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
|
||||
*
|
||||
* Bit fields:
|
||||
* 24: 1 = Channel 0 is idle
|
||||
*
|
||||
* FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
|
||||
* FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
|
||||
* contain default values that should not be altered by the driver.
|
||||
*/
|
||||
#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
|
||||
#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
|
||||
#define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
|
||||
#define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
|
||||
|
||||
#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
|
||||
#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
|
||||
#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
|
||||
(FH_MEM_RSSR_LOWER_BOUND + 0x008)
|
||||
#define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
|
||||
#define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
|
||||
#define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
|
||||
(FH49_MEM_RSSR_LOWER_BOUND + 0x008)
|
||||
|
||||
#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
|
||||
#define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
|
||||
|
||||
#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
|
||||
#define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
|
||||
|
||||
/* TFDB Area - TFDs buffer table */
|
||||
#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
|
||||
#define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900)
|
||||
#define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958)
|
||||
#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
|
||||
#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
|
||||
#define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
|
||||
#define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
|
||||
#define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
|
||||
#define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
|
||||
#define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
|
||||
|
||||
/**
|
||||
* Transmit DMA Channel Control/Status Registers (TCSR)
|
||||
@ -306,10 +306,10 @@
|
||||
* which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
|
||||
*
|
||||
* To use a Tx DMA channel, driver must initialize its
|
||||
* FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
|
||||
* FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
|
||||
*
|
||||
* FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
|
||||
* FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
|
||||
* FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
|
||||
* FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
|
||||
*
|
||||
* All other bits should be 0.
|
||||
*
|
||||
@ -320,62 +320,62 @@
|
||||
* 3: Enable internal DMA requests (1, normal operation), disable (0)
|
||||
* 2- 0: Reserved, set to "0"
|
||||
*/
|
||||
#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
|
||||
#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
|
||||
#define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
|
||||
#define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
|
||||
|
||||
/* Find Control/Status reg for given Tx DMA/FIFO channel */
|
||||
#define FH49_TCSR_CHNL_NUM (7)
|
||||
#define FH50_TCSR_CHNL_NUM (8)
|
||||
|
||||
/* TCSR: tx_config register values */
|
||||
#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
|
||||
(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
|
||||
#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
|
||||
(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
|
||||
#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
|
||||
(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
|
||||
#define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
|
||||
(FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
|
||||
#define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
|
||||
(FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
|
||||
#define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
|
||||
(FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
|
||||
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
|
||||
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
|
||||
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
|
||||
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
|
||||
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
|
||||
#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
|
||||
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
|
||||
|
||||
#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
|
||||
#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
|
||||
#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
|
||||
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
|
||||
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
|
||||
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
|
||||
|
||||
#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
|
||||
#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
|
||||
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
|
||||
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
|
||||
|
||||
/**
|
||||
* Tx Shared Status Registers (TSSR)
|
||||
*
|
||||
* After stopping Tx DMA channel (writing 0 to
|
||||
* FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
|
||||
* FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
|
||||
* FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
|
||||
* FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
|
||||
* (channel's buffers empty | no pending requests).
|
||||
*
|
||||
* Bit fields:
|
||||
* 31-24: 1 = Channel buffers empty (channel 7:0)
|
||||
* 23-16: 1 = No pending requests (channel 7:0)
|
||||
*/
|
||||
#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
|
||||
#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
|
||||
#define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
|
||||
#define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
|
||||
|
||||
#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
|
||||
#define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
|
||||
|
||||
/**
|
||||
* Bit fields for TSSR(Tx Shared Status & Control) error status register:
|
||||
@ -394,22 +394,22 @@
|
||||
* synchronized to the TxFIFO status
|
||||
* uCode/driver must write "1" in order to clear this flag
|
||||
*/
|
||||
#define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018)
|
||||
#define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
|
||||
|
||||
#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
|
||||
#define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
|
||||
|
||||
/* Tx service channels */
|
||||
#define FH_SRVC_CHNL (9)
|
||||
#define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8)
|
||||
#define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
|
||||
#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
|
||||
(FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
|
||||
#define FH49_SRVC_CHNL (9)
|
||||
#define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
|
||||
#define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
|
||||
#define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
|
||||
(FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
|
||||
|
||||
#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
|
||||
#define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
|
||||
/* Instruct FH to increment the retry count of a packet when
|
||||
* it is brought from the memory to TX-FIFO
|
||||
*/
|
||||
#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
|
||||
#define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
|
||||
|
||||
/* Keep Warm Size */
|
||||
#define IL_KW_SIZE 0x1000 /* 4k */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user