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drm/nouveau/fb/gf100-: allocate mmu debug buffers

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Later chipsets require setting this up both in FB and GR, so let's just
move the allocation to FB.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2016-04-14 10:39:18 +10:00
parent 917d95a86e
commit 99c5917253
13 changed files with 58 additions and 36 deletions
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3
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
View File

@ -55,6 +55,9 @@ struct nvkm_fb {
struct nvkm_fb_tile region[16];
int regions;
} tile;
struct nvkm_memory *mmu_rd;
struct nvkm_memory *mmu_wr;
};
bool nvkm_fb_memtype_valid(struct nvkm_fb *, u32 memtype);

29
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -1616,30 +1616,10 @@ gf100_gr_oneinit(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
int ret, i, j;
int i, j;
nvkm_pmu_pgob(device->pmu, false);
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,
&gr->unk4188b4);
if (ret)
return ret;
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,
&gr->unk4188b8);
if (ret)
return ret;
nvkm_kmap(gr->unk4188b4);
for (i = 0; i < 0x1000; i += 4)
nvkm_wo32(gr->unk4188b4, i, 0x00000010);
nvkm_done(gr->unk4188b4);
nvkm_kmap(gr->unk4188b8);
for (i = 0; i < 0x1000; i += 4)
nvkm_wo32(gr->unk4188b8, i, 0x00000010);
nvkm_done(gr->unk4188b8);
gr->rop_nr = gr->func->rops(gr);
gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
for (i = 0; i < gr->gpc_nr; i++) {
@ -1736,8 +1716,6 @@ gf100_gr_dtor(struct nvkm_gr *base)
gf100_gr_dtor_init(gr->fuc_sw_ctx);
gf100_gr_dtor_init(gr->fuc_sw_nonctx);
nvkm_memory_del(&gr->unk4188b8);
nvkm_memory_del(&gr->unk4188b4);
return gr;
}
@ -1822,6 +1800,7 @@ int
gf100_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
@ -1834,8 +1813,8 @@ gf100_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);
gf100_gr_mmio(gr, gr->func->mmio);

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -101,9 +101,6 @@ struct gf100_gr {
u8 ppc_mask[GPC_MAX];
u8 ppc_tpc_nr[GPC_MAX][4];
struct nvkm_memory *unk4188b4;
struct nvkm_memory *unk4188b8;
struct gf100_gr_data mmio_data[4];
struct gf100_gr_mmio mmio_list[4096/8];
u32 size;

7
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View File

@ -24,6 +24,8 @@
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <nvif/class.h>
/*******************************************************************************
@ -181,6 +183,7 @@ int
gk104_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
@ -193,8 +196,8 @@ gk104_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);
gf100_gr_mmio(gr, gr->func->mmio);

6
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View File

@ -22,6 +22,7 @@
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <nvif/class.h>
@ -219,6 +220,7 @@ int
gk20a_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
@ -239,8 +241,8 @@ gk20a_gr_init(struct gf100_gr *gr)
return ret;
/* MMU debug buffer */
nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(fb->mmu_rd) >> 8);
if (gr->func->init_gpc_mmu)
gr->func->init_gpc_mmu(gr);

6
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View File

@ -26,6 +26,7 @@
#include <subdev/bios.h>
#include <subdev/bios/P0260.h>
#include <subdev/fb.h>
#include <nvif/class.h>
@ -311,6 +312,7 @@ int
gm107_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
@ -320,8 +322,8 @@ gm107_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);
gf100_gr_mmio(gr, gr->func->mmio);

6
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View File

@ -24,6 +24,7 @@
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/secboot.h>
#include <nvif/class.h>
@ -56,6 +57,7 @@ int
gm200_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
@ -63,8 +65,8 @@ gm200_gr_init(struct gf100_gr *gr)
int i;
/*XXX: belongs in fb */
nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(fb->mmu_rd) >> 8);
nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000);
gr->func->init_gpc_mmu(gr);

4
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
View File

@ -24,6 +24,7 @@
#include "priv.h"
#include "ram.h"
#include <core/memory.h>
#include <subdev/bios.h>
#include <subdev/bios/M0203.h>
#include <engine/gr.h>
@ -142,6 +143,9 @@ nvkm_fb_dtor(struct nvkm_subdev *subdev)
struct nvkm_fb *fb = nvkm_fb(subdev);
int i;
nvkm_memory_del(&fb->mmu_wr);
nvkm_memory_del(&fb->mmu_rd);
for (i = 0; i < fb->tile.regions; i++)
fb->func->tile.fini(fb, i, &fb->tile.region[i]);

26
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
View File

@ -24,6 +24,9 @@
#include "gf100.h"
#include "ram.h"
#include <core/memory.h>
#include <core/option.h>
extern const u8 gf100_pte_storage_type_map[256];
bool
@ -46,6 +49,28 @@ gf100_fb_intr(struct nvkm_fb *base)
nvkm_debug(subdev, "PBFB intr\n");
}
int
gf100_fb_oneinit(struct nvkm_fb *fb)
{
struct nvkm_device *device = fb->subdev.device;
int ret, size = 0x1000;
size = nvkm_longopt(device->cfgopt, "MmuDebugBufferSize", size);
size = min(size, 0x1000);
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000,
false, &fb->mmu_rd);
if (ret)
return ret;
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000,
false, &fb->mmu_wr);
if (ret)
return ret;
return 0;
}
void
gf100_fb_init(struct nvkm_fb *base)
{
@ -98,6 +123,7 @@ gf100_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device,
static const struct nvkm_fb_func
gf100_fb = {
.dtor = gf100_fb_dtor,
.oneinit = gf100_fb_oneinit,
.init = gf100_fb_init,
.intr = gf100_fb_intr,
.ram_new = gf100_ram_new,

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c
View File

@ -27,6 +27,7 @@
static const struct nvkm_fb_func
gk104_fb = {
.dtor = gf100_fb_dtor,
.oneinit = gf100_fb_oneinit,
.init = gf100_fb_init,
.intr = gf100_fb_intr,
.ram_new = gk104_ram_new,

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
View File

@ -30,6 +30,7 @@ gk20a_fb_init(struct nvkm_fb *fb)
static const struct nvkm_fb_func
gk20a_fb = {
.oneinit = gf100_fb_oneinit,
.init = gk20a_fb_init,
.memtype_valid = gf100_fb_memtype_valid,
};

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
View File

@ -27,6 +27,7 @@
static const struct nvkm_fb_func
gm107_fb = {
.dtor = gf100_fb_dtor,
.oneinit = gf100_fb_oneinit,
.init = gf100_fb_init,
.intr = gf100_fb_intr,
.ram_new = gm107_ram_new,

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
View File

@ -59,5 +59,6 @@ void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
int gf100_fb_oneinit(struct nvkm_fb *);
bool gf100_fb_memtype_valid(struct nvkm_fb *, u32);
#endif