forked from Minki/linux
cirrusfb: check_var improvements
Break cirrusfb_decode_var() function into two parts: cirrusfb_check_pixclock() which can be called from the cirrusfb_check_var() aand merge rest into the cirrusfb_set_par_foo(). This allows rejecting modes with too high pixclock before before any change to hardware state (and a console is messed up). Also, fix RGB field's lengths for 8bpp modes to correct ones so X11 works with fbdev driver with cirrusfb. Kill some redundant function calls or register loads. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Helt
Linus Torvalds
parent
1b48cb563d
commit
99a4584752
@ -432,6 +432,53 @@ static int cirrusfb_check_mclk(struct fb_info *info, long freq)
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return 0;
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}
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static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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long freq;
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long maxclock;
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struct cirrusfb_info *cinfo = info->par;
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unsigned maxclockidx = var->bits_per_pixel >> 3;
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/* convert from ps to kHz */
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freq = PICOS2KHZ(var->pixclock);
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dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
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maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
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cinfo->multiplexing = 0;
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/* If the frequency is greater than we can support, we might be able
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* to use multiplexing for the video mode */
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if (freq > maxclock) {
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switch (cinfo->btype) {
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case BT_ALPINE:
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case BT_GD5480:
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cinfo->multiplexing = 1;
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break;
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default:
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dev_err(info->device,
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"Frequency greater than maxclock (%ld kHz)\n",
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maxclock);
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return -EINVAL;
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}
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}
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#if 0
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/* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
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* the VCLK is double the pixel clock. */
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switch (var->bits_per_pixel) {
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case 16:
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case 32:
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if (var->xres <= 800)
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/* Xbh has this type of clock for 32-bit */
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freq /= 2;
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break;
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}
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#endif
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return 0;
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}
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static int cirrusfb_check_var(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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@ -449,7 +496,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
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case 8:
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var->red.offset = 0;
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var->red.length = 6;
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var->red.length = 8;
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var->green = var->red;
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var->blue = var->red;
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break;
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@ -513,7 +560,6 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
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return -EINVAL;
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}
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if (var->xoffset < 0)
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var->xoffset = 0;
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if (var->yoffset < 0)
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@ -544,80 +590,9 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
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return -EINVAL;
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}
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return 0;
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}
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if (cirrusfb_check_pixclock(var, info))
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return -EINVAL;
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static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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long freq;
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long maxclock;
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int maxclockidx = var->bits_per_pixel >> 3;
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struct cirrusfb_info *cinfo = info->par;
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switch (var->bits_per_pixel) {
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case 1:
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info->fix.line_length = var->xres_virtual / 8;
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info->fix.visual = FB_VISUAL_MONO10;
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break;
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case 8:
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info->fix.line_length = var->xres_virtual;
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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break;
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case 16:
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case 32:
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info->fix.line_length = var->xres_virtual * maxclockidx;
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info->fix.visual = FB_VISUAL_TRUECOLOR;
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break;
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default:
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dev_dbg(info->device,
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"Unsupported bpp size: %d\n", var->bits_per_pixel);
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assert(false);
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/* should never occur */
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break;
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}
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info->fix.type = FB_TYPE_PACKED_PIXELS;
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/* convert from ps to kHz */
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freq = PICOS2KHZ(var->pixclock);
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dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
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maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
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cinfo->multiplexing = 0;
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/* If the frequency is greater than we can support, we might be able
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* to use multiplexing for the video mode */
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if (freq > maxclock) {
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switch (cinfo->btype) {
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case BT_ALPINE:
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case BT_GD5480:
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cinfo->multiplexing = 1;
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break;
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default:
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dev_err(info->device,
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"Frequency greater than maxclock (%ld kHz)\n",
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maxclock);
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return -EINVAL;
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}
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}
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#if 0
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/* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
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* the VCLK is double the pixel clock. */
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switch (var->bits_per_pixel) {
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case 16:
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case 32:
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if (var->xres <= 800)
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/* Xbh has this type of clock for 32-bit */
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freq /= 2;
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break;
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}
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#endif
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return 0;
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}
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@ -653,7 +628,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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struct fb_var_screeninfo *var = &info->var;
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u8 __iomem *regbase = cinfo->regbase;
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unsigned char tmp;
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int err;
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int pitch;
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const struct cirrusfb_board_info_rec *bi;
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int hdispend, hsyncstart, hsyncend, htotal;
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@ -664,17 +638,29 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
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var->xres, var->yres, var->bits_per_pixel);
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dev_dbg(info->device, "pixclock: %d\n", var->pixclock);
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switch (var->bits_per_pixel) {
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case 1:
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info->fix.line_length = var->xres_virtual / 8;
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info->fix.visual = FB_VISUAL_MONO10;
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break;
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case 8:
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info->fix.line_length = var->xres_virtual;
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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break;
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case 16:
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case 32:
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info->fix.line_length = var->xres_virtual *
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var->bits_per_pixel >> 3;
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info->fix.visual = FB_VISUAL_TRUECOLOR;
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break;
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}
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info->fix.type = FB_TYPE_PACKED_PIXELS;
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init_vgachip(info);
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err = cirrusfb_decode_var(var, info);
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if (err) {
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/* should never happen */
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dev_dbg(info->device, "mode change aborted. invalid var.\n");
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return -EINVAL;
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}
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bi = &cirrusfb_board_info[cinfo->btype];
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hsyncstart = var->xres + var->right_margin;
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@ -873,9 +859,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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* address wrap, no compat. */
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vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
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/* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
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* previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
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/* don't know if it would hurt to also program this if no interlaced */
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/* mode is used, but I feel better this way.. :-) */
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if (var->vmode & FB_VMODE_INTERLACED)
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@ -883,8 +866,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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else
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vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
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vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
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/* adjust horizontal/vertical sync type (low/high) */
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/* enable display memory & CRTC I/O address for color mode */
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tmp = 0x03;
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@ -896,8 +877,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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tmp |= 0xc;
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WGen(cinfo, VGA_MIS_W, tmp);
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/* Screen A Preset Row-Scan register */
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vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
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/* text cursor on and start line */
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vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
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/* text cursor end line */
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@ -1248,7 +1227,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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dev_dbg(info->device, "CRT1e: %d\n", tmp);
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}
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/* pixel panning */
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vga_wattr(regbase, CL_AR33, 0);
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@ -1274,9 +1252,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
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dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
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/* pan to requested offset */
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cirrusfb_pan_display(var, info);
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#ifdef CIRRUSFB_DEBUG
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cirrusfb_dbg_reg_dump(info, NULL);
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#endif
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@ -1332,8 +1307,7 @@ static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
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static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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int xoffset = 0;
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int yoffset = 0;
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int xoffset;
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unsigned long base;
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unsigned char tmp, xpix;
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struct cirrusfb_info *cinfo = info->par;
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@ -1347,9 +1321,8 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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return -EINVAL;
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xoffset = var->xoffset * info->var.bits_per_pixel / 8;
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yoffset = var->yoffset;
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base = yoffset * info->fix.line_length + xoffset;
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base = var->yoffset * info->fix.line_length + xoffset;
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if (info->var.bits_per_pixel == 1) {
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/* base is already correct */
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@ -1363,10 +1336,8 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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cirrusfb_WaitBLT(cinfo->regbase);
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/* lower 8 + 8 bits of screen start address */
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
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(unsigned char) (base & 0xff));
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
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(unsigned char) (base >> 8));
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
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/* 0xf2 is %11110010, exclude tmp bits */
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tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
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@ -1544,10 +1515,6 @@ static void init_vgachip(struct fb_info *info)
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/* FullBandwidth (video off) and 8/9 dot clock */
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vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
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/* polarity (-/-), disable access to display memory,
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* VGA_CRTC_START_HI base address: color
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*/
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WGen(cinfo, VGA_MIS_W, 0xc1);
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/* "magic cookie" - doesn't make any sense to me.. */
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/* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
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@ -1614,10 +1581,6 @@ static void init_vgachip(struct fb_info *info)
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vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
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/* Text cursor end: - */
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vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
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/* Screen start address high: 0 */
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
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/* Screen start address low: 0 */
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
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/* text cursor location high: 0 */
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vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
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/* text cursor location low: 0 */
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@ -1625,10 +1588,6 @@ static void init_vgachip(struct fb_info *info)
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/* Underline Row scanline: - */
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vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
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/* mode control: timing enable, byte mode, no compat modes */
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vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
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/* Line Compare: not needed */
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vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
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/* ### add 0x40 for text modes with > 30 MHz pixclock */
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/* ext. display controls: ext.adr. wrap */
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vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
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@ -1697,12 +1656,6 @@ static void init_vgachip(struct fb_info *info)
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WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
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if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
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/* polarity (-/-), enable display mem,
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* VGA_CRTC_START_HI i/o base = color
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*/
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WGen(cinfo, VGA_MIS_W, 0xc3);
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/* BLT Start/status: Blitter reset */
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vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
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/* - " - : "end-of-reset" */
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@ -2052,7 +2005,7 @@ static int __devinit cirrusfb_register(struct fb_info *info)
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info->var.activate = FB_ACTIVATE_NOW;
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err = cirrusfb_decode_var(&info->var, info);
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err = cirrusfb_check_var(&info->var, info);
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if (err < 0) {
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/* should never happen */
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dev_dbg(info->device,
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