forked from Minki/linux
tg3: Eliminate tg3_halt_cpu() prototype
This patch moves the implementatino of tg3_halt_cpu() earlier in the file to eliminate its prototype. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
fd6d3f0ec7
commit
997b4f135b
@ -2999,6 +2999,228 @@ static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
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return res;
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return res;
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}
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}
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#define RX_CPU_SCRATCH_BASE 0x30000
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#define RX_CPU_SCRATCH_SIZE 0x04000
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#define TX_CPU_SCRATCH_BASE 0x34000
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#define TX_CPU_SCRATCH_SIZE 0x04000
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/* tp->lock is held. */
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static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
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{
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int i;
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BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 val = tr32(GRC_VCPU_EXT_CTRL);
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tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
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return 0;
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}
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if (offset == RX_CPU_BASE) {
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for (i = 0; i < 10000; i++) {
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32(offset + CPU_MODE, CPU_MODE_HALT);
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if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
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break;
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}
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
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udelay(10);
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} else {
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for (i = 0; i < 10000; i++) {
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32(offset + CPU_MODE, CPU_MODE_HALT);
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if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
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break;
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}
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}
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if (i >= 10000) {
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netdev_err(tp->dev, "%s timed out, %s CPU\n",
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__func__, offset == RX_CPU_BASE ? "RX" : "TX");
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return -ENODEV;
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}
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/* Clear firmware's nvram arbitration. */
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if (tg3_flag(tp, NVRAM))
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tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
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return 0;
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}
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struct fw_info {
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unsigned int fw_base;
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unsigned int fw_len;
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const __be32 *fw_data;
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};
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/* tp->lock is held. */
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static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
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u32 cpu_scratch_base, int cpu_scratch_size,
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struct fw_info *info)
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{
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int err, lock_err, i;
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void (*write_op)(struct tg3 *, u32, u32);
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if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
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netdev_err(tp->dev,
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"%s: Trying to load TX cpu firmware which is 5705\n",
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__func__);
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return -EINVAL;
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}
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if (tg3_flag(tp, 5705_PLUS))
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write_op = tg3_write_mem;
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else
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write_op = tg3_write_indirect_reg32;
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/* It is possible that bootcode is still loading at this point.
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* Get the nvram lock first before halting the cpu.
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*/
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lock_err = tg3_nvram_lock(tp);
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err = tg3_halt_cpu(tp, cpu_base);
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if (!lock_err)
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tg3_nvram_unlock(tp);
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if (err)
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goto out;
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for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
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write_op(tp, cpu_scratch_base + i, 0);
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tw32(cpu_base + CPU_STATE, 0xffffffff);
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tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
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for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
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write_op(tp, (cpu_scratch_base +
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(info->fw_base & 0xffff) +
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(i * sizeof(u32))),
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be32_to_cpu(info->fw_data[i]));
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err = 0;
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out:
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return err;
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}
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/* tp->lock is held. */
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static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
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{
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struct fw_info info;
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const __be32 *fw_data;
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int err, i;
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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start address and length. We are setting complete length.
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length = end_address_of_bss - start_address_of_text.
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Remainder is the blob to be loaded contiguously
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from start address. */
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info.fw_base = be32_to_cpu(fw_data[1]);
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info.fw_len = tp->fw->size - 12;
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info.fw_data = &fw_data[3];
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err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
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RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
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&info);
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if (err)
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return err;
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err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
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TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
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&info);
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if (err)
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return err;
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/* Now startup only the RX cpu. */
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tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
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tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
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for (i = 0; i < 5; i++) {
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if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
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break;
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tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
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tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
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tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
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udelay(1000);
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}
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if (i >= 5) {
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netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
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"should be %08x\n", __func__,
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tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
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return -ENODEV;
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}
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tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
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tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
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return 0;
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}
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/* tp->lock is held. */
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static int tg3_load_tso_firmware(struct tg3 *tp)
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{
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struct fw_info info;
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const __be32 *fw_data;
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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if (tg3_flag(tp, HW_TSO_1) ||
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tg3_flag(tp, HW_TSO_2) ||
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tg3_flag(tp, HW_TSO_3))
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return 0;
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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start address and length. We are setting complete length.
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length = end_address_of_bss - start_address_of_text.
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Remainder is the blob to be loaded contiguously
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from start address. */
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info.fw_base = be32_to_cpu(fw_data[1]);
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cpu_scratch_size = tp->fw_len;
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info.fw_len = tp->fw->size - 12;
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info.fw_data = &fw_data[3];
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
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cpu_base = RX_CPU_BASE;
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cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
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} else {
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cpu_base = TX_CPU_BASE;
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cpu_scratch_base = TX_CPU_SCRATCH_BASE;
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cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
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}
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err = tg3_load_firmware_cpu(tp, cpu_base,
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cpu_scratch_base, cpu_scratch_size,
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&info);
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if (err)
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return err;
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/* Now startup the cpu. */
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tw32(cpu_base + CPU_STATE, 0xffffffff);
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tw32_f(cpu_base + CPU_PC, info.fw_base);
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for (i = 0; i < 5; i++) {
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if (tr32(cpu_base + CPU_PC) == info.fw_base)
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break;
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tw32(cpu_base + CPU_STATE, 0xffffffff);
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tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
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tw32_f(cpu_base + CPU_PC, info.fw_base);
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udelay(1000);
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}
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if (i >= 5) {
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netdev_err(tp->dev,
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"%s fails to set CPU PC, is %08x should be %08x\n",
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__func__, tr32(cpu_base + CPU_PC), info.fw_base);
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return -ENODEV;
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}
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tw32(cpu_base + CPU_STATE, 0xffffffff);
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tw32_f(cpu_base + CPU_MODE, 0x00000000);
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return 0;
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}
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/* tp->lock is held. */
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/* tp->lock is held. */
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static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
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static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
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{
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{
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@ -7707,227 +7929,6 @@ static int tg3_halt(struct tg3 *tp, int kind, int silent)
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return 0;
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return 0;
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}
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}
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#define RX_CPU_SCRATCH_BASE 0x30000
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#define RX_CPU_SCRATCH_SIZE 0x04000
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#define TX_CPU_SCRATCH_BASE 0x34000
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#define TX_CPU_SCRATCH_SIZE 0x04000
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/* tp->lock is held. */
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static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
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{
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int i;
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BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 val = tr32(GRC_VCPU_EXT_CTRL);
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tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
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return 0;
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}
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if (offset == RX_CPU_BASE) {
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for (i = 0; i < 10000; i++) {
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32(offset + CPU_MODE, CPU_MODE_HALT);
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if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
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break;
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}
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
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udelay(10);
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} else {
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for (i = 0; i < 10000; i++) {
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32(offset + CPU_MODE, CPU_MODE_HALT);
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if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
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break;
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}
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}
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if (i >= 10000) {
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netdev_err(tp->dev, "%s timed out, %s CPU\n",
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__func__, offset == RX_CPU_BASE ? "RX" : "TX");
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return -ENODEV;
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}
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/* Clear firmware's nvram arbitration. */
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if (tg3_flag(tp, NVRAM))
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tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
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return 0;
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}
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struct fw_info {
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unsigned int fw_base;
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unsigned int fw_len;
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const __be32 *fw_data;
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};
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/* tp->lock is held. */
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static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
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int cpu_scratch_size, struct fw_info *info)
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{
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int err, lock_err, i;
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void (*write_op)(struct tg3 *, u32, u32);
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if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
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netdev_err(tp->dev,
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"%s: Trying to load TX cpu firmware which is 5705\n",
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__func__);
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return -EINVAL;
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}
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if (tg3_flag(tp, 5705_PLUS))
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write_op = tg3_write_mem;
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else
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write_op = tg3_write_indirect_reg32;
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/* It is possible that bootcode is still loading at this point.
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* Get the nvram lock first before halting the cpu.
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*/
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lock_err = tg3_nvram_lock(tp);
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err = tg3_halt_cpu(tp, cpu_base);
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if (!lock_err)
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tg3_nvram_unlock(tp);
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if (err)
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goto out;
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for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
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write_op(tp, cpu_scratch_base + i, 0);
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tw32(cpu_base + CPU_STATE, 0xffffffff);
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tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
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for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
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write_op(tp, (cpu_scratch_base +
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(info->fw_base & 0xffff) +
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(i * sizeof(u32))),
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be32_to_cpu(info->fw_data[i]));
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err = 0;
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out:
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return err;
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}
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/* tp->lock is held. */
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static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
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{
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struct fw_info info;
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const __be32 *fw_data;
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int err, i;
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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start address and length. We are setting complete length.
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length = end_address_of_bss - start_address_of_text.
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Remainder is the blob to be loaded contiguously
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from start address. */
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info.fw_base = be32_to_cpu(fw_data[1]);
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info.fw_len = tp->fw->size - 12;
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info.fw_data = &fw_data[3];
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err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
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RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
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&info);
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if (err)
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return err;
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|
||||||
err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
|
|
||||||
TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
|
|
||||||
&info);
|
|
||||||
if (err)
|
|
||||||
return err;
|
|
||||||
|
|
||||||
/* Now startup only the RX cpu. */
|
|
||||||
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
|
|
||||||
tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
|
|
||||||
|
|
||||||
for (i = 0; i < 5; i++) {
|
|
||||||
if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
|
|
||||||
break;
|
|
||||||
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
|
|
||||||
tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
|
|
||||||
tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
|
|
||||||
udelay(1000);
|
|
||||||
}
|
|
||||||
if (i >= 5) {
|
|
||||||
netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
|
|
||||||
"should be %08x\n", __func__,
|
|
||||||
tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
|
|
||||||
tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* tp->lock is held. */
|
|
||||||
static int tg3_load_tso_firmware(struct tg3 *tp)
|
|
||||||
{
|
|
||||||
struct fw_info info;
|
|
||||||
const __be32 *fw_data;
|
|
||||||
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
|
|
||||||
int err, i;
|
|
||||||
|
|
||||||
if (tg3_flag(tp, HW_TSO_1) ||
|
|
||||||
tg3_flag(tp, HW_TSO_2) ||
|
|
||||||
tg3_flag(tp, HW_TSO_3))
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
fw_data = (void *)tp->fw->data;
|
|
||||||
|
|
||||||
/* Firmware blob starts with version numbers, followed by
|
|
||||||
start address and length. We are setting complete length.
|
|
||||||
length = end_address_of_bss - start_address_of_text.
|
|
||||||
Remainder is the blob to be loaded contiguously
|
|
||||||
from start address. */
|
|
||||||
|
|
||||||
info.fw_base = be32_to_cpu(fw_data[1]);
|
|
||||||
cpu_scratch_size = tp->fw_len;
|
|
||||||
info.fw_len = tp->fw->size - 12;
|
|
||||||
info.fw_data = &fw_data[3];
|
|
||||||
|
|
||||||
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
|
|
||||||
cpu_base = RX_CPU_BASE;
|
|
||||||
cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
|
|
||||||
} else {
|
|
||||||
cpu_base = TX_CPU_BASE;
|
|
||||||
cpu_scratch_base = TX_CPU_SCRATCH_BASE;
|
|
||||||
cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
|
|
||||||
}
|
|
||||||
|
|
||||||
err = tg3_load_firmware_cpu(tp, cpu_base,
|
|
||||||
cpu_scratch_base, cpu_scratch_size,
|
|
||||||
&info);
|
|
||||||
if (err)
|
|
||||||
return err;
|
|
||||||
|
|
||||||
/* Now startup the cpu. */
|
|
||||||
tw32(cpu_base + CPU_STATE, 0xffffffff);
|
|
||||||
tw32_f(cpu_base + CPU_PC, info.fw_base);
|
|
||||||
|
|
||||||
for (i = 0; i < 5; i++) {
|
|
||||||
if (tr32(cpu_base + CPU_PC) == info.fw_base)
|
|
||||||
break;
|
|
||||||
tw32(cpu_base + CPU_STATE, 0xffffffff);
|
|
||||||
tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
|
|
||||||
tw32_f(cpu_base + CPU_PC, info.fw_base);
|
|
||||||
udelay(1000);
|
|
||||||
}
|
|
||||||
if (i >= 5) {
|
|
||||||
netdev_err(tp->dev,
|
|
||||||
"%s fails to set CPU PC, is %08x should be %08x\n",
|
|
||||||
__func__, tr32(cpu_base + CPU_PC), info.fw_base);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
tw32(cpu_base + CPU_STATE, 0xffffffff);
|
|
||||||
tw32_f(cpu_base + CPU_MODE, 0x00000000);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static int tg3_set_mac_addr(struct net_device *dev, void *p)
|
static int tg3_set_mac_addr(struct net_device *dev, void *p)
|
||||||
{
|
{
|
||||||
struct tg3 *tp = netdev_priv(dev);
|
struct tg3 *tp = netdev_priv(dev);
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user