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drm/nouveau/xtensa: convert to new-style nvkm_engine

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:21 +10:00
parent 53e60da43a
commit 98b20c9ab8
8 changed files with 87 additions and 151 deletions
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2
drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
View File

@ -1,5 +1,5 @@
#ifndef __NVKM_BSP_H__
#define __NVKM_BSP_H__
#include <engine/xtensa.h>
extern struct nvkm_oclass g84_bsp_oclass;
int g84_bsp_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif

2
drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
View File

@ -1,5 +1,5 @@
#ifndef __NVKM_VP_H__
#define __NVKM_VP_H__
#include <engine/xtensa.h>
extern struct nvkm_oclass g84_vp_oclass;
int g84_vp_new(struct nvkm_device *, int, struct nvkm_engine **);
#endif

26
drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
View File

@ -4,30 +4,20 @@
#include <core/engine.h>
struct nvkm_xtensa {
struct nvkm_engine engine;
const struct nvkm_xtensa_func *func;
u32 addr;
struct nvkm_engine engine;
struct nvkm_memory *gpu_fw;
u32 fifo_val;
u32 unkd28;
};
int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *,
int index, bool enable, u32 addr, struct nvkm_engine **);
struct nvkm_xtensa_func {
void (*init)(struct nvkm_xtensa *);
u32 pmc_enable;
u32 fifo_val;
u32 unkd28;
struct nvkm_sclass sclass[];
};
#define nvkm_xtensa_create(p,e,c,b,d,i,f,r) \
nvkm_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \
sizeof(**r),(void **)r)
int nvkm_xtensa_create_(struct nvkm_object *,
struct nvkm_object *,
struct nvkm_oclass *, u32, bool,
const char *, const char *,
int, void **);
#define _nvkm_xtensa_dtor _nvkm_engine_dtor
int _nvkm_xtensa_init(struct nvkm_object *);
int _nvkm_xtensa_fini(struct nvkm_object *, bool);
#endif

38
drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
View File

@ -26,41 +26,19 @@
#include <nvif/class.h>
static const struct nvkm_xtensa_func
g84_bsp_func = {
g84_bsp = {
.pmc_enable = 0x04008000,
.fifo_val = 0x1111,
.unkd28 = 0x90044,
.sclass = {
{ -1, -1, NV74_BSP },
{}
}
};
static int
g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
int
g84_bsp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine)
{
struct nvkm_xtensa *bsp;
int ret;
ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true,
"PBSP", "bsp", &bsp);
*pobject = nv_object(bsp);
if (ret)
return ret;
bsp->func = &g84_bsp_func;
nv_subdev(bsp)->unit = 0x04008000;
bsp->fifo_val = 0x1111;
bsp->unkd28 = 0x90044;
return 0;
return nvkm_xtensa_new_(&g84_bsp, device, index,
true, 0x103000, pengine);
}
struct nvkm_oclass
g84_bsp_oclass = {
.handle = NV_ENGINE(BSP, 0x84),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = g84_bsp_ctor,
.dtor = _nvkm_xtensa_dtor,
.init = _nvkm_xtensa_init,
.fini = _nvkm_xtensa_fini,
},
};

24
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -897,7 +897,7 @@ nv84_chipset = {
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
.bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
// .dma = nv50_dma_new,
@ -906,7 +906,7 @@ nv84_chipset = {
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
.vp = g84_vp_new,
};
static const struct nvkm_device_chip
@ -928,7 +928,7 @@ nv86_chipset = {
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
.bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
// .dma = nv50_dma_new,
@ -937,7 +937,7 @@ nv86_chipset = {
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
.vp = g84_vp_new,
};
static const struct nvkm_device_chip
@ -959,7 +959,7 @@ nv92_chipset = {
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
.bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
// .dma = nv50_dma_new,
@ -968,7 +968,7 @@ nv92_chipset = {
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
.vp = g84_vp_new,
};
static const struct nvkm_device_chip
@ -990,7 +990,7 @@ nv94_chipset = {
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
.bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
@ -999,7 +999,7 @@ nv94_chipset = {
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
.vp = g84_vp_new,
};
static const struct nvkm_device_chip
@ -1026,9 +1026,9 @@ nv96_chipset = {
// .sw = nv50_sw_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .vp = g84_vp_new,
.vp = g84_vp_new,
// .cipher = g84_cipher_new,
// .bsp = g84_bsp_new,
.bsp = g84_bsp_new,
// .disp = g94_disp_new,
// .pm = g84_pm_new,
};
@ -1083,7 +1083,7 @@ nva0_chipset = {
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .bsp = g84_bsp_new,
.bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = gt200_disp_new,
// .dma = nv50_dma_new,
@ -1092,7 +1092,7 @@ nva0_chipset = {
// .mpeg = g84_mpeg_new,
// .pm = gt200_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
.vp = g84_vp_new,
};
static const struct nvkm_device_chip

12
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -42,9 +42,7 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
@ -54,9 +52,7 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
@ -66,9 +62,7 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
@ -78,9 +72,7 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
@ -90,9 +82,7 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
@ -110,9 +100,7 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;

38
drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
View File

@ -26,41 +26,19 @@
#include <nvif/class.h>
static const struct nvkm_xtensa_func
g84_vp_func = {
g84_vp = {
.pmc_enable = 0x01020000,
.fifo_val = 0x111,
.unkd28 = 0x9c544,
.sclass = {
{ -1, -1, NV74_VP2 },
{}
}
};
static int
g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
int
g84_vp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine)
{
struct nvkm_xtensa *vp;
int ret;
ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true,
"PVP", "vp", &vp);
*pobject = nv_object(vp);
if (ret)
return ret;
vp->func = &g84_vp_func;
nv_subdev(vp)->unit = 0x01020000;
vp->fifo_val = 0x111;
vp->unkd28 = 0x9c544;
return 0;
return nvkm_xtensa_new_(&g84_vp, device, index,
true, 0x00f000, pengine);
}
struct nvkm_oclass
g84_vp_oclass = {
.handle = NV_ENGINE(VP, 0x84),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = g84_vp_ctor,
.dtor = _nvkm_xtensa_dtor,
.init = _nvkm_xtensa_init,
.fini = _nvkm_xtensa_fini,
},
};

96
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
View File

@ -51,11 +51,12 @@ nvkm_xtensa_cclass = {
.bind = nvkm_xtensa_cclass_bind,
};
void
_nvkm_xtensa_intr(struct nvkm_subdev *subdev)
static void
nvkm_xtensa_intr(struct nvkm_engine *engine)
{
struct nvkm_xtensa *xtensa = (void *)subdev;
struct nvkm_device *device = xtensa->engine.subdev.device;
struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
struct nvkm_subdev *subdev = &xtensa->engine.subdev;
struct nvkm_device *device = subdev->device;
const u32 base = xtensa->addr;
u32 unk104 = nvkm_rd32(device, base + 0xd04);
u32 intr = nvkm_rd32(device, base + 0xc20);
@ -68,41 +69,29 @@ _nvkm_xtensa_intr(struct nvkm_subdev *subdev)
intr = nvkm_rd32(device, base + 0xc20);
if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) {
nvkm_debug(subdev, "Enabling FIFO_CTRL\n");
nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->fifo_val);
nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->func->fifo_val);
}
}
static const struct nvkm_engine_func
nvkm_xtensa = {
.fifo.sclass = nvkm_xtensa_oclass_get,
.cclass = &nvkm_xtensa_cclass,
};
int
nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, u32 addr, bool enable,
const char *iname, const char *fname,
int length, void **pobject)
static int
nvkm_xtensa_fini(struct nvkm_engine *engine, bool suspend)
{
struct nvkm_xtensa *xtensa;
int ret;
struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
struct nvkm_device *device = xtensa->engine.subdev.device;
const u32 base = xtensa->addr;
ret = nvkm_engine_create_(parent, engine, oclass, enable, iname,
fname, length, pobject);
xtensa = *pobject;
if (ret)
return ret;
nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */
nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */
xtensa->engine.subdev.intr = _nvkm_xtensa_intr;
xtensa->engine.func = &nvkm_xtensa;
xtensa->addr = addr;
if (!suspend)
nvkm_memory_del(&xtensa->gpu_fw);
return 0;
}
int
_nvkm_xtensa_init(struct nvkm_object *object)
static int
nvkm_xtensa_init(struct nvkm_engine *engine)
{
struct nvkm_xtensa *xtensa = (void *)object;
struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
struct nvkm_subdev *subdev = &xtensa->engine.subdev;
struct nvkm_device *device = subdev->device;
const u32 base = xtensa->addr;
@ -112,10 +101,6 @@ _nvkm_xtensa_init(struct nvkm_object *object)
u64 addr, size;
u32 tmp;
ret = nvkm_engine_init_old(&xtensa->engine);
if (ret)
return ret;
if (!xtensa->gpu_fw) {
snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x",
xtensa->addr >> 12);
@ -153,7 +138,7 @@ _nvkm_xtensa_init(struct nvkm_object *object)
nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */
nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */
nvkm_wr32(device, base + 0xd28, xtensa->unkd28); /* ?? */
nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */
nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */
nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */
@ -171,18 +156,35 @@ _nvkm_xtensa_init(struct nvkm_object *object)
return 0;
}
int
_nvkm_xtensa_fini(struct nvkm_object *object, bool suspend)
static void *
nvkm_xtensa_dtor(struct nvkm_engine *engine)
{
struct nvkm_xtensa *xtensa = (void *)object;
struct nvkm_device *device = xtensa->engine.subdev.device;
const u32 base = xtensa->addr;
nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */
nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */
if (!suspend)
nvkm_memory_del(&xtensa->gpu_fw);
return nvkm_engine_fini_old(&xtensa->engine, suspend);
return nvkm_xtensa(engine);
}
static const struct nvkm_engine_func
nvkm_xtensa = {
.dtor = nvkm_xtensa_dtor,
.init = nvkm_xtensa_init,
.fini = nvkm_xtensa_fini,
.intr = nvkm_xtensa_intr,
.fifo.sclass = nvkm_xtensa_oclass_get,
.cclass = &nvkm_xtensa_cclass,
};
int
nvkm_xtensa_new_(const struct nvkm_xtensa_func *func,
struct nvkm_device *device, int index, bool enable,
u32 addr, struct nvkm_engine **pengine)
{
struct nvkm_xtensa *xtensa;
if (!(xtensa = kzalloc(sizeof(*xtensa), GFP_KERNEL)))
return -ENOMEM;
xtensa->func = func;
xtensa->addr = addr;
*pengine = &xtensa->engine;
return nvkm_engine_ctor(&nvkm_xtensa, device, index, func->pmc_enable,
enable, &xtensa->engine);
}