Qualcomm ARM64 Updates for v5.2 - Part 2
* Add ADC temp for temp alarm node on PM8998 * Add ref clks for DSI PHYs on SDM845 and MSM8916 * Add CPU capacity and topology on SDM845 * Add display and gpu related nodes on MSM8996 * Add sound and hdmi display support on DB820C * Fixup thermal nodes on MSM8998 platform -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJcwoc2AAoJEFKiBbHx2RXV79sP/1l5EzWuFvypYASL+GTO7p2V VUdsg6LQIniM1+A3WbYfHHX6gaydbd/M1fzt4gbK7bMcCfMkIkC5awvORjYF723n LohxsAv0VVSEYZQBO6cPyP0TYPrUaIvtyjuazXHVJ+sdoapkuX6n8/nlsiBtqrAs 3gsH3CHYLkDH2OZdUqwiMmksXjg15sXCiCrGgygNYISyV43tujPDBCy5632RF14j AHqL0WdyqJE5CxTJ70I9jZis4x0Ramj56fdhjue6zOZ8uGEcXgBezOyao8T8CpxK cbl9KhYDQBHK+DC991lzEJsqYrup+xeZ1P+PI7HVILYogcyjRa8ZvnKQ3DXimhSW 6bUWKjsDmONMiKFXZDsDFnZYrOIH2gdd2q+Ve4J++zeGahqn3MbL1JxFBCgKnQ+S dAWgk/iSazbwrqxRcpkn4SsRsrdFxBVMWMWU3OVTgcDV/6wHATcCMqW114djlYMJ jNU9JiqHFntDX/WRu8ZIVGxv7qPhD0DL1w0NK+5gPofnfGasDjMppaH058xHJqPO 9F8+zaKljzoIzXiEyk2j/VimFuL6caLI7kv0Qi1WC0hAA1oJ8ZzPMe8eWCnFuG22 Ldn/Dr3iKIzv8L3x03EIA1raNB6sMhSZgb7IEFb7CC8QJ3BjeDR2izTnDk5kIKWO 14/sVe2utNiUOBZr9u2r =99VN -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt Qualcomm ARM64 Updates for v5.2 - Part 2 * Add ADC temp for temp alarm node on PM8998 * Add ref clks for DSI PHYs on SDM845 and MSM8916 * Add CPU capacity and topology on SDM845 * Add display and gpu related nodes on MSM8996 * Add sound and hdmi display support on DB820C * Fixup thermal nodes on MSM8998 platform * tag 'qcom-arm64-for-5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20 arm64: dts: msm8998: thermal: Fix number of supported sensors arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones arm64: dts: db820c: Add sound card support arm64: dts: apq8096-db820c: Add HDMI display support arm64: dts: Add Adreno GPU definitions arm64: qcom: msm8996.dtsi: Add Display nodes arm64: dts: msm8996: Add display smmu node arm64: dts: msm8996: Add graphics smmu node arm64: dts: sdm845: Add CPU capacity values arm64: dts: sdm845: Add CPU topology arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY arm64: dts: qcom: pm8998: Use ADC temperature to temp-alarm node Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
97fc172d86
@ -62,4 +62,56 @@
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bias-disable;
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};
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};
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hdmi_hpd_active: hdmi_hpd_active {
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mux {
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pins = "gpio34";
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function = "hdmi_hot";
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};
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config {
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pins = "gpio34";
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bias-pull-down;
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drive-strength = <16>;
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};
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};
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hdmi_hpd_suspend: hdmi_hpd_suspend {
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mux {
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pins = "gpio34";
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function = "hdmi_hot";
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};
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config {
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pins = "gpio34";
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bias-pull-down;
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drive-strength = <2>;
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};
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};
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hdmi_ddc_active: hdmi_ddc_active {
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mux {
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pins = "gpio32", "gpio33";
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function = "hdmi_ddc";
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};
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config {
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pins = "gpio32", "gpio33";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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hdmi_ddc_suspend: hdmi_ddc_suspend {
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mux {
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pins = "gpio32", "gpio33";
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function = "hdmi_ddc";
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};
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config {
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pins = "gpio32", "gpio33";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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@ -36,6 +36,14 @@
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};
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};
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audio_mclk: clk_div1 {
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pinconf {
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pins = "gpio15";
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function = "func1";
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power-source = <PM8994_GPIO_S4>; // 1.8V
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};
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};
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volume_up_gpio: pm8996_gpio2 {
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pinconf {
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pins = "gpio2";
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@ -18,6 +18,8 @@
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#include "apq8096-db820c-pmic-pins.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/sound/qcom,q6afe.h>
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#include <dt-bindings/sound/qcom,q6asm.h>
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/*
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* GPIO name legend: proper name = the GPIO line is used as GPIO
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@ -63,6 +65,7 @@
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};
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clocks {
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compatible = "simple-bus";
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divclk4: divclk4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@ -72,6 +75,15 @@
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pinctrl-names = "default";
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pinctrl-0 = <&divclk4_pin_a>;
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};
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div1_mclk: divclk1 {
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compatible = "gpio-gate-clock";
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pinctrl-0 = <&audio_mclk>;
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pinctrl-names = "default";
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clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
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#clock-cells = <0>;
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enable-gpios = <&pm8994_gpios 15 0>;
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};
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};
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soc {
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@ -452,6 +464,43 @@
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perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
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};
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};
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slim_msm: slim@91c0000 {
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ngd@1 {
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wcd9335: codec@1{
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clock-names = "mclk", "slimbus";
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clocks = <&div1_mclk>,
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<&rpmcc RPM_SMD_BB_CLK1>;
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};
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};
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};
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mdss@900000 {
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status = "okay";
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mdp@901000 {
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status = "okay";
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};
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hdmi-phy@9a0600 {
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status = "okay";
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vddio-supply = <&pm8994_l12>;
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vcca-supply = <&pm8994_l28>;
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#phy-cells = <0>;
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};
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hdmi-tx@9a0000 {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
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pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
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core-vdda-supply = <&pm8994_l12>;
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core-vcc-supply = <&pm8994_s4>;
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};
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};
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};
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@ -639,3 +688,75 @@
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};
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};
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};
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&sound {
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compatible = "qcom,apq8096-sndcard";
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model = "DB820c";
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audio-routing = "RX_BIAS", "MCLK";
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mm1-dai-link {
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link-name = "MultiMedia1";
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cpu {
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sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
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};
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};
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mm2-dai-link {
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link-name = "MultiMedia2";
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cpu {
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sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
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};
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};
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mm3-dai-link {
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link-name = "MultiMedia3";
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cpu {
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sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
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};
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};
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hdmi-dai-link {
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link-name = "HDMI";
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cpu {
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sound-dai = <&q6afedai HDMI_RX>;
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};
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platform {
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sound-dai = <&q6routing>;
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};
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codec {
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sound-dai = <&hdmi 0>;
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};
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};
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slim-dai-link {
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link-name = "SLIM Playback";
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cpu {
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sound-dai = <&q6afedai SLIMBUS_6_RX>;
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};
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platform {
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sound-dai = <&q6routing>;
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};
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codec {
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sound-dai = <&wcd9335 6>;
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};
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};
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slimcap-dai-link {
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link-name = "SLIM Capture";
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cpu {
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sound-dai = <&q6afedai SLIMBUS_0_TX>;
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};
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platform {
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sound-dai = <&q6routing>;
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};
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codec {
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sound-dai = <&wcd9335 1>;
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};
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};
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};
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@ -1024,8 +1024,9 @@
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>;
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clock-names = "iface";
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&xo_board>;
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clock-names = "iface", "ref";
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};
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};
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@ -13,6 +13,49 @@
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&msmgpio {
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wcd9xxx_intr {
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wcd_intr_default: wcd_intr_default{
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mux {
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pins = "gpio54";
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function = "gpio";
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};
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config {
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pins = "gpio54";
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drive-strength = <2>; /* 2 mA */
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bias-pull-down; /* pull down */
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input-enable;
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};
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};
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};
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cdc_reset_ctrl {
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cdc_reset_sleep: cdc_reset_sleep {
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mux {
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pins = "gpio64";
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function = "gpio";
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};
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config {
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pins = "gpio64";
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drive-strength = <16>;
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bias-disable;
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output-low;
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};
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};
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cdc_reset_active:cdc_reset_active {
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mux {
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pins = "gpio64";
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function = "gpio";
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};
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config {
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pins = "gpio64";
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drive-strength = <16>;
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bias-pull-down;
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output-high;
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};
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};
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};
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blsp1_spi0_default: blsp1_spi0_default {
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pinmux {
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function = "blsp_spi1";
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@ -14,6 +14,7 @@
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/soc/qcom,apr.h>
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/ {
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interrupt-parent = <&intc>;
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@ -84,6 +85,12 @@
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qcom,client-id = <1>;
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qcom,vmid = <15>;
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};
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zap_shader_region: gpu@8f200000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x90b00000 0x0 0xa00000>;
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no-map;
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};
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};
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cpus {
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@ -946,6 +953,11 @@
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reg = <0x24f 0x1>;
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bits = <1 4>;
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};
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gpu_speed_bin: gpu_speed_bin@133 {
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reg = <0x133 0x1>;
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bits = <5 3>;
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};
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};
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phy@34000 {
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@ -1288,6 +1300,70 @@
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};
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};
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adreno_smmu: arm,smmu@b40000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xb40000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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clocks = <&mmcc GPU_AHB_CLK>,
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<&gcc GCC_MMSS_BIMC_GFX_CLK>;
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clock-names = "iface", "bus";
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power-domains = <&mmcc GPU_GDSC>;
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status = "disabled";
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};
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mdp_smmu: arm,smmu@d00000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xd00000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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clocks = <&mmcc SMMU_MDP_AHB_CLK>,
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<&mmcc SMMU_MDP_AXI_CLK>;
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clock-names = "iface", "bus";
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power-domains = <&mmcc MDSS_GDSC>;
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status = "disabled";
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};
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lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0x1600000 0x20000>;
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#iommu-cells = <1>;
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power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
|
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|
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clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
|
||||
<&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
|
||||
clock-names = "iface", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
agnoc@0 {
|
||||
power-domains = <&gcc AGGRE0_NOC_GDSC>;
|
||||
compatible = "simple-pm-bus";
|
||||
@ -1453,6 +1529,265 @@
|
||||
"bus_slave";
|
||||
};
|
||||
};
|
||||
|
||||
slimbam:dma@9184000
|
||||
{
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
qcom,controlled-remotely;
|
||||
reg = <0x9184000 0x32000>;
|
||||
num-channels = <31>;
|
||||
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <1>;
|
||||
qcom,num-ees = <2>;
|
||||
};
|
||||
|
||||
slim_msm: slim@91c0000 {
|
||||
compatible = "qcom,slim-ngd-v1.5.0";
|
||||
reg = <0x91c0000 0x2C000>;
|
||||
reg-names = "ctrl";
|
||||
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&slimbam 3>, <&slimbam 4>,
|
||||
<&slimbam 5>, <&slimbam 6>;
|
||||
dma-names = "rx", "tx", "tx2", "rx2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ngd@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
tasha_ifd: tas-ifd {
|
||||
compatible = "slim217,1a0";
|
||||
reg = <0 0>;
|
||||
};
|
||||
|
||||
wcd9335: codec@1{
|
||||
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "slim217,1a0";
|
||||
reg = <1 0>;
|
||||
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "intr1", "intr2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reset-gpios = <&msmgpio 64 0>;
|
||||
|
||||
slim-ifc-dev = <&tasha_ifd>;
|
||||
|
||||
vdd-buck-supply = <&pm8994_s4>;
|
||||
vdd-buck-sido-supply = <&pm8994_s4>;
|
||||
vdd-tx-supply = <&pm8994_s4>;
|
||||
vdd-rx-supply = <&pm8994_s4>;
|
||||
vdd-io-supply = <&pm8994_s4>;
|
||||
|
||||
#sound-dai-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu@b00000 {
|
||||
compatible = "qcom,adreno-530.2", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
reg = <0xb00000 0x3f000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&mmcc GPU_GX_GFX3D_CLK>,
|
||||
<&mmcc GPU_AHB_CLK>,
|
||||
<&mmcc GPU_GX_RBBMTIMER_CLK>,
|
||||
<&gcc GCC_BIMC_GFX_CLK>,
|
||||
<&gcc GCC_MMSS_BIMC_GFX_CLK>;
|
||||
|
||||
clock-names = "core",
|
||||
"iface",
|
||||
"rbbmtimer",
|
||||
"mem",
|
||||
"mem_iface";
|
||||
|
||||
power-domains = <&mmcc GPU_GDSC>;
|
||||
iommus = <&adreno_smmu 0>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
qcom,gpu-quirk-two-pass-use-wfi;
|
||||
qcom,gpu-quirk-fault-detect-mask;
|
||||
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
compatible ="operating-points-v2";
|
||||
|
||||
/*
|
||||
* 624Mhz and 560Mhz are only available on speed
|
||||
* bin (1 << 0). All the rest are available on
|
||||
* all bins of the hardware
|
||||
*/
|
||||
opp-624000000 {
|
||||
opp-hz = /bits/ 64 <624000000>;
|
||||
opp-supported-hw = <0x01>;
|
||||
};
|
||||
opp-560000000 {
|
||||
opp-hz = /bits/ 64 <560000000>;
|
||||
opp-supported-hw = <0x01>;
|
||||
};
|
||||
opp-510000000 {
|
||||
opp-hz = /bits/ 64 <510000000>;
|
||||
opp-supported-hw = <0xFF>;
|
||||
};
|
||||
opp-401800000 {
|
||||
opp-hz = /bits/ 64 <401800000>;
|
||||
opp-supported-hw = <0xFF>;
|
||||
};
|
||||
opp-315000000 {
|
||||
opp-hz = /bits/ 64 <315000000>;
|
||||
opp-supported-hw = <0xFF>;
|
||||
};
|
||||
opp-214000000 {
|
||||
opp-hz = /bits/ 64 <214000000>;
|
||||
opp-supported-hw = <0xFF>;
|
||||
};
|
||||
opp-133000000 {
|
||||
opp-hz = /bits/ 64 <133000000>;
|
||||
opp-supported-hw = <0xFF>;
|
||||
};
|
||||
};
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&zap_shader_region>;
|
||||
};
|
||||
};
|
||||
|
||||
mdss: mdss@900000 {
|
||||
compatible = "qcom,mdss";
|
||||
|
||||
reg = <0x900000 0x1000>,
|
||||
<0x9b0000 0x1040>,
|
||||
<0x9b8000 0x1040>;
|
||||
reg-names = "mdss_phys",
|
||||
"vbif_phys",
|
||||
"vbif_nrt_phys";
|
||||
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
clock-names = "iface_clk";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp: mdp@901000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x901000 0x90000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc SMMU_MDP_AXI_CLK>,
|
||||
<&mmcc MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"bus_clk",
|
||||
"core_clk",
|
||||
"iommu_clk",
|
||||
"vsync_clk";
|
||||
|
||||
iommus = <&mdp_smmu 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf3_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi: hdmi-tx@9a0000 {
|
||||
compatible = "qcom,hdmi-tx-8996";
|
||||
reg = <0x009a0000 0x50c>,
|
||||
<0x00070000 0x6158>,
|
||||
<0x009e0000 0xfff>;
|
||||
reg-names = "core_physical",
|
||||
"qfprom_physical",
|
||||
"hdcp_physical";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_HDMI_CLK>,
|
||||
<&mmcc MDSS_HDMI_AHB_CLK>,
|
||||
<&mmcc MDSS_EXTPCLK_CLK>;
|
||||
clock-names =
|
||||
"mdp_core_clk",
|
||||
"iface_clk",
|
||||
"core_clk",
|
||||
"alt_iface_clk",
|
||||
"extp_clk";
|
||||
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi_phy";
|
||||
#sound-dai-cells = <1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hdmi_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf3_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_phy: hdmi-phy@9a0600 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "qcom,hdmi-phy-8996";
|
||||
reg = <0x9a0600 0x1c4>,
|
||||
<0x9a0a00 0x124>,
|
||||
<0x9a0c00 0x124>,
|
||||
<0x9a0e00 0x124>,
|
||||
<0x9a1000 0x124>,
|
||||
<0x9a1200 0x0c8>;
|
||||
reg-names = "hdmi_pll",
|
||||
"hdmi_tx_l0",
|
||||
"hdmi_tx_l1",
|
||||
"hdmi_tx_l2",
|
||||
"hdmi_tx_l3",
|
||||
"hdmi_phy";
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&gcc GCC_HDMI_CLKREF_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"ref_clk";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound: sound {
|
||||
};
|
||||
|
||||
adsp-pil {
|
||||
@ -1481,6 +1816,55 @@
|
||||
mboxes = <&apcs_glb 8>;
|
||||
qcom,smd-edge = <1>;
|
||||
qcom,remote-pid = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
apr {
|
||||
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
|
||||
compatible = "qcom,apr-v2";
|
||||
qcom,smd-channels = "apr_audio_svc";
|
||||
reg = <APR_DOMAIN_ADSP>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
q6core {
|
||||
reg = <APR_SVC_ADSP_CORE>;
|
||||
compatible = "qcom,q6core";
|
||||
};
|
||||
|
||||
q6afe: q6afe {
|
||||
compatible = "qcom,q6afe";
|
||||
reg = <APR_SVC_AFE>;
|
||||
q6afedai: dais {
|
||||
compatible = "qcom,q6afe-dais";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#sound-dai-cells = <1>;
|
||||
hdmi@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
q6asm: q6asm {
|
||||
compatible = "qcom,q6asm";
|
||||
reg = <APR_SVC_ASM>;
|
||||
q6asmdai: dais {
|
||||
compatible = "qcom,q6asm-dais";
|
||||
#sound-dai-cells = <1>;
|
||||
iommus = <&lpass_q6_smmu 1>;
|
||||
};
|
||||
};
|
||||
|
||||
q6adm: q6adm {
|
||||
compatible = "qcom,q6adm";
|
||||
reg = <APR_SVC_ADM>;
|
||||
q6routing: routing {
|
||||
compatible = "qcom,q6adm-routing";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -15,44 +15,6 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
battery-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens0 0>;
|
||||
|
||||
trips {
|
||||
battery_crit: trip0 {
|
||||
temperature = <60000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
skin-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens1 5>;
|
||||
|
||||
trips {
|
||||
skin_alert: trip0 {
|
||||
temperature = <44000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
skip_crit: trip1 {
|
||||
temperature = <70000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
|
||||
@ -536,7 +536,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
cluster0-mhm-thermal {
|
||||
clust0-mhm-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
@ -551,7 +551,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
cluster1-mhm-thermal {
|
||||
clust1-mhm-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
@ -745,7 +745,7 @@
|
||||
reg = <0x10ab000 0x1000>, /* TM */
|
||||
<0x10aa000 0x1000>; /* SROT */
|
||||
|
||||
#qcom,sensors = <12>;
|
||||
#qcom,sensors = <14>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
@ -58,6 +58,8 @@
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0x2400>;
|
||||
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
|
||||
io-channel-names = "thermal";
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
@ -190,6 +190,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <607>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
@ -207,6 +208,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <607>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_100>;
|
||||
@ -221,6 +223,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <607>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_200>;
|
||||
@ -235,6 +238,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <607>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_300>;
|
||||
@ -249,6 +253,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_400>;
|
||||
@ -263,6 +268,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_500>;
|
||||
@ -277,6 +283,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_600>;
|
||||
@ -291,6 +298,7 @@
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_700>;
|
||||
@ -299,6 +307,44 @@
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
@ -1985,8 +2031,9 @@
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
clock-names = "iface";
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
@ -2051,8 +2098,9 @@
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
clock-names = "iface";
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user