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ARM: dts: sti: ensure unique unit-address in stih407-clock

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Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.

Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Alain Volmat 2022-02-11 19:16:08 +01:00 committed by Patrice Chotard
parent e783362eb5
commit 97cdb33170
1 changed files with 47 additions and 56 deletions
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103
arch/arm/boot/dts/stih407-clock.dtsi
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@ -29,7 +29,7 @@
*/
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
reg = <0x92b0000 0xffff>;
reg = <0x92b0000 0x10000>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
@ -37,32 +37,27 @@
clocks = <&clk_sysin>;
};
};
/*
* ARM CPU related clocks.
*/
clk_m_a9: clk-m-a9@92b0000 {
#clock-cells = <0>;
compatible = "st,stih407-clkgen-a9-mux";
reg = <0x92b0000 0x10000>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
clk_m_a9: clk-m-a9 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
compatible = "st,stih407-clkgen-a9-mux";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
};
};
@ -87,14 +82,6 @@
};
};
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
};
clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@ -113,6 +100,13 @@
clocks = <&clk_sysin>;
};
clk_s_c0_quadfs: clk-s-c0-quadfs {
#clock-cells = <1>;
compatible = "st,quadfs-pll";
clocks = <&clk_sysin>;
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-c0";
@ -142,18 +136,17 @@
};
};
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
};
clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
clk_s_d0_quadfs: clk-s-d0-quadfs {
#clock-cells = <1>;
compatible = "st,quadfs-d0";
clocks = <&clk_sysin>;
};
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d0";
@ -166,18 +159,17 @@
};
};
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
};
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
clk_s_d2_quadfs: clk-s-d2-quadfs {
#clock-cells = <1>;
compatible = "st,quadfs-d2";
clocks = <&clk_sysin>;
};
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d2";
@ -192,18 +184,17 @@
};
};
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
};
clockgen-d3@9107000 {
compatible = "st,clkgen-c32";
reg = <0x9107000 0x1000>;
clk_s_d3_quadfs: clk-s-d3-quadfs {
#clock-cells = <1>;
compatible = "st,quadfs-d3";
clocks = <&clk_sysin>;
};
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d3";