forked from Minki/linux
drm/amdgpu: unify MQD programming sequence for kfd and amdgpu v2
Use the same gfx_*_mqd_commit function for kfd and amdgpu codepaths. This removes the last duplicates of this programming sequence. v2: fix cp_hqd_pq_wptr value Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
486d807cd9
commit
97bf47b21d
@ -29,6 +29,7 @@
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#include "cikd.h"
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#include "cik_sdma.h"
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#include "amdgpu_ucode.h"
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#include "gfx_v7_0.h"
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#include "gca/gfx_7_2_d.h"
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#include "gca/gfx_7_2_enum.h"
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#include "gca/gfx_7_2_sh_mask.h"
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@ -309,55 +310,11 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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m = get_mqd(mqd);
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is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
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if (is_wptr_shadow_valid)
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m->cp_hqd_pq_wptr = wptr_shadow;
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acquire_queue(kgd, pipe_id, queue_id);
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WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
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WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
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WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control);
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WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
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WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
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WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
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WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
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WREG32(mmCP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
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WREG32(mmCP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
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WREG32(mmCP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
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WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state);
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WREG32(mmCP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
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WREG32(mmCP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
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WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, m->cp_hqd_atomic0_preop_lo);
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WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, m->cp_hqd_atomic0_preop_hi);
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WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, m->cp_hqd_atomic1_preop_lo);
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WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, m->cp_hqd_atomic1_preop_hi);
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WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo);
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WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
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m->cp_hqd_pq_rptr_report_addr_hi);
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WREG32(mmCP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
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WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, m->cp_hqd_pq_wptr_poll_addr_lo);
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WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, m->cp_hqd_pq_wptr_poll_addr_hi);
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WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control);
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WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid);
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WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum);
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WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
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WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
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WREG32(mmCP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
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if (is_wptr_shadow_valid)
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WREG32(mmCP_HQD_PQ_WPTR, wptr_shadow);
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WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active);
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gfx_v7_0_mqd_commit(adev, m);
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release_queue(kgd);
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return 0;
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@ -28,6 +28,7 @@
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_ucode.h"
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#include "gfx_v8_0.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#include "gca/gfx_8_0_d.h"
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#include "gca/gfx_8_0_enum.h"
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@ -251,53 +252,11 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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m = get_mqd(mqd);
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valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr));
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acquire_queue(kgd, pipe_id, queue_id);
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WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control);
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WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
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WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
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WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid);
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WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state);
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WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
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WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
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WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum);
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WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
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WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
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WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo);
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WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
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m->cp_hqd_pq_rptr_report_addr_hi);
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if (valid_wptr > 0)
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WREG32(mmCP_HQD_PQ_WPTR, shadow_wptr);
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WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
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WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control);
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WREG32(mmCP_HQD_EOP_BASE_ADDR, m->cp_hqd_eop_base_addr_lo);
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WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, m->cp_hqd_eop_base_addr_hi);
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WREG32(mmCP_HQD_EOP_CONTROL, m->cp_hqd_eop_control);
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WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
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WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
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WREG32(mmCP_HQD_EOP_EVENTS, m->cp_hqd_eop_done_events);
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WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO, m->cp_hqd_ctx_save_base_addr_lo);
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WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI, m->cp_hqd_ctx_save_base_addr_hi);
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WREG32(mmCP_HQD_CTX_SAVE_CONTROL, m->cp_hqd_ctx_save_control);
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WREG32(mmCP_HQD_CNTL_STACK_OFFSET, m->cp_hqd_cntl_stack_offset);
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WREG32(mmCP_HQD_CNTL_STACK_SIZE, m->cp_hqd_cntl_stack_size);
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WREG32(mmCP_HQD_WG_STATE_OFFSET, m->cp_hqd_wg_state_offset);
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WREG32(mmCP_HQD_CTX_SAVE_SIZE, m->cp_hqd_ctx_save_size);
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WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
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WREG32(mmCP_HQD_DEQUEUE_REQUEST, m->cp_hqd_dequeue_request);
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WREG32(mmCP_HQD_ERROR, m->cp_hqd_error);
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WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
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WREG32(mmCP_HQD_EOP_DONES, m->cp_hqd_eop_dones);
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WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active);
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m->cp_hqd_pq_wptr = shadow_wptr;
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acquire_queue(kgd, pipe_id, queue_id);
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gfx_v8_0_mqd_commit(adev, mqd);
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release_queue(kgd);
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return 0;
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@ -3067,12 +3067,29 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
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/* set the vmid for the queue */
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mqd->cp_hqd_vmid = 0;
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/* defaults */
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mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
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mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
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mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
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mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
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mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
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mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
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mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
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mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
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mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
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mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
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mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
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mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
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mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
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mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
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mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
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mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
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/* activate the queue */
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mqd->cp_hqd_active = 1;
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}
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static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev,
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struct cik_mqd *mqd)
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int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
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{
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u32 tmp;
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@ -3096,6 +3113,23 @@ static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev,
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WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
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WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
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WREG32(mmCP_HQD_IB_CONTROL, mqd->cp_hqd_ib_control);
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WREG32(mmCP_HQD_IB_BASE_ADDR, mqd->cp_hqd_ib_base_addr_lo);
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WREG32(mmCP_HQD_IB_BASE_ADDR_HI, mqd->cp_hqd_ib_base_addr_hi);
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WREG32(mmCP_HQD_IB_RPTR, mqd->cp_hqd_ib_rptr);
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WREG32(mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
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WREG32(mmCP_HQD_SEMA_CMD, mqd->cp_hqd_sema_cmd);
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WREG32(mmCP_HQD_MSG_TYPE, mqd->cp_hqd_msg_type);
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WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, mqd->cp_hqd_atomic0_preop_lo);
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WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, mqd->cp_hqd_atomic0_preop_hi);
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WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, mqd->cp_hqd_atomic1_preop_lo);
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WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, mqd->cp_hqd_atomic1_preop_hi);
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WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
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WREG32(mmCP_HQD_QUANTUM, mqd->cp_hqd_quantum);
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WREG32(mmCP_HQD_PIPE_PRIORITY, mqd->cp_hqd_pipe_priority);
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WREG32(mmCP_HQD_QUEUE_PRIORITY, mqd->cp_hqd_queue_priority);
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WREG32(mmCP_HQD_IQ_RPTR, mqd->cp_hqd_iq_rptr);
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/* activate the HQD */
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WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
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@ -29,4 +29,9 @@ extern const struct amdgpu_ip_block_version gfx_v7_1_ip_block;
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extern const struct amdgpu_ip_block_version gfx_v7_2_ip_block;
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extern const struct amdgpu_ip_block_version gfx_v7_3_ip_block;
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struct amdgpu_device;
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struct cik_mqd;
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int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd);
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#endif
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@ -4913,17 +4913,32 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
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tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
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mqd->cp_hqd_ctx_save_control = tmp;
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/* defaults */
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mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
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mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
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mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
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mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
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mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
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mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
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mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
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mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
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mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
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mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
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mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
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mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
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mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
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mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
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mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
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/* activate the queue */
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mqd->cp_hqd_active = 1;
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return 0;
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}
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static int gfx_v8_0_mqd_commit(struct amdgpu_ring *ring)
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int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
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struct vi_mqd *mqd)
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{
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struct amdgpu_device *adev = ring->adev;
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struct vi_mqd *mqd = ring->mqd_ptr;
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/* disable wptr polling */
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WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
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@ -4970,6 +4985,28 @@ static int gfx_v8_0_mqd_commit(struct amdgpu_ring *ring)
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/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
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WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
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WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
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WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
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/* set the HQD priority */
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WREG32(mmCP_HQD_PIPE_PRIORITY, mqd->cp_hqd_pipe_priority);
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WREG32(mmCP_HQD_QUEUE_PRIORITY, mqd->cp_hqd_queue_priority);
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WREG32(mmCP_HQD_QUANTUM, mqd->cp_hqd_quantum);
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/* set cwsr save area */
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WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO, mqd->cp_hqd_ctx_save_base_addr_lo);
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WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI, mqd->cp_hqd_ctx_save_base_addr_hi);
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WREG32(mmCP_HQD_CTX_SAVE_CONTROL, mqd->cp_hqd_ctx_save_control);
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WREG32(mmCP_HQD_CNTL_STACK_OFFSET, mqd->cp_hqd_cntl_stack_offset);
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WREG32(mmCP_HQD_CNTL_STACK_SIZE, mqd->cp_hqd_cntl_stack_size);
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WREG32(mmCP_HQD_WG_STATE_OFFSET, mqd->cp_hqd_wg_state_offset);
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WREG32(mmCP_HQD_CTX_SAVE_SIZE, mqd->cp_hqd_ctx_save_size);
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WREG32(mmCP_HQD_IB_CONTROL, mqd->cp_hqd_ib_control);
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WREG32(mmCP_HQD_EOP_EVENTS, mqd->cp_hqd_eop_done_events);
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WREG32(mmCP_HQD_ERROR, mqd->cp_hqd_error);
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WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
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WREG32(mmCP_HQD_EOP_DONES, mqd->cp_hqd_eop_dones);
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/* set the vmid for the queue */
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WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
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@ -5006,7 +5043,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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dev_err(adev->dev, "failed to deactivate ring %s\n", ring->name);
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goto out_unlock;
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}
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gfx_v8_0_mqd_commit(ring);
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gfx_v8_0_mqd_commit(adev, mqd);
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vi_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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} else {
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@ -5018,7 +5055,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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dev_err(adev->dev, "failed to deactivate ring %s\n", ring->name);
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goto out_unlock;
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}
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gfx_v8_0_mqd_commit(ring);
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gfx_v8_0_mqd_commit(adev, mqd);
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vi_srbm_select(adev, 0, 0, 0, 0);
|
||||
mutex_unlock(&adev->srbm_mutex);
|
||||
|
||||
|
@ -27,4 +27,9 @@
|
||||
extern const struct amdgpu_ip_block_version gfx_v8_0_ip_block;
|
||||
extern const struct amdgpu_ip_block_version gfx_v8_1_ip_block;
|
||||
|
||||
struct amdgpu_device;
|
||||
struct vi_mqd;
|
||||
|
||||
int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, struct vi_mqd *mqd);
|
||||
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user