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These are the pin control changes for the v6.1 kernel cycle:

Browse Source 
New drivers:
 
 - Cypress CY8C95x0 chip pin control support, along with an immediate
   cleanup.
 
 - Mediatek MT8188 SoC pin control support.
 
 - Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem)
   pin control support.
 
 - Qualcomm PM7250, PM8450
 
 - Rockchip RV1126 SoC pin control support.
 
 Improvements:
 
 - Fix some missing pins in the Armada 37xx driver.
 
 - Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP() macro.
 
 - Fix some GPIO irq_chips to be immutable.
 
 - Massive Qualcomm device tree binding cleanup, with more to come.
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Merge tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "There is nothing exciting going on, no core changes, just a few
  drivers and cleanups.

  New drivers:

   - Cypress CY8C95x0 chip pin control support, along with an immediate
     cleanup

   - Mediatek MT8188 SoC pin control support

   - Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin
     control support

   - Qualcomm PM7250, PM8450

   - Rockchip RV1126 SoC pin control support

  Improvements:

   - Fix some missing pins in the Armada 37xx driver

   - Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP()
     macro

   - Fix some GPIO irq_chips to be immutable

   - Massive Qualcomm device tree binding cleanup, with more to come"

* tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits)
  MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement
  pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"
  pinctrl: Create subdirectory for StarFive drivers
  dt-bindings: pinctrl: st,stm32: Document interrupt-controller property
  dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property
  dt-bindings: pinctrl: st,stm32: Document gpio-line-names
  pinctrl: st: stop abusing of_get_named_gpio()
  pinctrl: wpcm450: Correct the fwnode_irq_get() return value check
  pinctrl: bcm: Remove unused struct bcm6328_pingroup
  pinctrl: qcom: restrict drivers per ARM/ARM64
  pinctrl: bcm: ns: Remove redundant dev_err call
  gpio: rockchip: request GPIO mux to pinctrl when setting direction
  pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback
  pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops
  pinctrl: cy8c95x0: Drop atomicity on operations on push_pull
  pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux()
  pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper
  pinctrl: stm32: Switch to use dev_err_probe() helper
  dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings
  pinctrl: qcom: spmi-gpio: Add compatible for PM7250B
  ...
This commit is contained in:
Linus Torvalds 2022-10-11 10:59:59 -07:00
commit 979bb59016
90 changed files with 9445 additions and 1147 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
View File

@ -63,6 +63,12 @@ examples:
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e6e2000 0x1000>;
pinctrl: pinctrl {
compatible = "aspeed,ast2400-pinctrl";

4
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View File

@ -82,6 +82,10 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e6e2000 0x1000>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx>, <&lhc>;

6
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
View File

@ -96,6 +96,12 @@ examples:
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0xf6c>;
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e6e2000 0x1000>;
pinctrl: pinctrl {
compatible = "aspeed,ast2600-pinctrl";

1
Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
View File

@ -23,6 +23,7 @@ patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
function:

134
Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml Normal file
View File

@ -0,0 +1,134 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/cypress,cy8c95x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cypress CY8C95X0 I2C GPIO expander
maintainers:
- Patrick Rudolph <patrick.rudolph@9elements.com>
description: |
This supports the 20/40/60 pin Cypress CYC95x0 GPIO I2C expanders.
Pin function configuration is performed on a per-pin basis.
properties:
compatible:
enum:
- cypress,cy8c9520
- cypress,cy8c9540
- cypress,cy8c9560
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
description:
The first cell is the GPIO number and the second cell specifies GPIO
flags, as defined in <dt-bindings/gpio/gpio.h>.
const: 2
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-line-names: true
gpio-ranges:
maxItems: 1
gpio-reserved-ranges:
maxItems: 1
vdd-supply:
description:
Optional power supply.
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: pincfg-node.yaml#
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: '^gp([0-7][0-7])$'
minItems: 1
maxItems: 60
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, pwm ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
drive-push-pull: true
drive-open-drain: true
drive-open-source: true
required:
- pins
- function
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pinctrl@20 {
compatible = "cypress,cy8c9520";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
vdd-supply = <&p3v3>;
gpio-reserved-ranges = <5 1>;
};
};

1
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
View File

@ -44,6 +44,7 @@ properties:
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
additionalProperties: false
description:
Child nodes can be specified to contain pin configuration information,

1
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-thunderbay.yaml
View File

@ -42,6 +42,7 @@ properties:
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
additionalProperties: false
description:
Child nodes can be specified to contain pin configuration information,

1
Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml
View File

@ -24,6 +24,7 @@ patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
marvell,function:

2
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
View File

@ -76,6 +76,8 @@ required:
patternProperties:
'-[0-9]*$':
type: object
additionalProperties: false
patternProperties:
'-pins*$':
type: object

8
Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml
View File

@ -117,6 +117,10 @@ patternProperties:
"i2s" "audio" 62, 63, 64, 65
"switch_int" "eth" 66
"mdc_mdio" "eth" 67
"wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83
"wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100
"wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
84, 85
$ref: "/schemas/pinctrl/pinmux-node.yaml"
properties:
@ -234,7 +238,9 @@ patternProperties:
then:
properties:
groups:
items:
enum: [wf_2g, wf_5g, wf_dbdc]
maxItems: 3
'.*conf.*':
type: object
additionalProperties: false
@ -248,6 +254,7 @@ patternProperties:
An array of strings. Each string contains the name of a pin.
There is no PIN 41 to PIN 65 above on mt7686b, you can only use
those pins on mt7986a.
items:
enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14,
@ -267,6 +274,7 @@ patternProperties:
WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
WF1_HB8]
maxItems: 101
bias-disable: true

226
Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml Normal file
View File

@ -0,0 +1,226 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT8188 Pin Controller
maintainers:
- Hui Liu <hui.liu@mediatek.com>
description: |
The MediaTek's MT8188 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8188-pinctrl
gpio-controller: true
'#gpio-cells':
description: |
Number of cells in GPIO specifier, should be two. The first cell
is the pin number, the second cell is used to specify optional
parameters which are defined in <dt-bindings/gpio/gpio.h>.
const: 2
gpio-ranges:
maxItems: 1
gpio-line-names: true
reg:
items:
- description: gpio registers base address
- description: rm group io configuration registers base address
- description: lt group io configuration registers base address
- description: lm group io configuration registers base address
- description: rt group io configuration registers base address
- description: eint registers base address
reg-names:
items:
- const: iocfg0
- const: iocfg_rm
- const: iocfg_lt
- const: iocfg_lm
- const: iocfg_rt
- const: eint
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
mediatek,rsel-resistance-in-si-unit:
type: boolean
description: |
We provide two methods to select the resistance for I2C when pull up or pull down.
The first is by RSEL definition value, another one is by resistance value(ohm).
This flag is used to identify if the method is resistance(si unit) value.
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
$ref: "/schemas/pinctrl/pincfg-node.yaml"
additionalProperties: false
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in dt-bindings/pinctrl/mediatek,<soc>-pinfunc.h
directly.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8188 pull down PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
description: mt8188 pull down RSEL type define value.
- enum: [75000, 5000]
description: mt8188 pull down RSEL type si unit value(ohm).
description: |
For pull down type is normal, it doesn't need add RSEL & R1R0 define
and resistance value.
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
define in mt8188.
For pull down type is RSEL, it can add RSEL define & resistance value(ohm)
to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
& "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
define in mt8188. It can also support resistance value(ohm) "75000" & "5000" in mt8188.
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8188 pull up PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
description: mt8188 pull up RSEL type define value.
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
description: mt8188 pull up RSEL type si unit value(ohm).
description: |
For pull up type is normal, it don't need add RSEL & R1R0 define
and resistance value.
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
define in mt8188.
For pull up type is RSEL, it can add RSEL define & resistance value(ohm)
to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
& "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
define in mt8188. It can also support resistance value(ohm)
"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188.
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8188-pinctrl";
reg = <0x10005000 0x1000>,
<0x11c00000 0x1000>,
<0x11e10000 0x1000>,
<0x11e20000 0x1000>,
<0x11ea0000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_rm",
"iocfg_lt", "iocfg_lm", "iocfg_rt",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 176>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
pio-pins {
pins {
pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>;
output-low;
};
};
spi0-pins {
pins-spi {
pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
<PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
<PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>;
drive-strength = <6>;
};
pins-spi-mi {
pinmux = <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO55__FUNC_B1_SCL0>,
<PINMUX_GPIO56__FUNC_B1_SDA0>;
bias-disable;
drive-strength-microamp = <1000>;
};
};
};

1
Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml
View File

@ -30,6 +30,7 @@ patternProperties:
"^gpio@[0-7]$":
type: object
additionalProperties: false
description:
Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18

14
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
View File

@ -41,12 +41,12 @@ properties:
Gpio base register names.
items:
- const: iocfg0
- const: iocfg_bm
- const: iocfg_bl
- const: iocfg_br
- const: iocfg_lt
- const: iocfg_lm
- const: iocfg_lb
- const: iocfg_bl
- const: iocfg_rb
- const: iocfg_tl
- const: iocfg_rt
- const: eint
interrupt-controller: true
@ -235,9 +235,9 @@ examples:
<0x10002A00 0x0200>,
<0x10002c00 0x0200>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
"iocfg_br", "iocfg_lm", "iocfg_rb",
"iocfg_tl", "eint";
reg-names = "iocfg0", "iocfg_lt", "iocfg_lm",
"iocfg_lb", "iocfg_bl", "iocfg_rb",
"iocfg_rt", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 185>;

4
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -24,6 +24,7 @@ properties:
- qcom,pm6150-gpio
- qcom,pm6150l-gpio
- qcom,pm6350-gpio
- qcom,pm7250b-gpio
- qcom,pm7325-gpio
- qcom,pm8005-gpio
- qcom,pm8008-gpio
@ -231,6 +232,7 @@ allOf:
enum:
- qcom,pm660l-gpio
- qcom,pm6150l-gpio
- qcom,pm7250b-gpio
- qcom,pm8038-gpio
- qcom,pm8150b-gpio
- qcom,pm8150l-gpio
@ -392,6 +394,7 @@ $defs:
- gpio1-gpio10 for pm6150
- gpio1-gpio12 for pm6150l
- gpio1-gpio9 for pm6350
- gpio1-gpio12 for pm7250b
- gpio1-gpio10 for pm7325
- gpio1-gpio4 for pm8005
- gpio1-gpio2 for pm8008
@ -407,6 +410,7 @@ $defs:
- gpio1-gpio10 for pm8350
- gpio1-gpio8 for pm8350b
- gpio1-gpio9 for pm8350c
- gpio1-gpio4 for pm8450
- gpio1-gpio38 for pm8917
- gpio1-gpio44 for pm8921
- gpio1-gpio36 for pm8941

17
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
View File

@ -42,6 +42,9 @@ properties:
gpio-ranges:
maxItems: 1
gpio-line-names:
maxItems: 174
wakeup-parent: true
#PIN CONFIGURATION NODES
@ -51,7 +54,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pins:
@ -60,7 +62,7 @@ patternProperties:
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$"
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
@ -118,12 +120,21 @@ patternProperties:
required:
- pins
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
then:
required:
- function
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible

17
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@ -51,8 +51,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sc8180x-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sc8180x-tlmm-state"
additionalProperties: false
'$defs':
qcom-sc8180x-tlmm-state:
@ -60,7 +61,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -111,6 +111,15 @@ patternProperties:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
then:
required:
- function
additionalProperties: false
@ -137,13 +146,13 @@ examples:
};
uart-w-subnodes-state {
rx {
rx-pins {
pins = "gpio4";
function = "qup6";
bias-pull-up;
};
tx {
tx-pins {
pins = "gpio5";
function = "qup6";
bias-disable;

133
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@ -0,0 +1,133 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
Low Power Island (LPI) TLMM block
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
LPASS LPI IP on most Qualcomm SoCs
properties:
compatible:
const: qcom,sc8280xp-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-1]|1[0-8]])$"
function:
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
description:
Specify the alternative function to be configured for the specified
pins.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
slew-rate:
enum: [0, 1, 2, 3]
default: 0
description: |
0: No adjustments
1: Higher Slew rate (faster edges)
2: Lower Slew rate (slower edges)
3: Reserved (No adjustments)
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6afe.h>
pinctrl@33c0000 {
compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
reg = <0x33c0000 0x20000>,
<0x3550000 0x10000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 18>;
};

17
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@ -43,8 +43,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
additionalProperties: false
'$defs':
qcom-sc8280xp-tlmm-state:
@ -52,7 +53,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -112,6 +112,15 @@ patternProperties:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
then:
required:
- function
additionalProperties: false
@ -135,13 +144,13 @@ examples:
};
uart-w-subnodes-state {
rx {
rx-pins {
pins = "gpio4";
function = "qup14";
bias-pull-up;
};
tx {
tx-pins {
pins = "gpio5";
function = "qup14";
bias-disable;

24
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml
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@ -49,6 +49,8 @@ properties:
gpio-ranges:
maxItems: 1
gpio-reserved-ranges: true
wakeup-parent: true
#PIN CONFIGURATION NODES
@ -57,8 +59,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6115-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6115-tlmm-state"
additionalProperties: false
'$defs':
qcom-sm6115-tlmm-state:
@ -66,7 +69,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -118,6 +120,16 @@ patternProperties:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
then:
required:
- function
additionalProperties: false
allOf:
@ -153,25 +165,25 @@ examples:
gpio-ranges = <&tlmm 0 0 114>;
sdc2_on_state: sdc2-on-state {
clk {
clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
sd-cd-pins {
pins = "gpio88";
function = "gpio";
bias-pull-up;

33
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@ -51,8 +51,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6125-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6125-tlmm-state"
additionalProperties: false
$defs:
qcom-sm6125-tlmm-state:
@ -60,7 +61,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -111,6 +111,15 @@ $defs:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
then:
required:
- function
additionalProperties: false
@ -130,4 +139,24 @@ examples:
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
sdc2-off-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
};
};

17
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@ -44,8 +44,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6350-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6350-tlmm-state"
additionalProperties: false
$defs:
qcom-sm6350-tlmm-state:
@ -53,7 +54,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -110,6 +110,15 @@ $defs:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$"
then:
required:
- function
additionalProperties: false
@ -133,13 +142,13 @@ examples:
};
uart-w-subnodes-state {
rx {
rx-pins {
pins = "gpio25";
function = "qup13_f2";
bias-disable;
};
tx {
tx-pins {
pins = "gpio26";
function = "qup13_f2";
bias-disable;

17
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml
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@ -44,8 +44,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6375-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6375-tlmm-state"
additionalProperties: false
$defs:
qcom-sm6375-tlmm-state:
@ -53,7 +54,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -119,6 +119,15 @@ $defs:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
then:
required:
- function
additionalProperties: false
@ -142,13 +151,13 @@ examples:
};
uart-w-subnodes-state {
rx {
rx-pins {
pins = "gpio18";
function = "qup13_f2";
bias-pull-up;
};
tx {
tx-pins {
pins = "gpio19";
function = "qup13_f2";
bias-disable;

9
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
View File

@ -110,6 +110,15 @@ patternProperties:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
then:
required:
- function
additionalProperties: false

17
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml
View File

@ -44,8 +44,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm8350-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm8350-tlmm-state"
additionalProperties: false
$defs:
qcom-sm8350-tlmm-state:
@ -53,7 +54,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -107,6 +107,15 @@ $defs:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
then:
required:
- function
additionalProperties: false
@ -130,13 +139,13 @@ examples:
};
uart-w-subnodes-state {
rx {
rx-pins {
pins = "gpio18";
function = "qup3";
bias-pull-up;
};
tx {
tx-pins {
pins = "gpio19";
function = "qup3";
bias-disable;

135
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@ -0,0 +1,135 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
Low Power Island (LPI) TLMM block
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
LPASS LPI IP on most Qualcomm SoCs
properties:
compatible:
const: qcom,sm8450-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-2][0-9]])$"
function:
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data,
slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data,
ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d,
ext_mclk1_e ]
description:
Specify the alternative function to be configured for the specified
pins.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
slew-rate:
enum: [0, 1, 2, 3]
default: 0
description: |
0: No adjustments
1: Higher Slew rate (faster edges)
2: Lower Slew rate (slower edges)
3: Reserved (No adjustments)
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6afe.h>
pinctrl@3440000 {
compatible = "qcom,sm8450-lpass-lpi-pinctrl";
reg = <0x3440000 0x20000>,
<0x34d0000 0x10000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 23>;
};

30
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml
View File

@ -27,7 +27,14 @@ properties:
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
gpio-reserved-ranges:
minItems: 1
maxItems: 105
gpio-line-names:
maxItems: 209
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
@ -43,8 +50,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm8450-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm8450-tlmm-state"
additionalProperties: false
$defs:
qcom-sm8450-tlmm-state:
@ -52,7 +60,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
@ -104,6 +111,15 @@ $defs:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
then:
required:
- function
additionalProperties: false
@ -121,19 +137,19 @@ examples:
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-wo-subnode-state {
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
uart-w-state {
rx-pins {
pins = "gpio26";
function = "qup7";
bias-pull-up;
};
tx {
tx-pins {
pins = "gpio27";
function = "qup7";
bias-disable;

1
Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml
View File

@ -41,6 +41,7 @@ required:
patternProperties:
"^gpio-[0-9]*$":
type: object
additionalProperties: false
description:
Each port of the r7s72100 pin controller hardware is itself a GPIO

2
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View File

@ -23,7 +23,7 @@ properties:
oneOf:
- items:
- enum:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- items:

1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
View File

@ -47,6 +47,7 @@ properties:
- rockchip,rk3568-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
- rockchip,rv1126-pinctrl
rockchip,grf:
$ref: "/schemas/types.yaml#/definitions/phandle"

1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml
View File

@ -20,7 +20,6 @@ description: |
The values used for config properties should be derived from the hardware
manual and these values are programmed as-is into the pin pull up/down and
driver strength register of the pin-controller.
See also include/dt-bindings/pinctrl/samsung.h with useful constants.
See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
additional information and example.

66
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
View File

@ -15,9 +15,6 @@ description: |
This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
controller.
Pin group settings (like drive strength, pull up/down) are available as
macros in include/dt-bindings/pinctrl/samsung.h.
All the pin controller nodes should be represented in the aliases node using
the following format 'pinctrl{n}' where n is a unique number for the alias.
@ -97,6 +94,9 @@ patternProperties:
additionalProperties: false
"^(initial|sleep)-state$":
type: object
additionalProperties: false
patternProperties:
"^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$":
$ref: samsung,pinctrl-pins-cfg.yaml
@ -138,8 +138,6 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@7f008000 {
compatible = "samsung,s3c64xx-pinctrl";
reg = <0x7f008000 0x1000>;
@ -166,8 +164,8 @@ examples:
uart0-data-pins {
samsung,pins = "gpa-0", "gpa-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
// ...
@ -175,7 +173,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
@ -197,9 +194,9 @@ examples:
uart0-data-pins {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
// ...
@ -207,14 +204,14 @@ examples:
sleep0: sleep-state {
gpa0-0-pin {
samsung,pins = "gpa0-0";
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-con-pdn = <2>;
samsung,pin-pud-pdn = <0>;
};
gpa0-1-pin {
samsung,pins = "gpa0-1";
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>;
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-con-pdn = <0>;
samsung,pin-pud-pdn = <0>;
};
// ...
@ -223,7 +220,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
@ -272,26 +268,26 @@ examples:
sd0-clk-pins {
samsung,pins = "gpk0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd4-bus-width8-pins {
part-1-pins {
samsung,pins = "gpk0-3", "gpk0-4",
"gpk0-5", "gpk0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
part-2-pins {
samsung,pins = "gpk1-3", "gpk1-4",
"gpk1-5", "gpk1-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
};
@ -299,16 +295,15 @@ examples:
otg-gp-pins {
samsung,pins = "gpx3-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
samsung,pin-val = <0>;
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@10580000 {
compatible = "samsung,exynos5433-pinctrl";
@ -352,9 +347,9 @@ examples:
initial_alive: initial-state {
gpa0-0-pin {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
// ...
@ -363,7 +358,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@114b0000 {
compatible = "samsung,exynos5433-pinctrl";
@ -384,9 +378,9 @@ examples:
i2s0-bus-pins {
samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
"gpz0-4", "gpz0-5", "gpz0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
// ...

13
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View File

@ -64,6 +64,9 @@ patternProperties:
gpio-controller: true
'#gpio-cells':
const: 2
interrupt-controller: true
'#interrupt-cells':
const: 2
reg:
maxItems: 1
@ -71,6 +74,7 @@ patternProperties:
maxItems: 1
resets:
maxItems: 1
gpio-line-names: true
gpio-ranges:
minItems: 1
maxItems: 16
@ -106,6 +110,12 @@ patternProperties:
minimum: 0
maximum: 11
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
type: object
required:
- gpio-hog
required:
- gpio-controller
- '#gpio-cells'
@ -115,9 +125,12 @@ patternProperties:
'-[0-9]*$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl group available on the machine. Each subnode will list the

2
Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
View File

@ -165,7 +165,7 @@ examples:
- |
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/reset/starfive-jh7100.h>
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
soc {
#address-cells = <2>;

1
Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
View File

@ -36,6 +36,7 @@ patternProperties:
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength.
$ref: "pinmux-node.yaml"
additionalProperties: false
properties:
function:

10
MAINTAINERS
View File

@ -5665,6 +5665,12 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
T: git git://linuxtv.org/anttip/media_tree.git
F: drivers/media/common/cypress_firmware*
CYPRESS CY8C95X0 PINCTRL DRIVER
M: Patrick Rudolph <patrick.rudolph@9elements.com>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/pinctrl/pinctrl-cy8c95x0.c
CYPRESS CY8CTMA140 TOUCHSCREEN DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-input@vger.kernel.org
@ -19606,8 +19612,8 @@ M: Emil Renner Berthing <kernel@esmil.dk>
L: linux-gpio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
F: drivers/pinctrl/pinctrl-starfive.c
F: include/dt-bindings/pinctrl/pinctrl-starfive.h
F: drivers/pinctrl/starfive/
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
STARFIVE JH7100 RESET CONTROLLER DRIVER
M: Emil Renner Berthing <kernel@esmil.dk>

15
arch/arm/mach-at91/pm.c
View File

@ -19,8 +19,6 @@
#include <linux/clk/at91_pmc.h>
#include <linux/platform_data/atmel.h>
#include <soc/at91/pm.h>
#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/system_misc.h>
@ -656,16 +654,6 @@ static int at91_pm_enter(suspend_state_t state)
if (ret)
return ret;
#ifdef CONFIG_PINCTRL_AT91
/*
* FIXME: this is needed to communicate between the pinctrl driver and
* the PM implementation in the machine. Possibly part of the PM
* implementation should be moved down into the pinctrl driver and get
* called as part of the generic suspend/resume path.
*/
at91_pinctrl_gpio_suspend();
#endif
switch (state) {
case PM_SUSPEND_MEM:
case PM_SUSPEND_STANDBY:
@ -690,9 +678,6 @@ static int at91_pm_enter(suspend_state_t state)
}
error:
#ifdef CONFIG_PINCTRL_AT91
at91_pinctrl_gpio_resume();
#endif
at91_pm_config_quirks(false);
return 0;
}

2
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
View File

@ -8,7 +8,7 @@
#include "jh7100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
/ {
model = "BeagleV Starlight Beta";

7
drivers/gpio/gpio-rockchip.c
View File

@ -19,6 +19,7 @@
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regmap.h>
@ -156,6 +157,12 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip,
unsigned long flags;
u32 data = input ? 0 : 1;
if (input)
pinctrl_gpio_direction_input(bank->pin_base + offset);
else
pinctrl_gpio_direction_output(bank->pin_base + offset);
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(&bank->slock, flags);

37
drivers/pinctrl/Kconfig
View File

@ -135,6 +135,20 @@ config PINCTRL_BM1880
help
Pinctrl driver for Bitmain BM1880 SoC.
config PINCTRL_CY8C95X0
tristate "Cypress CY8C95X0 I2C pinctrl and GPIO driver"
depends on I2C
select GPIOLIB
select GPIOLIB_IRQCHIP
select PINMUX
select PINCONF
select GENERIC_PINCONF
select REGMAP_I2C
help
Support for 20/40/60 pin Cypress Cy8C95x0 pinctrl/gpio I2C expander.
This driver can also be built as a module. If so, the module will be
called pinctrl-cy8c95x0.
config PINCTRL_DA850_PUPD
tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups"
depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST)
@ -324,6 +338,11 @@ config PINCTRL_OCELOT
select GENERIC_PINMUX_FUNCTIONS
select OF_GPIO
select REGMAP_MMIO
help
Support for the internal GPIO interfaces on Microsemi Ocelot and
Jaguar2 SoCs.
If conpiled as a module, the module name will be pinctrl-ocelot.
config PINCTRL_OXNAS
bool
@ -415,23 +434,6 @@ config PINCTRL_ST
select PINCONF
select GPIOLIB_IRQCHIP
config PINCTRL_STARFIVE
tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
depends on SOC_STARFIVE || COMPILE_TEST
depends on OF
default SOC_STARFIVE
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
select OF_GPIO
help
Say yes here to support pin control on the StarFive JH7100 SoC.
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
config PINCTRL_STMFX
tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
depends on I2C
@ -529,6 +531,7 @@ source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/starfive/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunplus/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"

3
drivers/pinctrl/Makefile
View File

@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
@ -43,7 +44,6 @@ obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
@ -70,6 +70,7 @@ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_SOC_STARFIVE) += starfive/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
obj-y += sunplus/
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/

9
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View File

@ -92,19 +92,10 @@ static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
pr_debug("Disabling signal %s for %s\n", expr->signal,
expr->function);
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
if (ret)
return aspeed_sig_expr_set(ctx, expr, false);
return 0;
}
/**

121
drivers/pinctrl/bcm/pinctrl-bcm6318.c
View File

@ -27,12 +27,6 @@
#define BCM6318_PAD_REG 0x54
#define BCM6328_PAD_MASK GENMASK(3, 0)
struct bcm6318_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6318_function {
const char *name;
const char * const *groups;
@ -146,64 +140,57 @@ static unsigned gpio47_pins[] = { 47 };
static unsigned gpio48_pins[] = { 48 };
static unsigned gpio49_pins[] = { 49 };
#define BCM6318_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6318_pingroup bcm6318_groups[] = {
BCM6318_GROUP(gpio0),
BCM6318_GROUP(gpio1),
BCM6318_GROUP(gpio2),
BCM6318_GROUP(gpio3),
BCM6318_GROUP(gpio4),
BCM6318_GROUP(gpio5),
BCM6318_GROUP(gpio6),
BCM6318_GROUP(gpio7),
BCM6318_GROUP(gpio8),
BCM6318_GROUP(gpio9),
BCM6318_GROUP(gpio10),
BCM6318_GROUP(gpio11),
BCM6318_GROUP(gpio12),
BCM6318_GROUP(gpio13),
BCM6318_GROUP(gpio14),
BCM6318_GROUP(gpio15),
BCM6318_GROUP(gpio16),
BCM6318_GROUP(gpio17),
BCM6318_GROUP(gpio18),
BCM6318_GROUP(gpio19),
BCM6318_GROUP(gpio20),
BCM6318_GROUP(gpio21),
BCM6318_GROUP(gpio22),
BCM6318_GROUP(gpio23),
BCM6318_GROUP(gpio24),
BCM6318_GROUP(gpio25),
BCM6318_GROUP(gpio26),
BCM6318_GROUP(gpio27),
BCM6318_GROUP(gpio28),
BCM6318_GROUP(gpio29),
BCM6318_GROUP(gpio30),
BCM6318_GROUP(gpio31),
BCM6318_GROUP(gpio32),
BCM6318_GROUP(gpio33),
BCM6318_GROUP(gpio34),
BCM6318_GROUP(gpio35),
BCM6318_GROUP(gpio36),
BCM6318_GROUP(gpio37),
BCM6318_GROUP(gpio38),
BCM6318_GROUP(gpio39),
BCM6318_GROUP(gpio40),
BCM6318_GROUP(gpio41),
BCM6318_GROUP(gpio42),
BCM6318_GROUP(gpio43),
BCM6318_GROUP(gpio44),
BCM6318_GROUP(gpio45),
BCM6318_GROUP(gpio46),
BCM6318_GROUP(gpio47),
BCM6318_GROUP(gpio48),
BCM6318_GROUP(gpio49),
static struct pingroup bcm6318_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(gpio48),
BCM_PIN_GROUP(gpio49),
};
/* GPIO_MODE */
@ -368,10 +355,10 @@ static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6318_groups[group].pins;
*num_pins = bcm6318_groups[group].num_pins;
*npins = bcm6318_groups[group].npins;
return 0;
}
@ -424,7 +411,7 @@ static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6318_pingroup *pg = &bcm6318_groups[group];
const struct pingroup *pg = &bcm6318_groups[group];
const struct bcm6318_function *f = &bcm6318_funcs[selector];
bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);

139
drivers/pinctrl/bcm/pinctrl-bcm63268.c
View File

@ -40,12 +40,6 @@ enum bcm63268_pinctrl_reg {
BCM63268_BASEMODE,
};
struct bcm63268_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm63268_function {
const char *name;
const char * const *groups;
@ -185,74 +179,67 @@ static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
#define BCM63268_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm63268_pingroup bcm63268_groups[] = {
BCM63268_GROUP(gpio0),
BCM63268_GROUP(gpio1),
BCM63268_GROUP(gpio2),
BCM63268_GROUP(gpio3),
BCM63268_GROUP(gpio4),
BCM63268_GROUP(gpio5),
BCM63268_GROUP(gpio6),
BCM63268_GROUP(gpio7),
BCM63268_GROUP(gpio8),
BCM63268_GROUP(gpio9),
BCM63268_GROUP(gpio10),
BCM63268_GROUP(gpio11),
BCM63268_GROUP(gpio12),
BCM63268_GROUP(gpio13),
BCM63268_GROUP(gpio14),
BCM63268_GROUP(gpio15),
BCM63268_GROUP(gpio16),
BCM63268_GROUP(gpio17),
BCM63268_GROUP(gpio18),
BCM63268_GROUP(gpio19),
BCM63268_GROUP(gpio20),
BCM63268_GROUP(gpio21),
BCM63268_GROUP(gpio22),
BCM63268_GROUP(gpio23),
BCM63268_GROUP(gpio24),
BCM63268_GROUP(gpio25),
BCM63268_GROUP(gpio26),
BCM63268_GROUP(gpio27),
BCM63268_GROUP(gpio28),
BCM63268_GROUP(gpio29),
BCM63268_GROUP(gpio30),
BCM63268_GROUP(gpio31),
BCM63268_GROUP(gpio32),
BCM63268_GROUP(gpio33),
BCM63268_GROUP(gpio34),
BCM63268_GROUP(gpio35),
BCM63268_GROUP(gpio36),
BCM63268_GROUP(gpio37),
BCM63268_GROUP(gpio38),
BCM63268_GROUP(gpio39),
BCM63268_GROUP(gpio40),
BCM63268_GROUP(gpio41),
BCM63268_GROUP(gpio42),
BCM63268_GROUP(gpio43),
BCM63268_GROUP(gpio44),
BCM63268_GROUP(gpio45),
BCM63268_GROUP(gpio46),
BCM63268_GROUP(gpio47),
BCM63268_GROUP(gpio48),
BCM63268_GROUP(gpio49),
BCM63268_GROUP(gpio50),
BCM63268_GROUP(gpio51),
static struct pingroup bcm63268_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(gpio48),
BCM_PIN_GROUP(gpio49),
BCM_PIN_GROUP(gpio50),
BCM_PIN_GROUP(gpio51),
/* multi pin groups */
BCM63268_GROUP(nand_grp),
BCM63268_GROUP(dectpd_grp),
BCM63268_GROUP(vdsl_phy0_grp),
BCM63268_GROUP(vdsl_phy1_grp),
BCM63268_GROUP(vdsl_phy2_grp),
BCM63268_GROUP(vdsl_phy3_grp),
BCM_PIN_GROUP(nand_grp),
BCM_PIN_GROUP(dectpd_grp),
BCM_PIN_GROUP(vdsl_phy0_grp),
BCM_PIN_GROUP(vdsl_phy1_grp),
BCM_PIN_GROUP(vdsl_phy2_grp),
BCM_PIN_GROUP(vdsl_phy3_grp),
};
static const char * const led_groups[] = {
@ -487,10 +474,10 @@ static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm63268_groups[group].pins;
*num_pins = bcm63268_groups[group].num_pins;
*npins = bcm63268_groups[group].npins;
return 0;
}
@ -545,13 +532,13 @@ static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm63268_pingroup *pg = &bcm63268_groups[group];
const struct pingroup *pg = &bcm63268_groups[group];
const struct bcm63268_function *f = &bcm63268_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->num_pins; i++)
for (i = 0; i < pg->npins; i++)
bcm63268_set_gpio(pc, pg->pins[i]);
switch (f->reg) {

89
drivers/pinctrl/bcm/pinctrl-bcm6328.c
View File

@ -26,12 +26,6 @@
#define BCM6328_MUX_OTHER_REG 0x24
#define BCM6328_MUX_MASK GENMASK(1, 0)
struct bcm6328_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6328_function {
const char *name;
const char * const *groups;
@ -125,49 +119,42 @@ static unsigned gpio31_pins[] = { 31 };
static unsigned hsspi_cs1_pins[] = { 36 };
static unsigned usb_port1_pins[] = { 38 };
#define BCM6328_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct pingroup bcm6328_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
static struct bcm6328_pingroup bcm6328_groups[] = {
BCM6328_GROUP(gpio0),
BCM6328_GROUP(gpio1),
BCM6328_GROUP(gpio2),
BCM6328_GROUP(gpio3),
BCM6328_GROUP(gpio4),
BCM6328_GROUP(gpio5),
BCM6328_GROUP(gpio6),
BCM6328_GROUP(gpio7),
BCM6328_GROUP(gpio8),
BCM6328_GROUP(gpio9),
BCM6328_GROUP(gpio10),
BCM6328_GROUP(gpio11),
BCM6328_GROUP(gpio12),
BCM6328_GROUP(gpio13),
BCM6328_GROUP(gpio14),
BCM6328_GROUP(gpio15),
BCM6328_GROUP(gpio16),
BCM6328_GROUP(gpio17),
BCM6328_GROUP(gpio18),
BCM6328_GROUP(gpio19),
BCM6328_GROUP(gpio20),
BCM6328_GROUP(gpio21),
BCM6328_GROUP(gpio22),
BCM6328_GROUP(gpio23),
BCM6328_GROUP(gpio24),
BCM6328_GROUP(gpio25),
BCM6328_GROUP(gpio26),
BCM6328_GROUP(gpio27),
BCM6328_GROUP(gpio28),
BCM6328_GROUP(gpio29),
BCM6328_GROUP(gpio30),
BCM6328_GROUP(gpio31),
BCM6328_GROUP(hsspi_cs1),
BCM6328_GROUP(usb_port1),
BCM_PIN_GROUP(hsspi_cs1),
BCM_PIN_GROUP(usb_port1),
};
/* GPIO_MODE */
@ -292,10 +279,10 @@ static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6328_groups[group].pins;
*num_pins = bcm6328_groups[group].num_pins;
*npins = bcm6328_groups[group].npins;
return 0;
}
@ -338,7 +325,7 @@ static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6328_pingroup *pg = &bcm6328_groups[group];
const struct pingroup *pg = &bcm6328_groups[group];
const struct bcm6328_function *f = &bcm6328_funcs[selector];
bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);

20
drivers/pinctrl/bcm/pinctrl-bcm6358.c
View File

@ -35,9 +35,7 @@
#define BCM6358_MODE_MUX_SYS_IRQ BIT(15)
struct bcm6358_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
struct pingroup grp;
const uint16_t mode_val;
@ -131,9 +129,7 @@ static unsigned sys_irq_grp_pins[] = { 5 };
#define BCM6358_GPIO_MUX_GROUP(n, bit, dir) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
.grp = BCM_PIN_GROUP(n), \
.mode_val = BCM6358_MODE_MUX_##bit, \
.direction = dir, \
}
@ -219,15 +215,15 @@ static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6358_groups[group].name;
return bcm6358_groups[group].grp.name;
}
static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6358_groups[group].pins;
*num_pins = bcm6358_groups[group].num_pins;
*pins = bcm6358_groups[group].grp.pins;
*npins = bcm6358_groups[group].grp.npins;
return 0;
}
@ -264,12 +260,12 @@ static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int mask = val;
unsigned pin;
for (pin = 0; pin < pg->num_pins; pin++)
for (pin = 0; pin < pg->grp.npins; pin++)
mask |= (unsigned long)bcm6358_pins[pin].drv_data;
regmap_field_update_bits(priv->overlays, mask, val);
for (pin = 0; pin < pg->num_pins; pin++) {
for (pin = 0; pin < pg->grp.npins; pin++) {
struct pinctrl_gpio_range *range;
unsigned int hw_gpio = bcm6358_pins[pin].number;

121
drivers/pinctrl/bcm/pinctrl-bcm6362.c
View File

@ -35,12 +35,6 @@ enum bcm6362_pinctrl_reg {
BCM6362_BASEMODE,
};
struct bcm6362_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6362_function {
const char *name;
const char * const *groups;
@ -162,63 +156,56 @@ static unsigned nand_grp_pins[] = {
18, 19, 20, 21, 22, 23, 27,
};
#define BCM6362_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6362_pingroup bcm6362_groups[] = {
BCM6362_GROUP(gpio0),
BCM6362_GROUP(gpio1),
BCM6362_GROUP(gpio2),
BCM6362_GROUP(gpio3),
BCM6362_GROUP(gpio4),
BCM6362_GROUP(gpio5),
BCM6362_GROUP(gpio6),
BCM6362_GROUP(gpio7),
BCM6362_GROUP(gpio8),
BCM6362_GROUP(gpio9),
BCM6362_GROUP(gpio10),
BCM6362_GROUP(gpio11),
BCM6362_GROUP(gpio12),
BCM6362_GROUP(gpio13),
BCM6362_GROUP(gpio14),
BCM6362_GROUP(gpio15),
BCM6362_GROUP(gpio16),
BCM6362_GROUP(gpio17),
BCM6362_GROUP(gpio18),
BCM6362_GROUP(gpio19),
BCM6362_GROUP(gpio20),
BCM6362_GROUP(gpio21),
BCM6362_GROUP(gpio22),
BCM6362_GROUP(gpio23),
BCM6362_GROUP(gpio24),
BCM6362_GROUP(gpio25),
BCM6362_GROUP(gpio26),
BCM6362_GROUP(gpio27),
BCM6362_GROUP(gpio28),
BCM6362_GROUP(gpio29),
BCM6362_GROUP(gpio30),
BCM6362_GROUP(gpio31),
BCM6362_GROUP(gpio32),
BCM6362_GROUP(gpio33),
BCM6362_GROUP(gpio34),
BCM6362_GROUP(gpio35),
BCM6362_GROUP(gpio36),
BCM6362_GROUP(gpio37),
BCM6362_GROUP(gpio38),
BCM6362_GROUP(gpio39),
BCM6362_GROUP(gpio40),
BCM6362_GROUP(gpio41),
BCM6362_GROUP(gpio42),
BCM6362_GROUP(gpio43),
BCM6362_GROUP(gpio44),
BCM6362_GROUP(gpio45),
BCM6362_GROUP(gpio46),
BCM6362_GROUP(gpio47),
BCM6362_GROUP(nand_grp),
static struct pingroup bcm6362_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(nand_grp),
};
static const char * const led_groups[] = {
@ -463,10 +450,10 @@ static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6362_groups[group].pins;
*num_pins = bcm6362_groups[group].num_pins;
*npins = bcm6362_groups[group].npins;
return 0;
}
@ -519,13 +506,13 @@ static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6362_pingroup *pg = &bcm6362_groups[group];
const struct pingroup *pg = &bcm6362_groups[group];
const struct bcm6362_function *f = &bcm6362_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->num_pins; i++)
for (i = 0; i < pg->npins; i++)
bcm6362_set_gpio(pc, pg->pins[i]);
switch (f->reg) {

91
drivers/pinctrl/bcm/pinctrl-bcm6368.c
View File

@ -26,12 +26,6 @@
#define BCM6368_BASEMODE_GPIO 0x0
#define BCM6368_BASEMODE_UART1 0x1
struct bcm6368_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6368_function {
const char *name;
const char * const *groups;
@ -127,47 +121,40 @@ static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
#define BCM6368_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6368_pingroup bcm6368_groups[] = {
BCM6368_GROUP(gpio0),
BCM6368_GROUP(gpio1),
BCM6368_GROUP(gpio2),
BCM6368_GROUP(gpio3),
BCM6368_GROUP(gpio4),
BCM6368_GROUP(gpio5),
BCM6368_GROUP(gpio6),
BCM6368_GROUP(gpio7),
BCM6368_GROUP(gpio8),
BCM6368_GROUP(gpio9),
BCM6368_GROUP(gpio10),
BCM6368_GROUP(gpio11),
BCM6368_GROUP(gpio12),
BCM6368_GROUP(gpio13),
BCM6368_GROUP(gpio14),
BCM6368_GROUP(gpio15),
BCM6368_GROUP(gpio16),
BCM6368_GROUP(gpio17),
BCM6368_GROUP(gpio18),
BCM6368_GROUP(gpio19),
BCM6368_GROUP(gpio20),
BCM6368_GROUP(gpio21),
BCM6368_GROUP(gpio22),
BCM6368_GROUP(gpio23),
BCM6368_GROUP(gpio24),
BCM6368_GROUP(gpio25),
BCM6368_GROUP(gpio26),
BCM6368_GROUP(gpio27),
BCM6368_GROUP(gpio28),
BCM6368_GROUP(gpio29),
BCM6368_GROUP(gpio30),
BCM6368_GROUP(gpio31),
BCM6368_GROUP(uart1_grp),
static struct pingroup bcm6368_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(uart1_grp),
};
static const char * const analog_afe_0_groups[] = {
@ -358,10 +345,10 @@ static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6368_groups[group].pins;
*num_pins = bcm6368_groups[group].num_pins;
*npins = bcm6368_groups[group].npins;
return 0;
}
@ -393,14 +380,14 @@ static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6368_priv *priv = pc->driver_data;
const struct bcm6368_pingroup *pg = &bcm6368_groups[group];
const struct pingroup *pg = &bcm6368_groups[group];
const struct bcm6368_function *fun = &bcm6368_funcs[selector];
int i, pin;
if (fun->basemode) {
unsigned int mask = 0;
for (i = 0; i < pg->num_pins; i++) {
for (i = 0; i < pg->npins; i++) {
pin = pg->pins[i];
if (pin < BCM63XX_BANK_GPIOS)
mask |= BIT(pin);
@ -419,7 +406,7 @@ static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
BIT(pin));
}
for (pin = 0; pin < pg->num_pins; pin++) {
for (pin = 0; pin < pg->npins; pin++) {
struct pinctrl_gpio_range *range;
int hw_gpio = bcm6368_pins[pin].number;

2
drivers/pinctrl/bcm/pinctrl-bcm63xx.h
View File

@ -21,6 +21,8 @@ struct bcm63xx_pinctrl_soc {
unsigned int ngpios;
};
#define BCM_PIN_GROUP(n) PINCTRL_PINGROUP(#n, n##_pins, ARRAY_SIZE(n##_pins))
struct bcm63xx_pinctrl {
struct device *dev;
struct regmap *regs;

4
drivers/pinctrl/bcm/pinctrl-ns.c
View File

@ -233,10 +233,8 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"cru_gpio_control");
ns_pinctrl->base = devm_ioremap_resource(dev, res);
if (IS_ERR(ns_pinctrl->base)) {
dev_err(dev, "Failed to map pinctrl regs\n");
if (IS_ERR(ns_pinctrl->base))
return PTR_ERR(ns_pinctrl->base);
}
memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));

2
drivers/pinctrl/berlin/berlin.c
View File

@ -209,7 +209,7 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
for (i = 0; i < pctrl->desc->ngroups; i++) {
desc_group = pctrl->desc->groups + i;
/* compute the maxiumum number of functions a group can have */
/* compute the maximum number of functions a group can have */
max_functions += 1 << (desc_group->bit_width + 1);
}

12
drivers/pinctrl/freescale/Kconfig
View File

@ -119,28 +119,32 @@ config PINCTRL_IMX7ULP
config PINCTRL_IMX8MM
tristate "IMX8MM pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mm pinctrl driver
config PINCTRL_IMX8MN
tristate "IMX8MN pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mn pinctrl driver
config PINCTRL_IMX8MP
tristate "IMX8MP pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mp pinctrl driver
config PINCTRL_IMX8MQ
tristate "IMX8MQ pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mq pinctrl driver

12
drivers/pinctrl/mediatek/Kconfig
View File

@ -162,6 +162,18 @@ config PINCTRL_MT8186
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8188
bool "MediaTek MT8188 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
help
Say yes here to support pin controller and gpio driver
on MediaTek MT8188 SoC.
In MTK platform, we support virtual gpio and use it to
map specific eint which doesn't have real gpio pin.
config PINCTRL_MT8192
bool "Mediatek MT8192 pin control"
depends on OF

1
drivers/pinctrl/mediatek/Makefile
View File

@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o

1673
drivers/pinctrl/mediatek/pinctrl-mt8188.c Normal file
View File

File diff suppressed because it is too large Load Diff

2259
drivers/pinctrl/mediatek/pinctrl-mtk-mt8188.h Normal file
View File

File diff suppressed because it is too large Load Diff

7
drivers/pinctrl/meson/pinctrl-meson.c
View File

@ -608,6 +608,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc)
pc->chip.label = pc->data->name;
pc->chip.parent = pc->dev;
pc->chip.fwnode = pc->fwnode;
pc->chip.request = gpiochip_generic_request;
pc->chip.free = gpiochip_generic_free;
pc->chip.set_config = gpiochip_generic_config;
@ -619,8 +620,6 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc)
pc->chip.base = -1;
pc->chip.ngpio = pc->data->num_pins;
pc->chip.can_sleep = false;
pc->chip.of_node = pc->of_node;
pc->chip.of_gpio_n_cells = 2;
ret = gpiochip_add_data(&pc->chip, pc);
if (ret) {
@ -678,8 +677,8 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc)
return -EINVAL;
}
gpio_np = to_of_node(gpiochip_node_get_first(pc->dev));
pc->of_node = gpio_np;
pc->fwnode = gpiochip_node_get_first(pc->dev);
gpio_np = to_of_node(pc->fwnode);
pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
if (IS_ERR_OR_NULL(pc->reg_mux)) {

4
drivers/pinctrl/meson/pinctrl-meson.h
View File

@ -12,6 +12,8 @@
#include <linux/types.h>
#include <linux/module.h>
struct fwnode_handle;
struct meson_pinctrl;
/**
@ -131,7 +133,7 @@ struct meson_pinctrl {
struct regmap *reg_gpio;
struct regmap *reg_ds;
struct gpio_chip chip;
struct device_node *of_node;
struct fwnode_handle *fwnode;
};
#define FUNCTION(fn) \

26
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View File

@ -112,14 +112,14 @@ struct armada_37xx_pinctrl {
struct armada_37xx_pm_state pm;
};
#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
#define PIN_GRP_GPIO_0(_name, _start, _nr) \
{ \
.name = _name, \
.start_pin = _start, \
.npins = _nr, \
.reg_mask = _mask, \
.val = {0, _mask}, \
.funcs = {_func1, _func2} \
.reg_mask = 0, \
.val = {0}, \
.funcs = {"gpio"} \
}
#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
@ -179,6 +179,7 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
"pwm", "led"),
PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
PIN_GRP_GPIO_0("gpio1_5", 5, 1),
PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
@ -195,15 +196,18 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
PIN_GRP_GPIO_0("gpio2_2", 2, 1),
PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"),
PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12),
"ptp", "mii"),
PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13),
"ptp", "mii"),
PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
"mii", "mii_err"),
};
@ -486,11 +490,15 @@ static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct armada_37xx_pin_group *group;
int grp = 0;
int ret;
dev_dbg(info->dev, "requesting gpio %d\n", offset);
while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) {
ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
if (ret)
return ret;
}
return 0;
}

295
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
View File

@ -674,163 +674,160 @@ static const unsigned hwobs_oc4_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
#define DB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
static const struct nmk_pingroup nmk_db8500_groups[] = {
/* Altfunction A column */
DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc0_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc0_dat47_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc0dat31dir_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d12_d15_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc2_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(modem_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc1dir_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc0_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc0_dat47_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc0dat31dir_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(lcd_d12_d15_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc2_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(modem_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mc1dir_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
/* Altfunction B column */
DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcd_d16_d23_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(lcd_d16_d23_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
/* Altfunction C column */
DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(clkout1_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(clkout2_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(clkout1_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(clkout2_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
/* Other alt C1 column */
DB8500_PIN_GROUP(u2rx_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(ptma9_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(rf_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(hxclk_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(uartmodrx_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(uartmodtx_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(stmmod_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(hxgpio_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(rf_oc1_2, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C1),
DB8500_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(u2rx_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(ptma9_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(rf_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(hxclk_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(uartmodrx_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(uartmodtx_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(stmmod_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(hxgpio_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(rf_oc1_2, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C1),
NMK_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C1),
/* Other alt C2 column */
DB8500_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2),
DB8500_PIN_GROUP(etmr4_oc2_1, NMK_GPIO_ALT_C2),
DB8500_PIN_GROUP(ptma9_oc2_1, NMK_GPIO_ALT_C2),
NMK_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2),
NMK_PIN_GROUP(etmr4_oc2_1, NMK_GPIO_ALT_C2),
NMK_PIN_GROUP(ptma9_oc2_1, NMK_GPIO_ALT_C2),
/* Other alt C3 column */
DB8500_PIN_GROUP(stmmod_oc3_1, NMK_GPIO_ALT_C3),
DB8500_PIN_GROUP(stmmod_oc3_2, NMK_GPIO_ALT_C3),
DB8500_PIN_GROUP(uartmodrx_oc3_1, NMK_GPIO_ALT_C3),
DB8500_PIN_GROUP(uartmodtx_oc3_1, NMK_GPIO_ALT_C3),
DB8500_PIN_GROUP(etmr4_oc3_1, NMK_GPIO_ALT_C3),
NMK_PIN_GROUP(stmmod_oc3_1, NMK_GPIO_ALT_C3),
NMK_PIN_GROUP(stmmod_oc3_2, NMK_GPIO_ALT_C3),
NMK_PIN_GROUP(uartmodrx_oc3_1, NMK_GPIO_ALT_C3),
NMK_PIN_GROUP(uartmodtx_oc3_1, NMK_GPIO_ALT_C3),
NMK_PIN_GROUP(etmr4_oc3_1, NMK_GPIO_ALT_C3),
/* Other alt C4 column */
DB8500_PIN_GROUP(sbag_oc4_1, NMK_GPIO_ALT_C4),
DB8500_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4),
NMK_PIN_GROUP(sbag_oc4_1, NMK_GPIO_ALT_C4),
NMK_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4),
};
/* We use this macro to define the groups applicable to a function */

29
drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
View File

@ -303,23 +303,20 @@ static const unsigned usbhs_c_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20,
STN8815_PIN_C16, STN8815_PIN_A15,
STN8815_PIN_D17, STN8815_PIN_C17 };
#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
static const struct nmk_pingroup nmk_stn8815_groups[] = {
STN8815_PIN_GROUP(u0txrx_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u0ctsrts_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u0modem_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(mmcsd_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(usbfs_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(usbhs_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(u0txrx_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u0ctsrts_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u0modem_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mmcsd_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(usbfs_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(usbhs_c_1, NMK_GPIO_ALT_C),
};
/* We use this macro to define the groups applicable to a function */

117
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -244,7 +244,6 @@ enum nmk_gpio_slpm {
struct nmk_gpio_chip {
struct gpio_chip chip;
struct irq_chip irqchip;
void __iomem *addr;
struct clk *clk;
unsigned int bank;
@ -608,8 +607,8 @@ static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev,
static void nmk_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
clk_enable(nmk_chip->clk);
writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
@ -675,15 +674,11 @@ static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
__nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
}
static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip,
struct irq_data *d, bool enable)
{
struct nmk_gpio_chip *nmk_chip;
unsigned long flags;
nmk_chip = irq_data_get_irq_chip_data(d);
if (!nmk_chip)
return -EINVAL;
clk_enable(nmk_chip->clk);
spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
spin_lock(&nmk_chip->lock);
@ -696,29 +691,32 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
spin_unlock(&nmk_chip->lock);
spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
clk_disable(nmk_chip->clk);
return 0;
}
static void nmk_gpio_irq_mask(struct irq_data *d)
{
nmk_gpio_irq_maskunmask(d, false);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
nmk_gpio_irq_maskunmask(nmk_chip, d, false);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void nmk_gpio_irq_unmask(struct irq_data *d)
{
nmk_gpio_irq_maskunmask(d, true);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
nmk_gpio_irq_maskunmask(nmk_chip, d, true);
}
static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct nmk_gpio_chip *nmk_chip;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
unsigned long flags;
nmk_chip = irq_data_get_irq_chip_data(d);
if (!nmk_chip)
return -EINVAL;
clk_enable(nmk_chip->clk);
spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
spin_lock(&nmk_chip->lock);
@ -740,14 +738,12 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
bool enabled = !irqd_irq_disabled(d);
bool wake = irqd_is_wakeup_set(d);
struct nmk_gpio_chip *nmk_chip;
unsigned long flags;
nmk_chip = irq_data_get_irq_chip_data(d);
if (!nmk_chip)
return -EINVAL;
if (type & IRQ_TYPE_LEVEL_HIGH)
return -EINVAL;
if (type & IRQ_TYPE_LEVEL_LOW)
@ -784,7 +780,8 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
{
struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
clk_enable(nmk_chip->clk);
nmk_gpio_irq_unmask(d);
@ -793,7 +790,8 @@ static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
static void nmk_gpio_irq_shutdown(struct irq_data *d)
{
struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
nmk_gpio_irq_mask(d);
clk_disable(nmk_chip->clk);
@ -1078,13 +1076,34 @@ static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
return nmk_chip;
}
static void nmk_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank,
gc->base, gc->base + gc->ngpio - 1);
}
static const struct irq_chip nmk_irq_chip = {
.irq_ack = nmk_gpio_irq_ack,
.irq_mask = nmk_gpio_irq_mask,
.irq_unmask = nmk_gpio_irq_unmask,
.irq_set_type = nmk_gpio_irq_set_type,
.irq_set_wake = nmk_gpio_irq_set_wake,
.irq_startup = nmk_gpio_irq_startup,
.irq_shutdown = nmk_gpio_irq_shutdown,
.irq_print_chip = nmk_gpio_irq_print_chip,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int nmk_gpio_probe(struct platform_device *dev)
{
struct device_node *np = dev->dev.of_node;
struct nmk_gpio_chip *nmk_chip;
struct gpio_chip *chip;
struct gpio_irq_chip *girq;
struct irq_chip *irqchip;
bool supports_sleepmode;
int irq;
int ret;
@ -1125,22 +1144,8 @@ static int nmk_gpio_probe(struct platform_device *dev)
chip->can_sleep = false;
chip->owner = THIS_MODULE;
irqchip = &nmk_chip->irqchip;
irqchip->irq_ack = nmk_gpio_irq_ack;
irqchip->irq_mask = nmk_gpio_irq_mask;
irqchip->irq_unmask = nmk_gpio_irq_unmask;
irqchip->irq_set_type = nmk_gpio_irq_set_type;
irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
irqchip->irq_startup = nmk_gpio_irq_startup;
irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
dev->id,
chip->base,
chip->base + chip->ngpio - 1);
girq = &chip->irq;
girq->chip = irqchip;
gpio_irq_chip_set_chip(girq, &nmk_irq_chip);
girq->parent_handler = nmk_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&dev->dev, 1,
@ -1179,17 +1184,17 @@ static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
return npct->soc->groups[selector].name;
return npct->soc->groups[selector].grp.name;
}
static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
*pins = npct->soc->groups[selector].pins;
*num_pins = npct->soc->groups[selector].npins;
*pins = npct->soc->groups[selector].grp.pins;
*npins = npct->soc->groups[selector].grp.npins;
return 0;
}
@ -1531,7 +1536,7 @@ static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
if (g->altsetting < 0)
return -EINVAL;
dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
dev_dbg(npct->dev, "enable group %s, %u pins\n", g->grp.name, g->grp.npins);
/*
* If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
@ -1566,26 +1571,26 @@ static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
* Then mask the pins that need to be sleeping now when we're
* switching to the ALT C function.
*/
for (i = 0; i < g->npins; i++)
slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
for (i = 0; i < g->grp.npins; i++)
slpm[g->grp.pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->grp.pins[i]);
nmk_gpio_glitch_slpm_init(slpm);
}
for (i = 0; i < g->npins; i++) {
for (i = 0; i < g->grp.npins; i++) {
struct nmk_gpio_chip *nmk_chip;
unsigned bit;
nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i]);
if (!nmk_chip) {
dev_err(npct->dev,
"invalid pin offset %d in group %s at index %d\n",
g->pins[i], g->name, i);
g->grp.pins[i], g->grp.name, i);
goto out_glitch;
}
dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->grp.pins[i], g->altsetting);
clk_enable(nmk_chip->clk);
bit = g->pins[i] % NMK_GPIO_PER_CHIP;
bit = g->grp.pins[i] % NMK_GPIO_PER_CHIP;
/*
* If the pin is switching to altfunc, and there was an
* interrupt installed on it which has been lazy disabled,
@ -1608,7 +1613,7 @@ static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
* then some bits in PRCM GPIOCR registers must be cleared.
*/
if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
nmk_prcm_altcx_set_mode(npct, g->pins[i],
nmk_prcm_altcx_set_mode(npct, g->grp.pins[i],
g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
}
@ -1802,10 +1807,6 @@ static const struct of_device_id nmk_pinctrl_match[] = {
.compatible = "stericsson,db8500-pinctrl",
.data = (void *)PINCTRL_NMK_DB8500,
},
{
.compatible = "stericsson,db8540-pinctrl",
.data = (void *)PINCTRL_NMK_DB8540,
},
{},
};
@ -1856,8 +1857,6 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
nmk_pinctrl_stn8815_init(&npct->soc);
if (version == PINCTRL_NMK_DB8500)
nmk_pinctrl_db8500_init(&npct->soc);
if (version == PINCTRL_NMK_DB8540)
nmk_pinctrl_db8540_init(&npct->soc);
/*
* Since we depend on the GPIO chips to provide clock and register base

30
drivers/pinctrl/nomadik/pinctrl-nomadik.h
View File

@ -5,7 +5,6 @@
/* Package definitions */
#define PINCTRL_NMK_STN8815 0
#define PINCTRL_NMK_DB8500 1
#define PINCTRL_NMK_DB8540 2
/* Alternate functions: function C is set in hw by setting both A and B */
#define NMK_GPIO_ALT_GPIO 0
@ -105,21 +104,21 @@ struct nmk_function {
/**
* struct nmk_pingroup - describes a Nomadik pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @num_pins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @grp: Generic data of the pin group (name and pins)
* @altsetting: the altsetting to apply to all pins in this group to
* configure them to be used by a function
*/
struct nmk_pingroup {
const char *name;
const unsigned int *pins;
const unsigned npins;
struct pingroup grp;
int altsetting;
};
#define NMK_PIN_GROUP(a, b) \
{ \
.grp = PINCTRL_PINGROUP(#a, a##_pins, ARRAY_SIZE(a##_pins)), \
.altsetting = b, \
}
/**
* struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
* @pins: An array describing all pins the pin controller affects.
@ -173,17 +172,4 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
#endif
#ifdef CONFIG_PINCTRL_DB8540
void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
#else
static inline void
nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
{
}
#endif
#endif /* PINCTRL_PINCTRL_NOMADIK_H */

8
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@ -81,11 +81,11 @@ struct npcm7xx_gpio {
int irq;
struct irq_chip irq_chip;
u32 pinctrl_id;
int (*direction_input)(struct gpio_chip *chip, unsigned offset);
int (*direction_output)(struct gpio_chip *chip, unsigned offset,
int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
int value);
int (*request)(struct gpio_chip *chip, unsigned offset);
void (*free)(struct gpio_chip *chip, unsigned offset);
int (*request)(struct gpio_chip *chip, unsigned int offset);
void (*free)(struct gpio_chip *chip, unsigned int offset);
};
struct npcm7xx_pinctrl {

5
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
View File

@ -1081,10 +1081,13 @@ static int wpcm450_gpio_register(struct platform_device *pdev,
girq->num_parents = 0;
for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) {
int irq = fwnode_irq_get(child, i);
int irq;
irq = fwnode_irq_get(child, i);
if (irq < 0)
break;
if (!irq)
continue;
girq->parents[i] = irq;
girq->num_parents++;

26
drivers/pinctrl/pinctrl-amd.c
View File

@ -246,7 +246,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
}
seq_printf(s, "GPIO bank%d\n", bank);
for (; i < pin_num; i++) {
seq_printf(s, "📌%d\t", i);
seq_printf(s, "#%d\t", i);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + i * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
@ -278,32 +278,32 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
}
if (pin_reg & BIT(INTERRUPT_MASK_OFF))
interrupt_mask = "-";
interrupt_mask = "😛";
else
interrupt_mask = "+";
seq_printf(s, "int %s (🎭 %s)| active-%s| %s-🔫| ",
interrupt_mask = "😷";
seq_printf(s, "int %s (%s)| active-%s| %s-⚡| ",
interrupt_enable,
interrupt_mask,
active_level,
level_trig);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
wake_cntrl0 = "+";
wake_cntrl0 = "⏰";
else
wake_cntrl0 = " ∅";
seq_printf(s, "S0i3 🌅 %s| ", wake_cntrl0);
seq_printf(s, "S0i3 %s| ", wake_cntrl0);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
wake_cntrl1 = "+";
wake_cntrl1 = "⏰";
else
wake_cntrl1 = " ∅";
seq_printf(s, "S3 🌅 %s| ", wake_cntrl1);
seq_printf(s, "S3 %s| ", wake_cntrl1);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
wake_cntrl2 = "+";
wake_cntrl2 = "⏰";
else
wake_cntrl2 = " ∅";
seq_printf(s, "S4/S5 🌅 %s| ", wake_cntrl2);
seq_printf(s, "S4/S5 %s| ", wake_cntrl2);
if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
pull_up_enable = "+";
@ -367,7 +367,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
debounce_enable = " ∅";
}
snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit);
seq_printf(s, "debounce %s (⏰ %sus)| ", debounce_enable, debounce_value);
seq_printf(s, "debounce %s (🕑 %sus)| ", debounce_enable, debounce_value);
seq_printf(s, " 0x%x\n", pin_reg);
}
}
@ -1051,13 +1051,13 @@ static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
if (index < 0) {
dev_warn(dev, "failed to get iomux index\n");
dev_dbg(dev, "iomux not supported\n");
goto out_no_pinmux;
}
gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
if (IS_ERR(gpio_dev->iomux_base)) {
dev_warn(dev, "Failed to get iomux %d io resource\n", index);
dev_dbg(dev, "iomux not supported %d io resource\n", index);
goto out_no_pinmux;
}

105
drivers/pinctrl/pinctrl-at91.c
View File

@ -22,8 +22,7 @@
#include <linux/pinctrl/pinmux.h>
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
#include <soc/at91/pm.h>
#include <linux/pm.h>
#include "pinctrl-at91.h"
#include "core.h"
@ -33,16 +32,34 @@
struct at91_pinctrl_mux_ops;
/**
* struct at91_gpio_chip: at91 gpio chip
* @chip: gpio chip
* @range: gpio range
* @next: bank sharing same clock
* @pioc_hwirq: PIO bank interrupt identifier on AIC
* @pioc_virq: PIO bank Linux virtual interrupt
* @pioc_idx: PIO bank index
* @regbase: PIO bank virtual address
* @clock: associated clock
* @ops: at91 pinctrl mux ops
* @wakeups: wakeup interrupts
* @backups: interrupts disabled in suspend
* @id: gpio chip identifier
*/
struct at91_gpio_chip {
struct gpio_chip chip;
struct pinctrl_gpio_range range;
struct at91_gpio_chip *next; /* Bank sharing same clock */
int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
int pioc_virq; /* PIO bank Linux virtual interrupt */
int pioc_idx; /* PIO bank index */
void __iomem *regbase; /* PIO bank virtual address */
struct clk *clock; /* associated clock */
const struct at91_pinctrl_mux_ops *ops; /* ops */
struct at91_gpio_chip *next;
int pioc_hwirq;
int pioc_virq;
int pioc_idx;
void __iomem *regbase;
struct clk *clock;
const struct at91_pinctrl_mux_ops *ops;
u32 wakeups;
u32 backups;
u32 id;
};
static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
@ -1615,70 +1632,51 @@ static void gpio_irq_ack(struct irq_data *d)
/* the interrupt is already cleared before by reading ISR */
}
static u32 wakeups[MAX_GPIO_BANKS];
static u32 backups[MAX_GPIO_BANKS];
static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
unsigned bank = at91_gpio->pioc_idx;
unsigned mask = 1 << d->hwirq;
if (unlikely(bank >= MAX_GPIO_BANKS))
return -EINVAL;
if (state)
wakeups[bank] |= mask;
at91_gpio->wakeups |= mask;
else
wakeups[bank] &= ~mask;
at91_gpio->wakeups &= ~mask;
irq_set_irq_wake(at91_gpio->pioc_virq, state);
return 0;
}
void at91_pinctrl_gpio_suspend(void)
static int at91_gpio_suspend(struct device *dev)
{
int i;
struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
void __iomem *pio = at91_chip->regbase;
for (i = 0; i < gpio_banks; i++) {
void __iomem *pio;
at91_chip->backups = readl_relaxed(pio + PIO_IMR);
writel_relaxed(at91_chip->backups, pio + PIO_IDR);
writel_relaxed(at91_chip->wakeups, pio + PIO_IER);
if (!gpio_chips[i])
continue;
pio = gpio_chips[i]->regbase;
backups[i] = readl_relaxed(pio + PIO_IMR);
writel_relaxed(backups[i], pio + PIO_IDR);
writel_relaxed(wakeups[i], pio + PIO_IER);
if (!wakeups[i])
clk_disable_unprepare(gpio_chips[i]->clock);
if (!at91_chip->wakeups)
clk_disable_unprepare(at91_chip->clock);
else
printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
'A'+i, wakeups[i]);
}
dev_dbg(dev, "GPIO-%c may wake for %08x\n",
'A' + at91_chip->id, at91_chip->wakeups);
return 0;
}
void at91_pinctrl_gpio_resume(void)
static int at91_gpio_resume(struct device *dev)
{
int i;
struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
void __iomem *pio = at91_chip->regbase;
for (i = 0; i < gpio_banks; i++) {
void __iomem *pio;
if (!at91_chip->wakeups)
clk_prepare_enable(at91_chip->clock);
if (!gpio_chips[i])
continue;
writel_relaxed(at91_chip->wakeups, pio + PIO_IDR);
writel_relaxed(at91_chip->backups, pio + PIO_IER);
pio = gpio_chips[i]->regbase;
if (!wakeups[i])
clk_prepare_enable(gpio_chips[i]->clock);
writel_relaxed(wakeups[i], pio + PIO_IDR);
writel_relaxed(backups[i], pio + PIO_IER);
}
return 0;
}
static void gpio_irq_handler(struct irq_desc *desc)
@ -1860,6 +1858,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
}
at91_chip->chip = at91_gpio_template;
at91_chip->id = alias_idx;
chip = &at91_chip->chip;
chip->label = dev_name(&pdev->dev);
@ -1905,6 +1904,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
goto gpiochip_add_err;
gpio_chips[alias_idx] = at91_chip;
platform_set_drvdata(pdev, at91_chip);
gpio_banks = max(gpio_banks, alias_idx + 1);
dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
@ -1920,10 +1920,15 @@ err:
return ret;
}
static const struct dev_pm_ops at91_gpio_pm_ops = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume)
};
static struct platform_driver at91_gpio_driver = {
.driver = {
.name = "gpio-at91",
.of_match_table = at91_gpio_of_match,
.pm = pm_ptr(&at91_gpio_pm_ops),
},
.probe = at91_gpio_probe,
};

1419
drivers/pinctrl/pinctrl-cy8c95x0.c Normal file
View File

File diff suppressed because it is too large Load Diff

31
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -12,14 +12,14 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
@ -4152,7 +4152,7 @@ static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
};
static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
struct device_node *node)
struct fwnode_handle *fwnode)
{
struct ingenic_gpio_chip *jzgc;
struct device *dev = jzpc->dev;
@ -4160,7 +4160,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
unsigned int bank;
int err;
err = of_property_read_u32(node, "reg", &bank);
err = fwnode_property_read_u32(fwnode, "reg", &bank);
if (err) {
dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
return err;
@ -4185,7 +4185,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
jzgc->gc.ngpio = 32;
jzgc->gc.parent = dev;
jzgc->gc.of_node = node;
jzgc->gc.fwnode = fwnode;
jzgc->gc.owner = THIS_MODULE;
jzgc->gc.set = ingenic_gpio_set;
@ -4196,9 +4196,12 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
jzgc->gc.request = gpiochip_generic_request;
jzgc->gc.free = gpiochip_generic_free;
jzgc->irq = irq_of_parse_and_map(node, 0);
if (!jzgc->irq)
err = fwnode_irq_get(fwnode, 0);
if (err < 0)
return err;
if (!err)
return -EINVAL;
jzgc->irq = err;
girq = &jzgc->gc.irq;
gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);
@ -4227,12 +4230,12 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
struct pinctrl_desc *pctl_desc;
void __iomem *base;
const struct ingenic_chip_info *chip_info;
struct device_node *node;
struct regmap_config regmap_config;
struct fwnode_handle *fwnode;
unsigned int i;
int err;
chip_info = of_device_get_match_data(dev);
chip_info = device_get_match_data(dev);
if (!chip_info) {
dev_err(dev, "Unsupported SoC\n");
return -EINVAL;
@ -4319,11 +4322,11 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
dev_set_drvdata(dev, jzpc->map);
for_each_child_of_node(dev->of_node, node) {
if (of_match_node(ingenic_gpio_of_matches, node)) {
err = ingenic_gpio_probe(jzpc, node);
device_for_each_child_node(dev, fwnode) {
if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) {
err = ingenic_gpio_probe(jzpc, fwnode);
if (err) {
of_node_put(node);
fwnode_handle_put(fwnode);
return err;
}
}

3
drivers/pinctrl/pinctrl-mcp23s08.c
View File

@ -549,9 +549,6 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
mcp->chip.get = mcp23s08_get;
mcp->chip.direction_output = mcp23s08_direction_output;
mcp->chip.set = mcp23s08_set;
#ifdef CONFIG_OF_GPIO
mcp->chip.of_gpio_n_cells = 2;
#endif
mcp->chip.base = base;
mcp->chip.can_sleep = true;

5
drivers/pinctrl/pinctrl-microchip-sgpio.c
View File

@ -865,9 +865,10 @@ static int microchip_sgpio_register_bank(struct device *dev,
gc->can_sleep = !bank->is_input;
if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
int irq = fwnode_irq_get(fwnode, 0);
int irq;
if (irq) {
irq = fwnode_irq_get(fwnode, 0);
if (irq > 0) {
struct gpio_irq_chip *girq = &gc->irq;
gpio_irq_chip_set_chip(girq, &microchip_sgpio_irqchip);

2
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -2129,4 +2129,6 @@ static struct platform_driver ocelot_pinctrl_driver = {
.remove = ocelot_pinctrl_remove,
};
module_platform_driver(ocelot_pinctrl_driver);
MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver");
MODULE_LICENSE("Dual MIT/GPL");

27
drivers/pinctrl/pinctrl-pistachio.c
View File

@ -10,13 +10,13 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/mod_devicetable.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
@ -1347,46 +1347,51 @@ static struct pistachio_gpio_bank pistachio_gpio_banks[] = {
static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
{
struct device_node *node = pctl->dev->of_node;
struct pistachio_gpio_bank *bank;
unsigned int i;
int irq, ret = 0;
for (i = 0; i < pctl->nbanks; i++) {
char child_name[sizeof("gpioXX")];
struct device_node *child;
struct fwnode_handle *child;
struct gpio_irq_chip *girq;
snprintf(child_name, sizeof(child_name), "gpio%d", i);
child = of_get_child_by_name(node, child_name);
child = device_get_named_child_node(pctl->dev, child_name);
if (!child) {
dev_err(pctl->dev, "No node for bank %u\n", i);
ret = -ENODEV;
goto err;
}
if (!of_find_property(child, "gpio-controller", NULL)) {
if (!fwnode_property_present(child, "gpio-controller")) {
fwnode_handle_put(child);
dev_err(pctl->dev,
"No gpio-controller property for bank %u\n", i);
of_node_put(child);
ret = -ENODEV;
goto err;
}
irq = irq_of_parse_and_map(child, 0);
if (!irq) {
ret = fwnode_irq_get(child, 0);
if (ret < 0) {
fwnode_handle_put(child);
dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n", i);
goto err;
}
if (!ret) {
fwnode_handle_put(child);
dev_err(pctl->dev, "No IRQ for bank %u\n", i);
of_node_put(child);
ret = -EINVAL;
goto err;
}
irq = ret;
bank = &pctl->gpio_banks[i];
bank->pctl = pctl;
bank->base = pctl->base + GPIO_BANK_BASE(i);
bank->gpio_chip.parent = pctl->dev;
bank->gpio_chip.of_node = child;
bank->gpio_chip.fwnode = child;
girq = &bank->gpio_chip.irq;
girq->chip = &bank->irq_chip;

346
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -57,6 +57,7 @@
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
#define IOMUX_L_SOURCE_PMU BIT(6)
#define PIN_BANK(id, pins, label) \
{ \
@ -147,6 +148,21 @@
.pull_type[3] = pull3, \
}
#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
iom3, offset0, offset1, offset2, \
offset3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = offset0 }, \
{ .type = iom1, .offset = offset1 }, \
{ .type = iom2, .offset = offset2 }, \
{ .type = iom3, .offset = offset3 }, \
}, \
}
#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, offset0, offset1, \
@ -443,6 +459,37 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
},
};
static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
{
.num = 0,
.pin = 20,
.reg = 0x10000,
.bit = 0,
.mask = 0xf
},
{
.num = 0,
.pin = 21,
.reg = 0x10000,
.bit = 4,
.mask = 0xf
},
{
.num = 0,
.pin = 22,
.reg = 0x10000,
.bit = 8,
.mask = 0xf
},
{
.num = 0,
.pin = 23,
.reg = 0x10000,
.bit = 12,
.mask = 0xf
},
};
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
@ -642,6 +689,103 @@ static struct rockchip_mux_route_data px30_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
};
static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
};
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
@ -877,8 +1021,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? info->regmap_pmu : info->regmap_base;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = info->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
else
regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@ -987,8 +1135,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? info->regmap_pmu : info->regmap_base;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = info->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
else
regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@ -1268,6 +1420,119 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RV1126_PULL_PMU_OFFSET 0x40
#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
#define RV1126_PULL_PINS_PER_REG 8
#define RV1126_PULL_BITS_PER_PIN 2
#define RV1126_PULL_BANK_STRIDE 16
#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
*bit = pin_num % RV1126_PULL_PINS_PER_REG;
*bit *= RV1126_PULL_BITS_PER_PIN;
return 0;
}
*regmap = info->regmap_pmu;
*reg = RV1126_PULL_PMU_OFFSET;
} else {
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*regmap = info->regmap_base;
*reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
*bit *= RV1126_PULL_BITS_PER_PIN;
return 0;
}
#define RV1126_DRV_PMU_OFFSET 0x20
#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
#define RV1126_DRV_BITS_PER_PIN 4
#define RV1126_DRV_PINS_PER_REG 4
#define RV1126_DRV_BANK_STRIDE 32
static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
*reg -= 0x4;
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
return 0;
}
*regmap = info->regmap_pmu;
*reg = RV1126_DRV_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
return 0;
}
#define RV1126_SCHMITT_PMU_OFFSET 0x60
#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
#define RV1126_SCHMITT_BANK_STRIDE 16
#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int pins_per_reg;
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
*bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
return 0;
}
*regmap = info->regmap_pmu;
*reg = RV1126_SCHMITT_PMU_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
} else {
*regmap = info->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
*reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / pins_per_reg) * 4);
*bit = pin_num % pins_per_reg;
return 0;
}
#define RK3308_SCHMITT_PINS_PER_REG 8
#define RK3308_SCHMITT_BANK_STRIDE 16
#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
@ -1998,6 +2263,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
goto config;
}
if (ctrl->type == RV1126) {
rmask_bits = RV1126_DRV_BITS_PER_PIN;
ret = strength;
goto config;
}
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
@ -2168,6 +2439,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1108:
case RV1126:
case RK3188:
case RK3288:
case RK3308:
@ -2393,11 +2665,24 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset,
bool input)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct rockchip_pin_bank *bank;
bank = pin_to_bank(info, offset);
return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
}
static const struct pinmux_ops rockchip_pmx_ops = {
.get_functions_count = rockchip_pmx_get_funcs_count,
.get_function_name = rockchip_pmx_get_func_name,
.get_function_groups = rockchip_pmx_get_groups,
.set_mux = rockchip_pmx_set,
.gpio_set_direction = rockchip_pmx_gpio_set_direction,
};
/*
@ -2416,6 +2701,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1108:
case RV1126:
case RK3188:
case RK3288:
case RK3308:
@ -2889,12 +3175,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
if (iom->type & IOMUX_SOURCE_PMU)
if ((iom->type & IOMUX_SOURCE_PMU) ||
(iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
(iom->type & IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
@ -2919,7 +3207,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
inc = (iom->type & (IOMUX_WIDTH_4BIT |
IOMUX_WIDTH_3BIT |
IOMUX_WIDTH_2BIT)) ? 8 : 4;
if (iom->type & IOMUX_SOURCE_PMU)
if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs += inc;
else
grf_offs += inc;
@ -3178,6 +3466,48 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1126_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x10010, 0x10018, 0x10020, 0x10028),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
IOMUX_WIDTH_4BIT, 0, 0, 0),
};
static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
.pin_banks = rv1126_pin_banks,
.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
.label = "RV1126-GPIO",
.type = RV1126,
.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
.pmu_mux_offset = 0x0,
.iomux_routes = rv1126_mux_route_data,
.niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
.iomux_recalced = rv1126_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
.pull_calc_reg = rv1126_calc_pull_reg_and_bit,
.drv_calc_reg = rv1126_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@ -3568,6 +3898,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
{ .compatible = "rockchip,rv1126-pinctrl",
.data = &rv1126_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = &rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",

1
drivers/pinctrl/pinctrl-rockchip.h
View File

@ -186,6 +186,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1108,
RV1126,
RK2928,
RK3066B,
RK3128,

34
drivers/pinctrl/pinctrl-st.c
View File

@ -12,7 +12,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h> /* of_get_named_gpio() */
#include <linux/of_address.h>
#include <linux/gpio/driver.h>
#include <linux/regmap.h>
@ -1162,6 +1161,31 @@ static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
return;
}
static int st_pctl_dt_calculate_pin(struct st_pinctrl *info,
phandle bank, unsigned int offset)
{
struct device_node *np;
struct gpio_chip *chip;
int retval = -EINVAL;
int i;
np = of_find_node_by_phandle(bank);
if (!np)
return -EINVAL;
for (i = 0; i < info->nbanks; i++) {
chip = &info->banks[i].gpio_chip;
if (chip->of_node == np) {
if (offset < chip->ngpio)
retval = chip->base + offset;
break;
}
}
of_node_put(np);
return retval;
}
/*
* Each pin is represented in of the below forms.
* <bank offset mux direction rt_type rt_delay rt_clk>
@ -1175,6 +1199,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
struct device *dev = info->dev;
struct st_pinconf *conf;
struct device_node *pins;
phandle bank;
unsigned int offset;
int i = 0, npins = 0, nr_props, ret = 0;
pins = of_get_child_by_name(np, "st,pins");
@ -1214,9 +1240,9 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
conf = &grp->pin_conf[i];
/* bank & offset */
be32_to_cpup(list++);
be32_to_cpup(list++);
conf->pin = of_get_named_gpio(pins, pp->name, 0);
bank = be32_to_cpup(list++);
offset = be32_to_cpup(list++);
conf->pin = st_pctl_dt_calculate_pin(info, bank, offset);
conf->name = pp->name;
grp->pins[i] = conf->pin;
/* mux */

57
drivers/pinctrl/qcom/Kconfig
View File

@ -15,6 +15,7 @@ config PINCTRL_MSM
config PINCTRL_APQ8064
tristate "Qualcomm APQ8064 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -23,6 +24,7 @@ config PINCTRL_APQ8064
config PINCTRL_APQ8084
tristate "Qualcomm APQ8084 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -31,6 +33,7 @@ config PINCTRL_APQ8084
config PINCTRL_IPQ4019
tristate "Qualcomm IPQ4019 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -39,6 +42,7 @@ config PINCTRL_IPQ4019
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -47,6 +51,7 @@ config PINCTRL_IPQ8064
config PINCTRL_IPQ8074
tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
@ -57,6 +62,7 @@ config PINCTRL_IPQ8074
config PINCTRL_IPQ6018
tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
@ -67,6 +73,7 @@ config PINCTRL_IPQ6018
config PINCTRL_MSM8226
tristate "Qualcomm 8226 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -76,6 +83,7 @@ config PINCTRL_MSM8226
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -84,6 +92,7 @@ config PINCTRL_MSM8660
config PINCTRL_MSM8960
tristate "Qualcomm 8960 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -100,6 +109,7 @@ config PINCTRL_MDM9607
config PINCTRL_MDM9615
tristate "Qualcomm 9615 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -108,6 +118,7 @@ config PINCTRL_MDM9615
config PINCTRL_MSM8X74
tristate "Qualcomm 8x74 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -116,6 +127,7 @@ config PINCTRL_MSM8X74
config PINCTRL_MSM8909
tristate "Qualcomm 8909 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -132,6 +144,7 @@ config PINCTRL_MSM8916
config PINCTRL_MSM8953
tristate "Qualcomm 8953 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -142,6 +155,7 @@ config PINCTRL_MSM8953
config PINCTRL_MSM8976
tristate "Qualcomm 8976 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -152,6 +166,7 @@ config PINCTRL_MSM8976
config PINCTRL_MSM8994
tristate "Qualcomm 8994 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -161,6 +176,7 @@ config PINCTRL_MSM8994
config PINCTRL_MSM8996
tristate "Qualcomm MSM8996 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -169,6 +185,7 @@ config PINCTRL_MSM8996
config PINCTRL_MSM8998
tristate "Qualcomm MSM8998 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -177,6 +194,7 @@ config PINCTRL_MSM8998
config PINCTRL_QCM2290
tristate "Qualcomm QCM2290 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -185,6 +203,7 @@ config PINCTRL_QCM2290
config PINCTRL_QCS404
tristate "Qualcomm QCS404 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -232,6 +251,7 @@ config PINCTRL_QCOM_SSBI_PMIC
config PINCTRL_SC7180
tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -241,6 +261,7 @@ config PINCTRL_SC7180
config PINCTRL_SC7280
tristate "Qualcomm Technologies Inc SC7280 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -250,6 +271,7 @@ config PINCTRL_SC7280
config PINCTRL_SC7280_LPASS_LPI
tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -259,6 +281,7 @@ config PINCTRL_SC7280_LPASS_LPI
config PINCTRL_SC8180X
tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
depends on (OF || ACPI)
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -268,6 +291,7 @@ config PINCTRL_SC8180X
config PINCTRL_SC8280XP
tristate "Qualcomm Technologies Inc SC8280xp pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -277,6 +301,7 @@ config PINCTRL_SC8280XP
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -286,6 +311,7 @@ config PINCTRL_SDM660
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
depends on (OF || ACPI)
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -295,6 +321,7 @@ config PINCTRL_SDM845
config PINCTRL_SDX55
tristate "Qualcomm Technologies Inc SDX55 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -304,6 +331,7 @@ config PINCTRL_SDX55
config PINCTRL_SM6115
tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -313,6 +341,7 @@ config PINCTRL_SM6115
config PINCTRL_SM6125
tristate "Qualcomm Technologies Inc SM6125 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -322,6 +351,7 @@ config PINCTRL_SM6125
config PINCTRL_SM6350
tristate "Qualcomm Technologies Inc SM6350 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -331,6 +361,7 @@ config PINCTRL_SM6350
config PINCTRL_SM6375
tristate "Qualcomm Technologies Inc SM6375 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -340,6 +371,7 @@ config PINCTRL_SM6375
config PINCTRL_SDX65
tristate "Qualcomm Technologies Inc SDX65 pin controller driver"
depends on GPIOLIB && OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -349,6 +381,7 @@ config PINCTRL_SDX65
config PINCTRL_SM8150
tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -358,6 +391,7 @@ config PINCTRL_SM8150
config PINCTRL_SM8250
tristate "Qualcomm Technologies Inc SM8250 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -367,6 +401,7 @@ config PINCTRL_SM8250
config PINCTRL_SM8250_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -375,6 +410,7 @@ config PINCTRL_SM8250_LPASS_LPI
config PINCTRL_SM8350
tristate "Qualcomm Technologies Inc SM8350 pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@ -384,12 +420,33 @@ config PINCTRL_SM8350
config PINCTRL_SM8450
tristate "Qualcomm Technologies Inc SM8450 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8450 platform.
config PINCTRL_SM8450_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform.
config PINCTRL_SC8280XP_LPASS_LPI
tristate "Qualcomm Technologies Inc SC8280XP LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform.
config PINCTRL_LPASS_LPI
tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
select PINMUX

2
drivers/pinctrl/qcom/Makefile
View File

@ -45,4 +45,6 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o
obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o

207
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c Normal file
View File

@ -0,0 +1,207 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Linaro Ltd.
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_dmic4_clk,
LPI_MUX_dmic4_data,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_i2s3_clk,
LPI_MUX_i2s3_data,
LPI_MUX_i2s3_ws,
LPI_MUX_qua_mi2s_data,
LPI_MUX_qua_mi2s_sclk,
LPI_MUX_qua_mi2s_ws,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_wsa2_swr_clk,
LPI_MUX_wsa2_swr_data,
LPI_MUX_ext_mclk1_a,
LPI_MUX_ext_mclk1_b,
LPI_MUX_ext_mclk1_c,
LPI_MUX_gpio,
LPI_MUX__,
};
static int gpio0_pins[] = { 0 };
static int gpio1_pins[] = { 1 };
static int gpio2_pins[] = { 2 };
static int gpio3_pins[] = { 3 };
static int gpio4_pins[] = { 4 };
static int gpio5_pins[] = { 5 };
static int gpio6_pins[] = { 6 };
static int gpio7_pins[] = { 7 };
static int gpio8_pins[] = { 8 };
static int gpio9_pins[] = { 9 };
static int gpio10_pins[] = { 10 };
static int gpio11_pins[] = { 11 };
static int gpio12_pins[] = { 12 };
static int gpio13_pins[] = { 13 };
static int gpio14_pins[] = { 14 };
static int gpio15_pins[] = { 15 };
static int gpio16_pins[] = { 16 };
static int gpio17_pins[] = { 17 };
static int gpio18_pins[] = { 18 };
static const struct pinctrl_pin_desc sc8280xp_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
};
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const dmic4_clk_groups[] = { "gpio17" };
static const char * const dmic4_data_groups[] = { "gpio18" };
static const char * const i2s2_clk_groups[] = { "gpio10" };
static const char * const i2s2_ws_groups[] = { "gpio11" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
static const char * const i2s1_clk_groups[] = { "gpio6" };
static const char * const i2s1_ws_groups[] = { "gpio7" };
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_data_groups[] = { "gpio11" };
static const char * const wsa2_swr_clk_groups[] = { "gpio15" };
static const char * const wsa2_swr_data_groups[] = { "gpio16" };
static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" };
static const char * const i2s3_clk_groups[] = { "gpio12"};
static const char * const i2s3_ws_groups[] = { "gpio13"};
static const char * const i2s3_data_groups[] = { "gpio17", "gpio18"};
static const char * const ext_mclk1_c_groups[] = { "gpio5" };
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
static const char * const ext_mclk1_a_groups[] = { "gpio13" };
static const struct lpi_pingroup sc8280xp_groups[] = {
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, qua_mi2s_data, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _),
LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _),
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _),
LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _),
LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _),
LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _),
LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _),
};
static const struct lpi_function sc8280xp_functions[] = {
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(dmic4_clk),
LPI_FUNCTION(dmic4_data),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(i2s3_clk),
LPI_FUNCTION(i2s3_data),
LPI_FUNCTION(i2s3_ws),
LPI_FUNCTION(qua_mi2s_data),
LPI_FUNCTION(qua_mi2s_sclk),
LPI_FUNCTION(qua_mi2s_ws),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
LPI_FUNCTION(wsa2_swr_clk),
LPI_FUNCTION(wsa2_swr_data),
LPI_FUNCTION(ext_mclk1_a),
LPI_FUNCTION(ext_mclk1_b),
LPI_FUNCTION(ext_mclk1_c),
};
static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = {
.pins = sc8280xp_lpi_pins,
.npins = ARRAY_SIZE(sc8280xp_lpi_pins),
.groups = sc8280xp_groups,
.ngroups = ARRAY_SIZE(sc8280xp_groups),
.functions = sc8280xp_functions,
.nfunctions = ARRAY_SIZE(sc8280xp_functions),
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,sc8280xp-lpass-lpi-pinctrl",
.data = &sc8280xp_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-sc8280xp-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI SC8280XP LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

240
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c Normal file
View File

@ -0,0 +1,240 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Linaro Ltd.
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_dmic4_clk,
LPI_MUX_dmic4_data,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_i2s3_clk,
LPI_MUX_i2s3_data,
LPI_MUX_i2s3_ws,
LPI_MUX_i2s4_clk,
LPI_MUX_i2s4_data,
LPI_MUX_i2s4_ws,
LPI_MUX_qua_mi2s_data,
LPI_MUX_qua_mi2s_sclk,
LPI_MUX_qua_mi2s_ws,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_wsa2_swr_clk,
LPI_MUX_wsa2_swr_data,
LPI_MUX_slimbus_clk,
LPI_MUX_slimbus_data,
LPI_MUX_ext_mclk1_a,
LPI_MUX_ext_mclk1_b,
LPI_MUX_ext_mclk1_c,
LPI_MUX_ext_mclk1_d,
LPI_MUX_ext_mclk1_e,
LPI_MUX_gpio,
LPI_MUX__,
};
static int gpio0_pins[] = { 0 };
static int gpio1_pins[] = { 1 };
static int gpio2_pins[] = { 2 };
static int gpio3_pins[] = { 3 };
static int gpio4_pins[] = { 4 };
static int gpio5_pins[] = { 5 };
static int gpio6_pins[] = { 6 };
static int gpio7_pins[] = { 7 };
static int gpio8_pins[] = { 8 };
static int gpio9_pins[] = { 9 };
static int gpio10_pins[] = { 10 };
static int gpio11_pins[] = { 11 };
static int gpio12_pins[] = { 12 };
static int gpio13_pins[] = { 13 };
static int gpio14_pins[] = { 14 };
static int gpio15_pins[] = { 15 };
static int gpio16_pins[] = { 16 };
static int gpio17_pins[] = { 17 };
static int gpio18_pins[] = { 18 };
static int gpio19_pins[] = { 19 };
static int gpio20_pins[] = { 20 };
static int gpio21_pins[] = { 21 };
static int gpio22_pins[] = { 22 };
static const struct pinctrl_pin_desc sm8450_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
};
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" };
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const dmic4_clk_groups[] = { "gpio17" };
static const char * const dmic4_data_groups[] = { "gpio18" };
static const char * const i2s2_clk_groups[] = { "gpio10" };
static const char * const i2s2_ws_groups[] = { "gpio11" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
static const char * const i2s1_clk_groups[] = { "gpio6" };
static const char * const i2s1_ws_groups[] = { "gpio7" };
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_data_groups[] = { "gpio11" };
static const char * const wsa2_swr_clk_groups[] = { "gpio15" };
static const char * const wsa2_swr_data_groups[] = { "gpio16" };
static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" };
static const char * const i2s4_ws_groups[] = { "gpio13" };
static const char * const i2s4_clk_groups[] = { "gpio12" };
static const char * const i2s4_data_groups[] = { "gpio17", "gpio18" };
static const char * const slimbus_clk_groups[] = { "gpio19"};
static const char * const i2s3_clk_groups[] = { "gpio19"};
static const char * const i2s3_ws_groups[] = { "gpio20"};
static const char * const i2s3_data_groups[] = { "gpio21", "gpio22"};
static const char * const slimbus_data_groups[] = { "gpio20"};
static const char * const ext_mclk1_c_groups[] = { "gpio5" };
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
static const char * const ext_mclk1_a_groups[] = { "gpio13" };
static const char * const ext_mclk1_d_groups[] = { "gpio14" };
static const char * const ext_mclk1_e_groups[] = { "gpio22" };
static const struct lpi_pingroup sm8450_groups[] = {
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, qua_mi2s_data, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _),
LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s4_clk, _, _),
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s4_ws, ext_mclk1_a, _),
LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _),
LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _),
LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _),
LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s4_data, _, _),
LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s4_data, _, _),
LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, _, _),
LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, _, _),
LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, _, _, _),
LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, ext_mclk1_e, _, _),
};
static const struct lpi_function sm8450_functions[] = {
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(dmic4_clk),
LPI_FUNCTION(dmic4_data),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(i2s3_clk),
LPI_FUNCTION(i2s3_data),
LPI_FUNCTION(i2s3_ws),
LPI_FUNCTION(i2s4_clk),
LPI_FUNCTION(i2s4_data),
LPI_FUNCTION(i2s4_ws),
LPI_FUNCTION(qua_mi2s_data),
LPI_FUNCTION(qua_mi2s_sclk),
LPI_FUNCTION(qua_mi2s_ws),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(slimbus_clk),
LPI_FUNCTION(slimbus_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
LPI_FUNCTION(wsa2_swr_clk),
LPI_FUNCTION(wsa2_swr_data),
LPI_FUNCTION(ext_mclk1_a),
LPI_FUNCTION(ext_mclk1_b),
LPI_FUNCTION(ext_mclk1_c),
LPI_FUNCTION(ext_mclk1_d),
LPI_FUNCTION(ext_mclk1_e),
};
static const struct lpi_pinctrl_variant_data sm8450_lpi_data = {
.pins = sm8450_lpi_pins,
.npins = ARRAY_SIZE(sm8450_lpi_pins),
.groups = sm8450_groups,
.ngroups = ARRAY_SIZE(sm8450_groups),
.functions = sm8450_functions,
.nfunctions = ARRAY_SIZE(sm8450_functions),
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,sm8450-lpass-lpi-pinctrl",
.data = &sm8450_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-sm8450-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI SM8450 LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

75
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/gpio/driver.h>
@ -36,6 +37,8 @@
#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12
#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13
#define PMIC_MPP_REG_RT_STS 0x10
#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
@ -98,6 +101,9 @@
#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
#define PMIC_GPIO_OUT_STRENGTH_LOW 1
#define PMIC_GPIO_OUT_STRENGTH_HIGH 3
/* PMIC_GPIO_REG_EN_CTL */
#define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
@ -171,7 +177,6 @@ struct pmic_gpio_state {
struct regmap *map;
struct pinctrl_dev *ctrl;
struct gpio_chip chip;
struct irq_chip irq;
u8 usid;
u8 pid_base;
};
@ -437,8 +442,18 @@ static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
arg = pad->pullup;
break;
case PMIC_GPIO_CONF_STRENGTH:
switch (pad->strength) {
case PMIC_GPIO_OUT_STRENGTH_HIGH:
arg = PMIC_GPIO_STRENGTH_HIGH;
break;
case PMIC_GPIO_OUT_STRENGTH_LOW:
arg = PMIC_GPIO_STRENGTH_LOW;
break;
default:
arg = pad->strength;
break;
}
break;
case PMIC_GPIO_CONF_ATEST:
arg = pad->atest;
break;
@ -524,8 +539,18 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
case PMIC_GPIO_CONF_STRENGTH:
if (arg > PMIC_GPIO_STRENGTH_LOW)
return -EINVAL;
switch (arg) {
case PMIC_GPIO_STRENGTH_HIGH:
pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH;
break;
case PMIC_GPIO_STRENGTH_LOW:
pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW;
break;
default:
pad->strength = arg;
break;
}
break;
case PMIC_GPIO_CONF_ATEST:
if (!pad->lv_mv_type || arg > 4)
return -EINVAL;
@ -823,6 +848,16 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
pad->have_buffer = true;
pad->lv_mv_type = true;
break;
case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2:
pad->num_sources = 2;
pad->have_buffer = true;
pad->lv_mv_type = true;
break;
case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3:
pad->num_sources = 3;
pad->have_buffer = true;
pad->lv_mv_type = true;
break;
default:
dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
return -ENODEV;
@ -985,6 +1020,33 @@ static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
return 0;
}
static void pmic_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
irq_chip_mask_parent(data);
gpiochip_disable_irq(gc, data->hwirq);
}
static void pmic_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
gpiochip_enable_irq(gc, data->hwirq);
irq_chip_unmask_parent(data);
}
static const struct irq_chip spmi_gpio_irq_chip = {
.name = "spmi-gpio",
.irq_ack = irq_chip_ack_parent,
.irq_mask = pmic_gpio_irq_mask,
.irq_unmask = pmic_gpio_irq_unmask,
.irq_set_type = irq_chip_set_type_parent,
.irq_set_wake = irq_chip_set_wake_parent,
.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int pmic_gpio_probe(struct platform_device *pdev)
{
struct irq_domain *parent_domain;
@ -1078,16 +1140,8 @@ static int pmic_gpio_probe(struct platform_device *pdev)
if (!parent_domain)
return -ENXIO;
state->irq.name = "spmi-gpio",
state->irq.irq_ack = irq_chip_ack_parent,
state->irq.irq_mask = irq_chip_mask_parent,
state->irq.irq_unmask = irq_chip_unmask_parent,
state->irq.irq_set_type = irq_chip_set_type_parent,
state->irq.irq_set_wake = irq_chip_set_wake_parent,
state->irq.flags = IRQCHIP_MASK_ON_SUSPEND,
girq = &state->chip.irq;
girq->chip = &state->irq;
gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip);
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
girq->fwnode = of_node_to_fwnode(state->dev->of_node);
@ -1147,6 +1201,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
{ .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },

8
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -1166,15 +1166,15 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
if (ret)
goto err_put_banks;
ret = samsung_gpiolib_register(pdev, drvdata);
if (ret)
goto err_unregister;
if (ctrl->eint_gpio_init)
ctrl->eint_gpio_init(drvdata);
if (ctrl->eint_wkup_init)
ctrl->eint_wkup_init(drvdata);
ret = samsung_gpiolib_register(pdev, drvdata);
if (ret)
goto err_unregister;
platform_set_drvdata(pdev, drvdata);
return 0;

18
drivers/pinctrl/starfive/Kconfig Normal file
View File

@ -0,0 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only
config PINCTRL_STARFIVE_JH7100
tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
depends on SOC_STARFIVE || COMPILE_TEST
depends on OF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
select OF_GPIO
default SOC_STARFIVE
help
Say yes here to support pin control on the StarFive JH7100 SoC.
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.

3
drivers/pinctrl/starfive/Makefile Normal file
View File

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o

10
drivers/pinctrl/pinctrl-starfive.c → drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
View File

@ -20,12 +20,12 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
#include "core.h"
#include "pinctrl-utils.h"
#include "pinmux.h"
#include "pinconf.h"
#include "../core.h"
#include "../pinctrl-utils.h"
#include "../pinmux.h"
#include "../pinconf.h"
#define DRIVER_NAME "pinctrl-starfive"

5
drivers/pinctrl/stm32/pinctrl-stm32.c
View File

@ -1603,10 +1603,9 @@ int stm32_pctl_probe(struct platform_device *pdev)
bank->clk = of_clk_get_by_name(np, NULL);
if (IS_ERR(bank->clk)) {
if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
fwnode_handle_put(child);
return PTR_ERR(bank->clk);
return dev_err_probe(dev, PTR_ERR(bank->clk),
"failed to get clk\n");
}
i++;
}

9
drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
View File

@ -551,12 +551,9 @@ static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
int ret;
ret = platform_irq_count(pdev);
if (ret < 0) {
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev, "Couldn't determine irq count: %pe\n",
ERR_PTR(ret));
return ret;
}
if (ret < 0)
return dev_err_probe(&pdev->dev, ret,
"Couldn't determine irq count\n");
switch (ret) {
case 2:

1280
include/dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h Normal file
View File

File diff suppressed because it is too large Load Diff

6
include/dt-bindings/pinctrl/pinctrl-starfive.h → include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
View File

@ -3,8 +3,8 @@
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_H__
#define __DT_BINDINGS_PINCTRL_STARFIVE_H__
#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
#define PAD_GPIO_OFFSET 0
#define PAD_FUNC_SHARE_OFFSET 64
@ -272,4 +272,4 @@
#define GPI_NONE 0xff
#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_H__ */
#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ */

7
include/dt-bindings/pinctrl/samsung.h
View File

@ -10,6 +10,13 @@
#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
/*
* These bindings are deprecated, because they do not match the actual
* concept of bindings but rather contain pure register values.
* Instead include the header in the DTS source directory.
*/
#warning "These bindings are deprecated. Instead use the header in the DTS source directory."
#define EXYNOS_PIN_PULL_NONE 0
#define EXYNOS_PIN_PULL_DOWN 1
#define EXYNOS_PIN_PULL_UP 3

16
include/soc/at91/pm.h
View File

@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atmel Power Management
*
* Copyright (C) 2020 Atmel
*
* Author: Lee Jones <lee.jones@linaro.org>
*/
#ifndef __SOC_ATMEL_PM_H
#define __SOC_ATMEL_PM_H
void at91_pinctrl_gpio_suspend(void);
void at91_pinctrl_gpio_resume(void);
#endif /* __SOC_ATMEL_PM_H */