OMAP4: hwmod data: Add GPIO
Add GPIO hwmod data for OMAP4 Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Charulatha V <charu@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Benoit Cousson
Tony Lindgren
parent
70034d38fb
commit
9780a9cfa7
@ -22,6 +22,7 @@
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#include <plat/omap_hwmod.h>
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#include <plat/cpu.h>
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#include <plat/gpio.h>
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#include "omap_hwmod_common_data.h"
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@ -1043,6 +1044,338 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/*
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* 'gpio' class
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* general purpose io module
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0114,
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.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
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.name = "gpio",
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.sysc = &omap44xx_gpio_sysc,
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.rev = 2,
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};
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/* gpio dev_attr */
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static struct omap_gpio_dev_attr gpio_dev_attr = {
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.bank_width = 32,
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.dbck_flag = true,
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};
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/* gpio1 */
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static struct omap_hwmod omap44xx_gpio1_hwmod;
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static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
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{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
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{
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.pa_start = 0x4a310000,
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.pa_end = 0x4a3101ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_wkup -> gpio1 */
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static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
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.master = &omap44xx_l4_wkup_hwmod,
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.slave = &omap44xx_gpio1_hwmod,
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.addr = omap44xx_gpio1_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* gpio1 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
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&omap44xx_l4_wkup__gpio1,
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};
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static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
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{ .role = "dbclk", .clk = "sys_32k_ck" },
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};
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static struct omap_hwmod omap44xx_gpio1_hwmod = {
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.name = "gpio1",
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.class = &omap44xx_gpio_hwmod_class,
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.mpu_irqs = omap44xx_gpio1_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
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.main_clk = "gpio1_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
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},
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},
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.opt_clks = gpio1_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
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.dev_attr = &gpio_dev_attr,
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.slaves = omap44xx_gpio1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* gpio2 */
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static struct omap_hwmod omap44xx_gpio2_hwmod;
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static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
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{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
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{
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.pa_start = 0x48055000,
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.pa_end = 0x480551ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> gpio2 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio2_hwmod,
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.addr = omap44xx_gpio2_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* gpio2 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
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&omap44xx_l4_per__gpio2,
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};
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static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
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{ .role = "dbclk", .clk = "sys_32k_ck" },
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};
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static struct omap_hwmod omap44xx_gpio2_hwmod = {
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.name = "gpio2",
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.class = &omap44xx_gpio_hwmod_class,
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.mpu_irqs = omap44xx_gpio2_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
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.main_clk = "gpio2_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
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},
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},
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.opt_clks = gpio2_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
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.dev_attr = &gpio_dev_attr,
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.slaves = omap44xx_gpio2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* gpio3 */
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static struct omap_hwmod omap44xx_gpio3_hwmod;
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static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
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{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
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{
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.pa_start = 0x48057000,
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.pa_end = 0x480571ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> gpio3 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio3_hwmod,
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.addr = omap44xx_gpio3_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* gpio3 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
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&omap44xx_l4_per__gpio3,
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};
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static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
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{ .role = "dbclk", .clk = "sys_32k_ck" },
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};
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static struct omap_hwmod omap44xx_gpio3_hwmod = {
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.name = "gpio3",
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.class = &omap44xx_gpio_hwmod_class,
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.mpu_irqs = omap44xx_gpio3_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
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.main_clk = "gpio3_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
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},
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},
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.opt_clks = gpio3_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
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.dev_attr = &gpio_dev_attr,
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.slaves = omap44xx_gpio3_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* gpio4 */
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static struct omap_hwmod omap44xx_gpio4_hwmod;
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static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
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{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
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{
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.pa_start = 0x48059000,
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.pa_end = 0x480591ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> gpio4 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio4_hwmod,
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.addr = omap44xx_gpio4_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* gpio4 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
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&omap44xx_l4_per__gpio4,
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};
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static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
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{ .role = "dbclk", .clk = "sys_32k_ck" },
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};
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static struct omap_hwmod omap44xx_gpio4_hwmod = {
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.name = "gpio4",
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.class = &omap44xx_gpio_hwmod_class,
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.mpu_irqs = omap44xx_gpio4_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
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.main_clk = "gpio4_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
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},
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},
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.opt_clks = gpio4_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
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.dev_attr = &gpio_dev_attr,
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.slaves = omap44xx_gpio4_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* gpio5 */
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static struct omap_hwmod omap44xx_gpio5_hwmod;
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static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
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{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
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{
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.pa_start = 0x4805b000,
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.pa_end = 0x4805b1ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> gpio5 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio5_hwmod,
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.addr = omap44xx_gpio5_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* gpio5 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
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&omap44xx_l4_per__gpio5,
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};
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static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
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{ .role = "dbclk", .clk = "sys_32k_ck" },
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};
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static struct omap_hwmod omap44xx_gpio5_hwmod = {
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.name = "gpio5",
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.class = &omap44xx_gpio_hwmod_class,
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.mpu_irqs = omap44xx_gpio5_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
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.main_clk = "gpio5_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
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},
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},
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.opt_clks = gpio5_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
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.dev_attr = &gpio_dev_attr,
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.slaves = omap44xx_gpio5_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* gpio6 */
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static struct omap_hwmod omap44xx_gpio6_hwmod;
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static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
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{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
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{
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.pa_start = 0x4805d000,
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.pa_end = 0x4805d1ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> gpio6 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio6_hwmod,
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.addr = omap44xx_gpio6_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* gpio6 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
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&omap44xx_l4_per__gpio6,
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};
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static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
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{ .role = "dbclk", .clk = "sys_32k_ck" },
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};
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static struct omap_hwmod omap44xx_gpio6_hwmod = {
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.name = "gpio6",
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.class = &omap44xx_gpio_hwmod_class,
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.mpu_irqs = omap44xx_gpio6_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
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.main_clk = "gpio6_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
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},
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},
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.opt_clks = gpio6_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
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.dev_attr = &gpio_dev_attr,
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.slaves = omap44xx_gpio6_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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/* dmm class */
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&omap44xx_dmm_hwmod,
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@ -1066,6 +1399,14 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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/* mpu_bus class */
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&omap44xx_mpu_private_hwmod,
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/* gpio class */
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&omap44xx_gpio1_hwmod,
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&omap44xx_gpio2_hwmod,
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&omap44xx_gpio3_hwmod,
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&omap44xx_gpio4_hwmod,
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&omap44xx_gpio5_hwmod,
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&omap44xx_gpio6_hwmod,
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/* mpu class */
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&omap44xx_mpu_hwmod,
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/* wd_timer class */
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