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drm/amd/display: Add dppclk to dcn_bw_clocks

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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2017-11-14 11:52:11 -05:00
committed by Alex Deucher
parent bce14857bd
commit 96d9238879
3 changed files with 3 additions and 2 deletions
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3
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
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@@ -582,7 +582,8 @@ struct dce_hwseq_registers {
type DOMAIN7_PGFSM_PWR_STATUS; \ type DOMAIN7_PGFSM_PWR_STATUS; \
type DCFCLK_GATE_DIS; \ type DCFCLK_GATE_DIS; \
type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
type DENTIST_DPPCLK_WDIVIDER; type DENTIST_DPPCLK_WDIVIDER; \
type DENTIST_DISPCLK_WDIVIDER;
struct dce_hwseq_shift { struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t) HWSEQ_REG_FIELD_LIST(uint8_t)

1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
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@@ -1335,7 +1335,6 @@ static void dcn10_enable_plane(
/* make sure OPP_PIPE_CLOCK_EN = 1 */ /* make sure OPP_PIPE_CLOCK_EN = 1 */
REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst], REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
OPP_PIPE_CLOCK_EN, 1); OPP_PIPE_CLOCK_EN, 1);
/*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
/* TODO: enable/disable in dm as per update type. /* TODO: enable/disable in dm as per update type.
if (plane_state) { if (plane_state) {

1
drivers/gpu/drm/amd/display/dc/inc/core_types.h
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@@ -241,6 +241,7 @@ struct dce_bw_output {
struct dcn_bw_clocks { struct dcn_bw_clocks {
int dispclk_khz; int dispclk_khz;
int dppclk_khz;
bool dppclk_div; bool dppclk_div;
int dcfclk_khz; int dcfclk_khz;
int dcfclk_deep_sleep_khz; int dcfclk_deep_sleep_khz;