forked from Minki/linux
ALSA: x86: intel_hdmi: add definitions and logic for DP audio
Imported from legacy patches Note: the new code doesn't assume a modified ELD but an explicit notification that DP is present. It appears that the i915 code does change the ELD so we could use the ELD-based tests to check for DP audio Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Pierre-Louis Bossart
Takashi Iwai
parent
f95e29b921
commit
964ca8083c
@ -396,6 +396,7 @@ static int snd_intelhad_prog_audio_ctrl_v2(struct snd_pcm_substream *substream,
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else
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cfg_val.cfg_regx_v2.layout = LAYOUT1;
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cfg_val.cfg_regx_v2.val_bit = 1;
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had_write_register(AUD_CONFIG, cfg_val.cfg_regval);
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return 0;
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}
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@ -447,6 +448,7 @@ static int snd_intelhad_prog_audio_ctrl_v1(struct snd_pcm_substream *substream,
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}
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cfg_val.cfg_regx.val_bit = 1;
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had_write_register(AUD_CONFIG, cfg_val.cfg_regval);
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return 0;
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}
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@ -548,6 +550,7 @@ void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
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}
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had_get_caps(HAD_GET_ELD, &intelhaddata->eeld);
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had_get_caps(HAD_GET_DP_OUTPUT, &intelhaddata->dp_output);
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pr_debug("eeld.speaker_allocation_block = %x\n",
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intelhaddata->eeld.speaker_allocation_block);
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@ -685,7 +688,7 @@ static void snd_intelhad_prog_dip_v1(struct snd_pcm_substream *substream,
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/*Calculte the byte wide checksum for all valid DIP words*/
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (INFO_FRAME_WORD1 >> i*BITS_PER_BYTE) & MASK_BYTE0;
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checksum += (HDMI_INFO_FRAME_WORD1 >> i*BITS_PER_BYTE) & MASK_BYTE0;
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (frame2.fr2_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
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for (i = 0; i < BYTES_PER_WORD; i++)
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@ -693,7 +696,7 @@ static void snd_intelhad_prog_dip_v1(struct snd_pcm_substream *substream,
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frame2.fr2_regx.chksum = -(checksum);
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had_write_register(AUD_HDMIW_INFOFR, INFO_FRAME_WORD1);
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had_write_register(AUD_HDMIW_INFOFR, HDMI_INFO_FRAME_WORD1);
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had_write_register(AUD_HDMIW_INFOFR, frame2.fr2_val);
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had_write_register(AUD_HDMIW_INFOFR, frame3.fr3_val);
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@ -722,12 +725,18 @@ static void snd_intelhad_prog_dip_v2(struct snd_pcm_substream *substream,
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union aud_info_frame2 frame2 = {.fr2_val = 0};
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union aud_info_frame3 frame3 = {.fr3_val = 0};
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u8 checksum = 0;
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u32 info_frame;
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int channels;
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channels = substream->runtime->channels;
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had_write_register(AUD_CNTL_ST, ctrl_state.ctrl_val);
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if (intelhaddata->dp_output) {
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info_frame = DP_INFO_FRAME_WORD1;
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frame2.fr2_val = 1;
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} else {
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info_frame = HDMI_INFO_FRAME_WORD1;
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frame2.fr2_regx.chnl_cnt = substream->runtime->channels - 1;
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frame3.fr3_regx.chnl_alloc = snd_intelhad_channel_allocation(
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@ -735,15 +744,16 @@ static void snd_intelhad_prog_dip_v2(struct snd_pcm_substream *substream,
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/*Calculte the byte wide checksum for all valid DIP words*/
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (INFO_FRAME_WORD1 >> i*BITS_PER_BYTE) & MASK_BYTE0;
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checksum += (info_frame >> i*BITS_PER_BYTE) & MASK_BYTE0;
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (frame2.fr2_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (frame3.fr3_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
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frame2.fr2_regx.chksum = -(checksum);
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}
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had_write_register(AUD_HDMIW_INFOFR_v2, INFO_FRAME_WORD1);
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had_write_register(AUD_HDMIW_INFOFR_v2, info_frame);
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had_write_register(AUD_HDMIW_INFOFR_v2, frame2.fr2_val);
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had_write_register(AUD_HDMIW_INFOFR_v2, frame3.fr3_val);
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@ -839,6 +849,85 @@ int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
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return retval;
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}
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static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
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{
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u32 maud_val;
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/* Select maud according to DP 1.2 spec*/
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if (link_rate == DP_2_7_GHZ) {
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switch (aud_samp_freq) {
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case AUD_SAMPLE_RATE_32:
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maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_44_1:
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maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_48:
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maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_88_2:
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maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_96:
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maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_176_4:
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maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
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break;
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case HAD_MAX_RATE:
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maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
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break;
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default:
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maud_val = -EINVAL;
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break;
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}
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} else if (link_rate == DP_1_62_GHZ) {
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switch (aud_samp_freq) {
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case AUD_SAMPLE_RATE_32:
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maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_44_1:
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maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_48:
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maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_88_2:
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maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_96:
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maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
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break;
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case AUD_SAMPLE_RATE_176_4:
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maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
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break;
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case HAD_MAX_RATE:
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maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
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break;
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default:
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maud_val = -EINVAL;
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break;
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}
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} else
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maud_val = -EINVAL;
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return maud_val;
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}
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/**
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* snd_intelhad_prog_cts_v1 - Program HDMI audio CTS value
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*
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@ -849,7 +938,8 @@ int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
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*
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* Program CTS register based on the audio and display sampling frequency
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*/
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static void snd_intelhad_prog_cts_v1(u32 aud_samp_freq, u32 tmds, u32 n_param,
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static void snd_intelhad_prog_cts_v1(u32 aud_samp_freq, u32 tmds,
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u32 link_rate, u32 n_param,
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struct snd_intelhad *intelhaddata)
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{
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u32 cts_val;
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@ -874,16 +964,22 @@ static void snd_intelhad_prog_cts_v1(u32 aud_samp_freq, u32 tmds, u32 n_param,
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*
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* Program CTS register based on the audio and display sampling frequency
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*/
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static void snd_intelhad_prog_cts_v2(u32 aud_samp_freq, u32 tmds, u32 n_param,
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static void snd_intelhad_prog_cts_v2(u32 aud_samp_freq, u32 tmds,
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u32 link_rate, u32 n_param,
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struct snd_intelhad *intelhaddata)
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{
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u32 cts_val;
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u64 dividend, divisor;
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if (intelhaddata->dp_output) {
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/* Substitute cts_val with Maud according to DP 1.2 spec*/
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cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
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} else {
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/* Calculate CTS according to HDMI 1.3a spec*/
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dividend = (u64)tmds * n_param*1000;
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divisor = 128 * aud_samp_freq;
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cts_val = div64_u64(dividend, divisor);
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}
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pr_debug("TMDS value=%d, N value=%d, CTS Value=%d\n",
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tmds, n_param, cts_val);
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had_write_register(AUD_HDMI_CTS, (BIT(24) | cts_val));
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@ -970,6 +1066,17 @@ static int snd_intelhad_prog_n_v2(u32 aud_samp_freq, u32 *n_param,
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{
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s32 n_val;
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if (intelhaddata->dp_output) {
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/*
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* According to DP specs, Maud and Naud values hold
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* a relationship, which is stated as:
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* Maud/Naud = 512 * fs / f_LS_Clk
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* where, fs is the sampling frequency of the audio stream
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* and Naud is 32768 for Async clock.
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*/
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n_val = DP_NAUD_VAL;
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} else
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n_val = had_calculate_n_value(aud_samp_freq);
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if (n_val < 0)
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@ -1343,6 +1450,7 @@ static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
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{
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int retval;
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u32 disp_samp_freq, n_param;
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u32 link_rate = 0;
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struct snd_intelhad *intelhaddata;
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struct snd_pcm_runtime *runtime;
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struct had_pvt_data *had_stream;
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@ -1387,6 +1495,7 @@ static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
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}
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had_get_caps(HAD_GET_ELD, &intelhaddata->eeld);
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had_get_caps(HAD_GET_DP_OUTPUT, &intelhaddata->dp_output);
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retval = intelhaddata->ops->prog_n(substream->runtime->rate, &n_param,
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intelhaddata);
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@ -1394,8 +1503,14 @@ static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
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pr_err("programming N value failed %#x\n", retval);
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goto prep_end;
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}
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if (intelhaddata->dp_output)
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had_get_caps(HAD_GET_LINK_RATE, &link_rate);
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intelhaddata->ops->prog_cts(substream->runtime->rate,
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disp_samp_freq, n_param, intelhaddata);
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disp_samp_freq, link_rate,
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n_param, intelhaddata);
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intelhaddata->ops->prog_dip(substream, intelhaddata);
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@ -1503,6 +1618,7 @@ int hdmi_audio_mode_change(struct snd_pcm_substream *substream)
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{
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int retval = 0;
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u32 disp_samp_freq, n_param;
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u32 link_rate = 0;
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struct snd_intelhad *intelhaddata;
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intelhaddata = snd_pcm_substream_chip(substream);
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@ -1523,8 +1639,13 @@ int hdmi_audio_mode_change(struct snd_pcm_substream *substream)
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pr_err("programming N value failed %#x\n", retval);
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goto out;
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}
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if (intelhaddata->dp_output)
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had_get_caps(HAD_GET_LINK_RATE, &link_rate);
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intelhaddata->ops->prog_cts(substream->runtime->rate,
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disp_samp_freq, n_param, intelhaddata);
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disp_samp_freq, link_rate,
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n_param, intelhaddata);
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/* Enable Audio */
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intelhaddata->ops->enable_audio(substream, 1);
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@ -44,7 +44,8 @@
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#define MAX_CAP_STREAMS 0
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#define HDMI_AUDIO_DRIVER "hdmi-audio"
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#define INFO_FRAME_WORD1 0x000a0184
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#define HDMI_INFO_FRAME_WORD1 0x000a0184
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#define DP_INFO_FRAME_WORD1 0x00441b84
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#define FIFO_THRESHOLD 0xFE
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#define DMA_FIFO_THRESHOLD 0x7
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#define BYTES_PER_WORD 0x4
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@ -134,6 +135,7 @@ struct snd_intelhad {
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struct ring_buf_info buf_info[HAD_NUM_OF_RING_BUFS];
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struct pcm_stream_info stream_info;
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union otm_hdmi_eld_t eeld;
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bool dp_output;
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enum intel_had_aud_buf_type curr_buf;
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int valid_buf_cnt;
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unsigned int aes_bits;
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@ -156,8 +158,8 @@ struct had_ops {
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void (*reset_audio)(u8 reset);
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int (*prog_n)(u32 aud_samp_freq, u32 *n_param,
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struct snd_intelhad *intelhaddata);
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void (*prog_cts)(u32 aud_samp_freq, u32 tmds, u32 n_param,
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struct snd_intelhad *intelhaddata);
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void (*prog_cts)(u32 aud_samp_freq, u32 tmds, u32 link_rate,
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u32 n_param, struct snd_intelhad *intelhaddata);
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int (*audio_ctrl)(struct snd_pcm_substream *substream,
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struct snd_intelhad *intelhaddata);
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void (*prog_dip)(struct snd_pcm_substream *substream,
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@ -48,6 +48,8 @@ struct hdmi_lpe_audio_ctx {
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struct snd_intel_had_interface *had_interface;
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void *had_pvt_data;
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int tmds_clock_speed;
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bool dp_output;
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int link_rate;
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unsigned int had_config_offset;
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int hdmi_audio_interrupt_mask;
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struct work_struct hdmi_audio_wq;
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@ -187,6 +189,15 @@ static int hdmi_audio_write(u32 reg, u32 val)
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dev_dbg(&hlpe_pdev->dev, "%s: reg[0x%x] = 0x%x\n", __func__, reg, val);
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if (ctx->dp_output) {
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if ((reg == AUDIO_HDMI_CONFIG_A) ||
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(reg == AUDIO_HDMI_CONFIG_B) ||
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(reg == AUDIO_HDMI_CONFIG_C)) {
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if (val & AUD_CONFIG_VALID_BIT)
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val = val | AUD_CONFIG_DP_MODE |
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AUD_CONFIG_BLOCK_BIT;
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}
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}
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iowrite32(val, (ctx->mmio_start+reg));
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return 0;
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@ -220,6 +231,16 @@ static int hdmi_audio_rmw(u32 reg, u32 val, u32 mask)
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val_tmp = (val & mask) |
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((ioread32(ctx->mmio_start + reg)) & ~mask);
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if (ctx->dp_output) {
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if ((reg == AUDIO_HDMI_CONFIG_A) ||
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(reg == AUDIO_HDMI_CONFIG_B) ||
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(reg == AUDIO_HDMI_CONFIG_C)) {
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if (val_tmp & AUD_CONFIG_VALID_BIT)
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val_tmp = val_tmp | AUD_CONFIG_DP_MODE |
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AUD_CONFIG_BLOCK_BIT;
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}
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}
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iowrite32(val_tmp, (ctx->mmio_start+reg));
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dev_dbg(&hlpe_pdev->dev, "%s: reg[0x%x] = 0x%x\n", __func__,
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reg, val_tmp);
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@ -251,6 +272,17 @@ static int hdmi_audio_get_caps(enum had_caps_list get_element,
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dev_dbg(&hlpe_pdev->dev, "%s: tmds_clock_speed = 0x%x\n",
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__func__, ctx->tmds_clock_speed);
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break;
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case HAD_GET_LINK_RATE:
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/* ToDo: Verify if sampling freq logic is correct */
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*(u32 *)capabilities = ctx->link_rate;
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dev_dbg(&hlpe_pdev->dev, "%s: link rate = 0x%x\n",
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__func__, ctx->link_rate);
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break;
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case HAD_GET_DP_OUTPUT:
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*(u32 *)capabilities = ctx->dp_output;
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dev_dbg(&hlpe_pdev->dev, "%s: dp_output = %d\n",
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__func__, ctx->dp_output);
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break;
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default:
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break;
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}
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@ -442,6 +474,8 @@ static void notify_audio_lpe(void *audio_ptr)
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if (pdata->tmds_clock_speed) {
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ctx->tmds_clock_speed = pdata->tmds_clock_speed;
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ctx->dp_output = pdata->dp_output;
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ctx->link_rate = pdata->link_rate;
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mid_hdmi_audio_signal_event(HAD_EVENT_MODE_CHANGING);
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}
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} else
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@ -31,6 +31,10 @@
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#include <sound/control.h>
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#include <sound/pcm.h>
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#define AUD_CONFIG_VALID_BIT (1<<9)
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#define AUD_CONFIG_DP_MODE (1<<15)
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#define AUD_CONFIG_BLOCK_BIT (1<<7)
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#define HMDI_LPE_AUDIO_DRIVER_NAME "intel-hdmi-lpe-audio"
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#define HAD_MAX_DEVICES 1
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#define HAD_MIN_CHANNEL 2
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@ -68,6 +72,29 @@
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#define HAD_MAX_DIP_WORDS 16
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#define INTEL_HAD "IntelHdmiLpeAudio"
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/* DP Link Rates */
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#define DP_2_7_GHZ 270000
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#define DP_1_62_GHZ 162000
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/* Maud Values */
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#define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988
|
||||
#define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740
|
||||
#define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982
|
||||
#define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480
|
||||
#define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965
|
||||
#define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961
|
||||
#define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930
|
||||
#define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314
|
||||
#define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567
|
||||
#define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971
|
||||
#define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134
|
||||
#define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942
|
||||
#define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268
|
||||
#define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884
|
||||
|
||||
/* Naud Value */
|
||||
#define DP_NAUD_VAL 32768
|
||||
|
||||
/* _AUD_CONFIG register MASK */
|
||||
#define AUD_CONFIG_MASK_UNDERRUN 0xC0000000
|
||||
#define AUD_CONFIG_MASK_SRDBG 0x00000002
|
||||
@ -618,6 +645,8 @@ enum hdmi_connector_status {
|
||||
enum had_caps_list {
|
||||
HAD_GET_ELD = 1,
|
||||
HAD_GET_DISPLAY_RATE,
|
||||
HAD_GET_DP_OUTPUT,
|
||||
HAD_GET_LINK_RATE,
|
||||
HAD_SET_ENABLE_AUDIO,
|
||||
HAD_SET_DISABLE_AUDIO,
|
||||
HAD_SET_ENABLE_AUDIO_INT,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user