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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs.  Some for SoC-family code under
  drivers/soc, but also some other driver updates that don't belong
  anywhere else.  We also bring in the drivers/reset code through
  arm-soc.

  Some of the larger updates:

   - Qualcomm support for SMEM, SMSM, SMP2P.  All used to communicate
     with other parts of the chip/board on these platforms, all
     proprietary protocols that don't fit into other subsystems and live
     in drivers/soc for now.

   - System bus driver for UniPhier

   - Driver for the TI Wakeup M3 IPC device

   - Power management for Raspberry PI

  + Again a bunch of other smaller updates and patches"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
  bus: uniphier: allow only built-in driver
  ARM: bcm2835: clarify RASPBERRYPI_FIRMWARE dependency
  MAINTAINERS: Drop Kumar Gala from QCOM
  bus: uniphier-system-bus: add UniPhier System Bus driver
  ARM: bcm2835: add rpi power domain driver
  dt-bindings: add rpi power domain driver bindings
  ARM: bcm2835: Define two new packets from the latest firmware.
  drivers/soc: make mediatek/mtk-scpsys.c explicitly non-modular
  soc: mediatek: SCPSYS: Add regulator support
  MAINTAINERS: Change QCOM entries
  soc: qcom: smd-rpm: Add existing platform support
  memory/tegra: Add number of TLB lines for Tegra124
  reset: hi6220: fix modular build
  soc: qcom: Introduce WCNSS_CTRL SMD client
  ARM: qcom: select ARM_CPU_SUSPEND for power management
  MAINTAINERS: Add rules for Qualcomm dts files
  soc: qcom: enable smsm/smp2p modular build
  serial: msm_serial: Make config tristate
  soc: qcom: smp2p: Qualcomm Shared Memory Point to Point
  soc: qcom: smsm: Add driver for Qualcomm SMSM
  ...
This commit is contained in:
Linus Torvalds
2016-01-20 18:42:30 -08:00
parent 03d7d12415 ce96cb7386
commit 9638685e32
47 changed files with 3439 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
include/dt-bindings/power/raspberrypi-power.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright © 2015 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
/* These power domain indices are the firmware interface's indices
* minus one.
*/
#define RPI_POWER_DOMAIN_I2C0 0
#define RPI_POWER_DOMAIN_I2C1 1
#define RPI_POWER_DOMAIN_I2C2 2
#define RPI_POWER_DOMAIN_VIDEO_SCALER 3
#define RPI_POWER_DOMAIN_VPU1 4
#define RPI_POWER_DOMAIN_HDMI 5
#define RPI_POWER_DOMAIN_USB 6
#define RPI_POWER_DOMAIN_VEC 7
#define RPI_POWER_DOMAIN_JPEG 8
#define RPI_POWER_DOMAIN_H264 9
#define RPI_POWER_DOMAIN_V3D 10
#define RPI_POWER_DOMAIN_ISP 11
#define RPI_POWER_DOMAIN_UNICAM0 12
#define RPI_POWER_DOMAIN_UNICAM1 13
#define RPI_POWER_DOMAIN_CCP2RX 14
#define RPI_POWER_DOMAIN_CSI2 15
#define RPI_POWER_DOMAIN_CPI 16
#define RPI_POWER_DOMAIN_DSI0 17
#define RPI_POWER_DOMAIN_DSI1 18
#define RPI_POWER_DOMAIN_TRANSPOSER 19
#define RPI_POWER_DOMAIN_CCP2TX 20
#define RPI_POWER_DOMAIN_CDP 21
#define RPI_POWER_DOMAIN_ARM 22
#define RPI_POWER_DOMAIN_COUNT 23
#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */

67
include/dt-bindings/reset/hisi,hi6220-resets.h Normal file
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@@ -0,0 +1,67 @@
/**
* This header provides index for the reset controller
* based on hi6220 SoC.
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
#define _DT_BINDINGS_RESET_CONTROLLER_HI6220
#define PERIPH_RSTDIS0_MMC0 0x000
#define PERIPH_RSTDIS0_MMC1 0x001
#define PERIPH_RSTDIS0_MMC2 0x002
#define PERIPH_RSTDIS0_NANDC 0x003
#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
#define PERIPH_RSTDIS0_USBOTG 0x006
#define PERIPH_RSTDIS0_USBOTG_32K 0x007
#define PERIPH_RSTDIS1_HIFI 0x100
#define PERIPH_RSTDIS1_DIGACODEC 0x105
#define PERIPH_RSTEN2_IPF 0x200
#define PERIPH_RSTEN2_SOCP 0x201
#define PERIPH_RSTEN2_DMAC 0x202
#define PERIPH_RSTEN2_SECENG 0x203
#define PERIPH_RSTEN2_ABB 0x204
#define PERIPH_RSTEN2_HPM0 0x205
#define PERIPH_RSTEN2_HPM1 0x206
#define PERIPH_RSTEN2_HPM2 0x207
#define PERIPH_RSTEN2_HPM3 0x208
#define PERIPH_RSTEN3_CSSYS 0x300
#define PERIPH_RSTEN3_I2C0 0x301
#define PERIPH_RSTEN3_I2C1 0x302
#define PERIPH_RSTEN3_I2C2 0x303
#define PERIPH_RSTEN3_I2C3 0x304
#define PERIPH_RSTEN3_UART1 0x305
#define PERIPH_RSTEN3_UART2 0x306
#define PERIPH_RSTEN3_UART3 0x307
#define PERIPH_RSTEN3_UART4 0x308
#define PERIPH_RSTEN3_SSP 0x309
#define PERIPH_RSTEN3_PWM 0x30a
#define PERIPH_RSTEN3_BLPWM 0x30b
#define PERIPH_RSTEN3_TSENSOR 0x30c
#define PERIPH_RSTEN3_DAPB 0x312
#define PERIPH_RSTEN3_HKADC 0x313
#define PERIPH_RSTEN3_CODEC_SSI 0x314
#define PERIPH_RSTEN3_PMUSSI1 0x316
#define PERIPH_RSTEN8_RS0 0x400
#define PERIPH_RSTEN8_RS2 0x401
#define PERIPH_RSTEN8_RS3 0x402
#define PERIPH_RSTEN8_MS0 0x403
#define PERIPH_RSTEN8_MS2 0x405
#define PERIPH_RSTEN8_XG2RAM0 0x406
#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407
#define PERIPH_RSTEN8_SRAM 0x408
#define PERIPH_RSTEN8_HARQ 0x40a
#define PERIPH_RSTEN8_DDRC 0x40c
#define PERIPH_RSTEN8_DDRC_APB 0x40d
#define PERIPH_RSTEN8_DDRPACK_APB 0x40e
#define PERIPH_RSTEN8_DDRT 0x411
#define PERIPH_RSDIST9_CARM_DAP 0x500
#define PERIPH_RSDIST9_CARM_ATB 0x501
#define PERIPH_RSDIST9_CARM_LBUS 0x502
#define PERIPH_RSDIST9_CARM_POR 0x503
#define PERIPH_RSDIST9_CARM_CORE 0x504
#define PERIPH_RSDIST9_CARM_DBG 0x505
#define PERIPH_RSDIST9_CARM_L2 0x506
#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
#define PERIPH_RSDIST9_CARM_ETM 0x508
#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/

4
include/dt-bindings/reset/stih407-resets.h
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@@ -52,6 +52,10 @@
#define STIH407_KEYSCAN_SOFTRESET 26
#define STIH407_USB2_PORT0_SOFTRESET 27
#define STIH407_USB2_PORT1_SOFTRESET 28
#define STIH407_ST231_AUD_SOFTRESET 29
#define STIH407_ST231_DMU_SOFTRESET 30
#define STIH407_ST231_GP0_SOFTRESET 31
#define STIH407_ST231_GP1_SOFTRESET 32
/* Picophy reset defines */
#define STIH407_PICOPHY0_RESET 0

17
include/linux/reset.h
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@@ -38,6 +38,9 @@ static inline struct reset_control *devm_reset_control_get_optional(
struct reset_control *of_reset_control_get(struct device_node *node,
const char *id);
struct reset_control *of_reset_control_get_by_index(
struct device_node *node, int index);
#else
static inline int reset_control_reset(struct reset_control *rstc)
@@ -71,7 +74,7 @@ static inline void reset_control_put(struct reset_control *rstc)
static inline int device_reset_optional(struct device *dev)
{
return -ENOSYS;
return -ENOTSUPP;
}
static inline struct reset_control *__must_check reset_control_get(
@@ -91,19 +94,25 @@ static inline struct reset_control *__must_check devm_reset_control_get(
static inline struct reset_control *reset_control_get_optional(
struct device *dev, const char *id)
{
return ERR_PTR(-ENOSYS);
return ERR_PTR(-ENOTSUPP);
}
static inline struct reset_control *devm_reset_control_get_optional(
struct device *dev, const char *id)
{
return ERR_PTR(-ENOSYS);
return ERR_PTR(-ENOTSUPP);
}
static inline struct reset_control *of_reset_control_get(
struct device_node *node, const char *id)
{
return ERR_PTR(-ENOSYS);
return ERR_PTR(-ENOTSUPP);
}
static inline struct reset_control *of_reset_control_get_by_index(
struct device_node *node, int index)
{
return ERR_PTR(-ENOTSUPP);
}
#endif /* CONFIG_RESET_CONTROLLER */

18
include/linux/soc/qcom/smem_state.h Normal file
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@@ -0,0 +1,18 @@
#ifndef __QCOM_SMEM_STATE__
#define __QCOM_SMEM_STATE__
struct qcom_smem_state;
struct qcom_smem_state_ops {
int (*update_bits)(void *, u32, u32);
};
struct qcom_smem_state *qcom_smem_state_get(struct device *dev, const char *con_id, unsigned *bit);
void qcom_smem_state_put(struct qcom_smem_state *);
int qcom_smem_state_update_bits(struct qcom_smem_state *state, u32 mask, u32 value);
struct qcom_smem_state *qcom_smem_state_register(struct device_node *of_node, const struct qcom_smem_state_ops *ops, void *data);
void qcom_smem_state_unregister(struct qcom_smem_state *state);
#endif

55
include/linux/wkup_m3_ipc.h Normal file
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@@ -0,0 +1,55 @@
/*
* TI Wakeup M3 for AMx3 SoCs Power Management Routines
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _LINUX_WKUP_M3_IPC_H
#define _LINUX_WKUP_M3_IPC_H
#define WKUP_M3_DEEPSLEEP 1
#define WKUP_M3_STANDBY 2
#define WKUP_M3_IDLE 3
#include <linux/mailbox_client.h>
struct wkup_m3_ipc_ops;
struct wkup_m3_ipc {
struct rproc *rproc;
void __iomem *ipc_mem_base;
struct device *dev;
int mem_type;
unsigned long resume_addr;
int state;
struct completion sync_complete;
struct mbox_client mbox_client;
struct mbox_chan *mbox;
struct wkup_m3_ipc_ops *ops;
};
struct wkup_m3_ipc_ops {
void (*set_mem_type)(struct wkup_m3_ipc *m3_ipc, int mem_type);
void (*set_resume_address)(struct wkup_m3_ipc *m3_ipc, void *addr);
int (*prepare_low_power)(struct wkup_m3_ipc *m3_ipc, int state);
int (*finish_low_power)(struct wkup_m3_ipc *m3_ipc);
int (*request_pm_status)(struct wkup_m3_ipc *m3_ipc);
};
struct wkup_m3_ipc *wkup_m3_ipc_get(void);
void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc);
#endif /* _LINUX_WKUP_M3_IPC_H */

2
include/soc/bcm2835/raspberrypi-firmware.h
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@@ -72,10 +72,12 @@ enum rpi_firmware_property_tag {
RPI_FIRMWARE_SET_ENABLE_QPU = 0x00030012,
RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014,
RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020,
RPI_FIRMWARE_GET_DOMAIN_STATE = 0x00030030,
RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001,
RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002,
RPI_FIRMWARE_SET_VOLTAGE = 0x00038003,
RPI_FIRMWARE_SET_TURBO = 0x00038009,
RPI_FIRMWARE_SET_DOMAIN_STATE = 0x00038030,
/* Dispmanx TAGS */
RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001,