First round of amlogic clock headers update for v4.13
Only gx related update in this round. Expose i2s out, spdif out, EE uart gates and SPICC gate. Un-expose CPU clk which was wrongly copy/pasted from meson8b -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJZL+QSAAoJEAFRo5MEFpTR1m8P/06r+kYGLRpJscTEjcM4JaBG xOgpEsjPYV7pLzG7FuiDP2mh0CUXs8IboypFQRz1fQpVLLi6ACO70SuR0Ov3rIKw AzfGsb0gCqvA/HMrAbJNPptynFKjfST3kYouom9A5BbDS4dj9XzoEGjToB7aMgzR K1q1yEsO+o+xMcLE9SSd1Z+B+C38kpPNZ7mbWgaEPsA0P24ymfl5jCqOHppCPsMs AJbuSbXqFMp630+OWn+Igwn7ZjZlS0S2dIdiEXG3U8D2Pk+aO0++s81pL6HUNq4o 4EtVHVxAqYDPxBksBp1shWFzdONW0kDjvn7rRr4+vqcIdih4mZVGQmOikX+uLShD bQfPBQYiVoyABXbOX1HZJcVMtQGmFs8KtMQ6ZNFZDTCY2FQfzjKnktxY5CFWtsxH ePIwD9RGdKQ+NqF2PAjUyqiHtd4eeCo88tThrdJpZndypP391RZ+XtBel8rRH9JX bJ5nBoJ4nbMf3T3FzxVgHE7RphAnZPgOcdRyJXoFkq+sNNnzq3a3+yHcGEv31X2I moTUL636DO4809UcUybfRKgm/VQZMS2MfDn9jPAeFHga1deVoZKtMqpEPS18qAFV J5B/+hbPkYhpxcsBDh4/dcgI14P3k0TKSQ3puBytzoiwmL+mJ3/NvLyaqDJVwGlX pojYfBcipL4CPqaHPL3o =I7Rf -----END PGP SIGNATURE----- Merge tag 'meson-clk-headers-for-4.13' of git://github.com/BayLibre/clk-meson into v4.13/dt64 First round of amlogic clock headers update for v4.13 Only gx related update in this round. Expose i2s out, spdif out, EE uart gates and SPICC gate. Un-expose CPU clk which was wrongly copy/pasted from meson8b * tag 'meson-clk-headers-for-4.13' of git://github.com/BayLibre/clk-meson: clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
This commit is contained in:
Kevin Hilman
commit
9624dda9f4
@ -171,7 +171,7 @@
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* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
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*/
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#define CLKID_SYS_PLL 0
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/* CLKID_CPUCLK */
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#define CLKID_CPUCLK 1
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/* CLKID_HDMI_PLL */
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#define CLKID_FIXED_PLL 3
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/* CLKID_FCLK_DIV2 */
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@ -191,12 +191,12 @@
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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/* CLKID_SPICC */
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/* CLKID_I2C */
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/* #define CLKID_SAR_ADC */
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#define CLKID_SMART_CARD 24
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/* CLKID_RNG0 */
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#define CLKID_UART0 26
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/* CLKID_UART0 */
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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@ -209,7 +209,7 @@
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/* CLKID_ETH */
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#define CLKID_DEMUX 37
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/* CLKID_AIU_GLUE */
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#define CLKID_IEC958 39
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/* CLKID_IEC958 */
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/* CLKID_I2S_OUT */
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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@ -218,7 +218,7 @@
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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/* CLKID_AIU */
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#define CLKID_UART1 48
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/* CLKID_UART1 */
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#define CLKID_G2D 49
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/* CLKID_USB0 */
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/* CLKID_USB1 */
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@ -238,7 +238,7 @@
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/* CLKID_USB0_DDR_BRIDGE */
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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/* CLKID_UART2 */
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/* #define CLKID_SANA */
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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@ -251,7 +251,7 @@
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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/* CLKID_AOCLK_GATE */
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#define CLKID_IEC958_GATE 81
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/* CLKID_IEC958_GATE */
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCI_INT1 84
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@ -277,13 +277,13 @@
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#define CLKID_MALI_1_DIV 104
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/* CLKID_MALI_1 */
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/* CLKID_MALI */
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#define CLKID_CTS_AMCLK 107
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/* CLKID_CTS_AMCLK */
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#define CLKID_CTS_AMCLK_SEL 108
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#define CLKID_CTS_AMCLK_DIV 109
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#define CLKID_CTS_MCLK_I958 110
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/* CLKID_CTS_MCLK_I958 */
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#define CLKID_CTS_MCLK_I958_SEL 111
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#define CLKID_CTS_MCLK_I958_DIV 112
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#define CLKID_CTS_I958 113
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/* CLKID_CTS_I958 */
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#define NR_CLKS 114
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@ -5,7 +5,6 @@
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#ifndef __GXBB_CLKC_H
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#define __GXBB_CLKC_H
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#define CLKID_CPUCLK 1
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#define CLKID_HDMI_PLL 2
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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@ -13,24 +12,30 @@
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL2 15
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_UART0 26
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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#define CLKID_MIXER_IFACE 44
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_AO_I2C 93
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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@ -42,5 +47,8 @@
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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#define CLKID_CTS_AMCLK 107
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#define CLKID_CTS_MCLK_I958 110
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#define CLKID_CTS_I958 113
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#endif /* __GXBB_CLKC_H */
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