forked from Minki/linux
KVM: arm64: Add feature register flag definitions
Add feature register flag definitions to clarify which features might be supported. Consolidate the various ID_AA64PFR0_ELx flags for all ELs. No functional change intended. Signed-off-by: Fuad Tabba <tabba@google.com> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210817081134.2918285-10-tabba@google.com
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@ -602,14 +602,14 @@ static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
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{
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{
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u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT);
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u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT);
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return val == ID_AA64PFR0_EL1_32BIT_64BIT;
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return val == ID_AA64PFR0_ELx_32BIT_64BIT;
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}
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}
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static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
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static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
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{
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{
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u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
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u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
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return val == ID_AA64PFR0_EL0_32BIT_64BIT;
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return val == ID_AA64PFR0_ELx_32BIT_64BIT;
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}
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}
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static inline bool id_aa64pfr0_sve(u64 pfr0)
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static inline bool id_aa64pfr0_sve(u64 pfr0)
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@ -784,14 +784,13 @@
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#define ID_AA64PFR0_AMU 0x1
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#define ID_AA64PFR0_AMU 0x1
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#define ID_AA64PFR0_SVE 0x1
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#define ID_AA64PFR0_SVE 0x1
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#define ID_AA64PFR0_RAS_V1 0x1
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#define ID_AA64PFR0_RAS_V1 0x1
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#define ID_AA64PFR0_RAS_V1P1 0x2
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#define ID_AA64PFR0_FP_NI 0xf
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#define ID_AA64PFR0_FP_NI 0xf
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#define ID_AA64PFR0_FP_SUPPORTED 0x0
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#define ID_AA64PFR0_FP_SUPPORTED 0x0
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#define ID_AA64PFR0_ASIMD_NI 0xf
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#define ID_AA64PFR0_ASIMD_NI 0xf
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#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
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#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
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#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
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#define ID_AA64PFR0_ELx_64BIT_ONLY 0x1
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#define ID_AA64PFR0_EL1_32BIT_64BIT 0x2
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#define ID_AA64PFR0_ELx_32BIT_64BIT 0x2
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#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
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#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
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/* id_aa64pfr1 */
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/* id_aa64pfr1 */
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#define ID_AA64PFR1_MPAMFRAC_SHIFT 16
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#define ID_AA64PFR1_MPAMFRAC_SHIFT 16
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@ -847,12 +846,16 @@
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#define ID_AA64MMFR0_ASID_SHIFT 4
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#define ID_AA64MMFR0_ASID_SHIFT 4
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#define ID_AA64MMFR0_PARANGE_SHIFT 0
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#define ID_AA64MMFR0_PARANGE_SHIFT 0
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#define ID_AA64MMFR0_ASID_8 0x0
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#define ID_AA64MMFR0_ASID_16 0x2
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#define ID_AA64MMFR0_TGRAN4_NI 0xf
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#define ID_AA64MMFR0_TGRAN4_NI 0xf
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#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN64_NI 0xf
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#define ID_AA64MMFR0_TGRAN64_NI 0xf
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#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN16_NI 0x0
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#define ID_AA64MMFR0_TGRAN16_NI 0x0
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#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
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#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
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#define ID_AA64MMFR0_PARANGE_40 0x2
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#define ID_AA64MMFR0_PARANGE_48 0x5
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#define ID_AA64MMFR0_PARANGE_48 0x5
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#define ID_AA64MMFR0_PARANGE_52 0x6
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#define ID_AA64MMFR0_PARANGE_52 0x6
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@ -900,6 +903,7 @@
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#define ID_AA64MMFR2_CNP_SHIFT 0
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#define ID_AA64MMFR2_CNP_SHIFT 0
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/* id_aa64dfr0 */
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/* id_aa64dfr0 */
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#define ID_AA64DFR0_MTPMU_SHIFT 48
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#define ID_AA64DFR0_TRBE_SHIFT 44
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#define ID_AA64DFR0_TRBE_SHIFT 44
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#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
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#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
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#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
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#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
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@ -239,8 +239,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
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S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
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S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
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ARM64_FTR_END,
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ARM64_FTR_END,
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};
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};
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@ -1956,7 +1956,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.sign = FTR_UNSIGNED,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64PFR0_EL0_SHIFT,
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.field_pos = ID_AA64PFR0_EL0_SHIFT,
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.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
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.min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
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},
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},
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#ifdef CONFIG_KVM
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#ifdef CONFIG_KVM
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{
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{
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@ -1967,7 +1967,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.sign = FTR_UNSIGNED,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64PFR0_EL1_SHIFT,
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.field_pos = ID_AA64PFR0_EL1_SHIFT,
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.min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
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.min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
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},
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},
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{
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{
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.desc = "Protected KVM",
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.desc = "Protected KVM",
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