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arm64: tegra: Describe interconnect paths on Tegra186

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The interface used by clients of the memory controller can be configured
in a number of different ways. Describe this path using the interconnect
bindings to enable the configuration of these parameters.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2019-12-13 14:07:33 +01:00
parent b3fa0e03fa
commit 954490b30c
1 changed files with 55 additions and 1 deletions
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56
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -60,6 +60,9 @@
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
resets = <&bpmp TEGRA186_RESET_EQOS>;
reset-names = "eqos";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_EQOS>;
status = "disabled";
@ -139,12 +142,13 @@
};
};
memory-controller@2c00000 {
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0xb0000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#interconnect-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
@ -163,6 +167,8 @@
clocks = <&bpmp TEGRA186_CLK_EMC>;
clock-names = "emc";
#interconnect-cells = <0>;
nvidia,bpmp = <&bpmp>;
};
};
@ -335,6 +341,9 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC1>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
@ -361,6 +370,9 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC2>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC2>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc2_3v3>;
@ -382,6 +394,9 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC3>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc3_3v3>;
@ -408,6 +423,9 @@
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
resets = <&bpmp TEGRA186_RESET_SDMMC4>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
@ -436,6 +454,9 @@
<&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_HDA>;
status = "disabled";
};
@ -564,6 +585,9 @@
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
power-domain-names = "xusb_host", "xusb_ss";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
#address-cells = <1>;
#size-cells = <0>;
@ -786,6 +810,10 @@
<&bpmp TEGRA186_RESET_PCIEXCLK>;
reset-names = "afi", "pex", "pcie_x";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_AFI>;
iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
iommu-map-mask = <0x0>;
@ -921,6 +949,10 @@
#size-cells = <1>;
ranges = <0x15000000 0x0 0x15000000 0x01000000>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA186_SID_HOST1X>;
dpaux1: dpaux@15040000 {
@ -992,6 +1024,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
@ -1008,6 +1043,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
@ -1024,6 +1062,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1>;
@ -1056,6 +1097,9 @@
reset-names = "vic";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_VIC>;
};
@ -1211,6 +1255,11 @@
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
};
sysram@30000000 {
@ -1237,6 +1286,11 @@
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;