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ARM: dts: Configure omap5 OTG ID pin

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The ID pin GPIO comes from the PMIC. Let's configure it as a GPIO
for the driver to use, and also make sure the PMIC GPIO pin muxing
is correct. The PMIC pad1 and 2 values for omap5-uevm and igepv5 are
0x5a and 0x1b, we only need to clear bit 2 in pad1 register to make
the ID pin GPIO work.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2016-09-09 14:04:28 -07:00
parent 08f9268b2a
commit 952a5db0c0
2 changed files with 10 additions and 1 deletions
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9
arch/arm/boot/dts/omap5-board-common.dtsi
View File

@ -393,14 +393,23 @@
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
ti,mux-pad1 = <0xa1>;
ti,mux-pad2 = <0x1b>;
pinctrl-names = "default";
pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
palmas_gpio: gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
extcon_usb3: palmas_usb {
compatible = "ti,palmas-usb-vid";
ti,enable-vbus-detection;
ti,enable-id-detection;
ti,wakeup;
id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
};
clk32kgaudio: palmas_clk32k@1 {

2
arch/arm/boot/dts/omap5.dtsi
View File

@ -863,7 +863,7 @@
#size-cells = <1>;
utmi-mode = <2>;
ranges;
dwc3@4a030000 {
dwc3: dwc3@4a030000 {
compatible = "snps,dwc3";
reg = <0x4a030000 0x10000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,