forked from Minki/linux
sfc: Reduce RX scatter buffer size, and reduce alignment if appropriate
efx_start_datapath() asserts that we can fit 2 RX scatter buffers plus a software structure, each appropriately aligned, into a single page. Where L1_CACHE_BYTES == 256 and PAGE_SIZE == 4096, which is the case on s390, this assertion fails. The current scatter buffer size is also not a multiple of 64 or 128, which are more common cache line sizes. If we can make both the start and end of a scatter buffer cache-aligned, this will reduce the need for read-modify-write operations on inter- processor links. Fix the alignment by reducing EFX_RX_USR_BUF_SIZE to 2048 - 256 == 1792. (We could use 2048 - L1_CACHE_BYTES, but EFX_RX_USR_BUF_SIZE also affects user-level networking where a larger amount of housekeeping data may be needed. Although this version of the driver does not support user-level networking, I prefer to keep scattering behaviour consistent with the out-of-tree version.) This still doesn't fix the s390 build because like most architectures it has NET_IP_ALIGN == 2. When NET_IP_ALIGN != 0 we cannot achieve cache line alignment at either the start or end of a scatter buffer, so there is actually no point in padding the buffers to a multiple of the cache line size. All we need is 4-byte alignment of the network header, so do that. Adjust the assertions accordingly. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Reported-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -643,9 +643,11 @@ static void efx_start_datapath(struct efx_nic *efx)
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efx->rx_scatter = false;
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efx->rx_scatter = false;
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efx->rx_buffer_order = 0;
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efx->rx_buffer_order = 0;
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} else if (efx->type->can_rx_scatter) {
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} else if (efx->type->can_rx_scatter) {
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BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
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BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
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BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
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NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE >
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2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
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PAGE_SIZE / 2);
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EFX_RX_BUF_ALIGNMENT) >
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PAGE_SIZE);
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efx->rx_scatter = true;
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efx->rx_scatter = true;
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efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
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efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
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efx->rx_buffer_order = 0;
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efx->rx_buffer_order = 0;
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@ -72,8 +72,20 @@
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/* Maximum possible MTU the driver supports */
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/* Maximum possible MTU the driver supports */
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#define EFX_MAX_MTU (9 * 1024)
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#define EFX_MAX_MTU (9 * 1024)
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/* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page. */
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/* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
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#define EFX_RX_USR_BUF_SIZE 1824
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* and should be a multiple of the cache line size.
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*/
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#define EFX_RX_USR_BUF_SIZE (2048 - 256)
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/* If possible, we should ensure cache line alignment at start and end
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* of every buffer. Otherwise, we just need to ensure 4-byte
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* alignment of the network header.
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*/
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#if NET_IP_ALIGN == 0
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#define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
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#else
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#define EFX_RX_BUF_ALIGNMENT 4
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#endif
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/* Forward declare Precision Time Protocol (PTP) support structure. */
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/* Forward declare Precision Time Protocol (PTP) support structure. */
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struct efx_ptp_data;
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struct efx_ptp_data;
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@ -94,7 +94,7 @@ static inline void efx_sync_rx_buffer(struct efx_nic *efx,
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void efx_rx_config_page_split(struct efx_nic *efx)
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void efx_rx_config_page_split(struct efx_nic *efx)
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{
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{
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efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + NET_IP_ALIGN,
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efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + NET_IP_ALIGN,
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L1_CACHE_BYTES);
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EFX_RX_BUF_ALIGNMENT);
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efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
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efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
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((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
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((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
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efx->rx_page_buf_step);
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efx->rx_page_buf_step);
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