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drm/amd/pp: Refine pp_dpm_force_clock_level functions

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Only when user set manual performance mode, driver
enable pp_dpm_force_clock_level.
so check the mode in pp_dpm_force_clock_level,
and delete the same logic in callback functions.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-01-30 12:48:12 +08:00 committed by Alex Deucher
parent 6fa3ef3a9c
commit 948fd66c94
5 changed files with 5 additions and 17 deletions
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4
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
View File

@ -6639,9 +6639,7 @@ static int ci_dpm_force_clock_level(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev); struct ci_power_info *pi = ci_get_pi(adev);
if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO | if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL)
AMD_DPM_FORCED_LEVEL_LOW |
AMD_DPM_FORCED_LEVEL_HIGH))
return -EINVAL; return -EINVAL;
switch (type) { switch (type) {

5
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
View File

@ -839,7 +839,10 @@ static int pp_dpm_force_clock_level(void *handle,
return 0; return 0;
} }
mutex_lock(&pp_handle->pp_lock); mutex_lock(&pp_handle->pp_lock);
hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
else
ret = -EINVAL;
mutex_unlock(&pp_handle->pp_lock); mutex_unlock(&pp_handle->pp_lock);
return ret; return ret;
} }

3
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
View File

@ -1558,9 +1558,6 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
static int cz_force_clock_level(struct pp_hwmgr *hwmgr, static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask) enum pp_clock_type type, uint32_t mask)
{ {
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
return -EINVAL;
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
smum_send_msg_to_smc_with_parameter(hwmgr, smum_send_msg_to_smc_with_parameter(hwmgr,

5
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -4296,11 +4296,6 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
{ {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
AMD_DPM_FORCED_LEVEL_LOW |
AMD_DPM_FORCED_LEVEL_HIGH))
return -EINVAL;
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
if (!data->sclk_dpm_key_disabled) if (!data->sclk_dpm_key_disabled)

5
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View File

@ -4500,11 +4500,6 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
{ {
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
AMD_DPM_FORCED_LEVEL_LOW |
AMD_DPM_FORCED_LEVEL_HIGH))
return -EINVAL;
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;